mx6-ddr.h 4.9 KB

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  1. /*
  2. * Copyright (C) 2013 Boundary Devices Inc.
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. */
  6. #ifndef __ASM_ARCH_MX6_DDR_H__
  7. #define __ASM_ARCH_MX6_DDR_H__
  8. #ifndef CONFIG_SPL_BUILD
  9. #ifdef CONFIG_MX6Q
  10. #include "mx6q-ddr.h"
  11. #else
  12. #if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
  13. #include "mx6dl-ddr.h"
  14. #else
  15. #error "Please select cpu"
  16. #endif /* CONFIG_MX6DL or CONFIG_MX6S */
  17. #endif /* CONFIG_MX6Q */
  18. #else
  19. /* MMDC P0/P1 Registers */
  20. struct mmdc_p_regs {
  21. u32 mdctl;
  22. u32 mdpdc;
  23. u32 mdotc;
  24. u32 mdcfg0;
  25. u32 mdcfg1;
  26. u32 mdcfg2;
  27. u32 mdmisc;
  28. u32 mdscr;
  29. u32 mdref;
  30. u32 res1[2];
  31. u32 mdrwd;
  32. u32 mdor;
  33. u32 res2[3];
  34. u32 mdasp;
  35. u32 res3[240];
  36. u32 mapsr;
  37. u32 res4[254];
  38. u32 mpzqhwctrl;
  39. u32 res5[2];
  40. u32 mpwldectrl0;
  41. u32 mpwldectrl1;
  42. u32 res6;
  43. u32 mpodtctrl;
  44. u32 mprddqby0dl;
  45. u32 mprddqby1dl;
  46. u32 mprddqby2dl;
  47. u32 mprddqby3dl;
  48. u32 res7[4];
  49. u32 mpdgctrl0;
  50. u32 mpdgctrl1;
  51. u32 res8;
  52. u32 mprddlctl;
  53. u32 res9;
  54. u32 mpwrdlctl;
  55. u32 res10[25];
  56. u32 mpmur0;
  57. };
  58. /*
  59. * MMDC iomux registers (pinctl/padctl) - (different for IMX6DQ vs IMX6SDL)
  60. */
  61. #define MX6DQ_IOM_DDR_BASE 0x020e0500
  62. struct mx6dq_iomux_ddr_regs {
  63. u32 res1[3];
  64. u32 dram_sdqs5;
  65. u32 dram_dqm5;
  66. u32 dram_dqm4;
  67. u32 dram_sdqs4;
  68. u32 dram_sdqs3;
  69. u32 dram_dqm3;
  70. u32 dram_sdqs2;
  71. u32 dram_dqm2;
  72. u32 res2[16];
  73. u32 dram_cas;
  74. u32 res3[2];
  75. u32 dram_ras;
  76. u32 dram_reset;
  77. u32 res4[2];
  78. u32 dram_sdclk_0;
  79. u32 dram_sdba2;
  80. u32 dram_sdcke0;
  81. u32 dram_sdclk_1;
  82. u32 dram_sdcke1;
  83. u32 dram_sdodt0;
  84. u32 dram_sdodt1;
  85. u32 res5;
  86. u32 dram_sdqs0;
  87. u32 dram_dqm0;
  88. u32 dram_sdqs1;
  89. u32 dram_dqm1;
  90. u32 dram_sdqs6;
  91. u32 dram_dqm6;
  92. u32 dram_sdqs7;
  93. u32 dram_dqm7;
  94. };
  95. #define MX6DQ_IOM_GRP_BASE 0x020e0700
  96. struct mx6dq_iomux_grp_regs {
  97. u32 res1[18];
  98. u32 grp_b7ds;
  99. u32 grp_addds;
  100. u32 grp_ddrmode_ctl;
  101. u32 res2;
  102. u32 grp_ddrpke;
  103. u32 res3[6];
  104. u32 grp_ddrmode;
  105. u32 res4[3];
  106. u32 grp_b0ds;
  107. u32 grp_b1ds;
  108. u32 grp_ctlds;
  109. u32 res5;
  110. u32 grp_b2ds;
  111. u32 grp_ddr_type;
  112. u32 grp_b3ds;
  113. u32 grp_b4ds;
  114. u32 grp_b5ds;
  115. u32 grp_b6ds;
  116. };
  117. #define MX6SDL_IOM_DDR_BASE 0x020e0400
  118. struct mx6sdl_iomux_ddr_regs {
  119. u32 res1[25];
  120. u32 dram_cas;
  121. u32 res2[2];
  122. u32 dram_dqm0;
  123. u32 dram_dqm1;
  124. u32 dram_dqm2;
  125. u32 dram_dqm3;
  126. u32 dram_dqm4;
  127. u32 dram_dqm5;
  128. u32 dram_dqm6;
  129. u32 dram_dqm7;
  130. u32 dram_ras;
  131. u32 dram_reset;
  132. u32 res3[2];
  133. u32 dram_sdba2;
  134. u32 dram_sdcke0;
  135. u32 dram_sdcke1;
  136. u32 dram_sdclk_0;
  137. u32 dram_sdclk_1;
  138. u32 dram_sdodt0;
  139. u32 dram_sdodt1;
  140. u32 dram_sdqs0;
  141. u32 dram_sdqs1;
  142. u32 dram_sdqs2;
  143. u32 dram_sdqs3;
  144. u32 dram_sdqs4;
  145. u32 dram_sdqs5;
  146. u32 dram_sdqs6;
  147. u32 dram_sdqs7;
  148. };
  149. #define MX6SDL_IOM_GRP_BASE 0x020e0700
  150. struct mx6sdl_iomux_grp_regs {
  151. u32 res1[18];
  152. u32 grp_b7ds;
  153. u32 grp_addds;
  154. u32 grp_ddrmode_ctl;
  155. u32 grp_ddrpke;
  156. u32 res2[2];
  157. u32 grp_ddrmode;
  158. u32 grp_b0ds;
  159. u32 res3;
  160. u32 grp_ctlds;
  161. u32 grp_b1ds;
  162. u32 grp_ddr_type;
  163. u32 grp_b2ds;
  164. u32 grp_b3ds;
  165. u32 grp_b4ds;
  166. u32 grp_b5ds;
  167. u32 res4;
  168. u32 grp_b6ds;
  169. };
  170. #endif /* CONFIG_SPL_BUILD */
  171. #define MX6_MMDC_P0_MDCTL 0x021b0000
  172. #define MX6_MMDC_P0_MDPDC 0x021b0004
  173. #define MX6_MMDC_P0_MDOTC 0x021b0008
  174. #define MX6_MMDC_P0_MDCFG0 0x021b000c
  175. #define MX6_MMDC_P0_MDCFG1 0x021b0010
  176. #define MX6_MMDC_P0_MDCFG2 0x021b0014
  177. #define MX6_MMDC_P0_MDMISC 0x021b0018
  178. #define MX6_MMDC_P0_MDSCR 0x021b001c
  179. #define MX6_MMDC_P0_MDREF 0x021b0020
  180. #define MX6_MMDC_P0_MDRWD 0x021b002c
  181. #define MX6_MMDC_P0_MDOR 0x021b0030
  182. #define MX6_MMDC_P0_MDASP 0x021b0040
  183. #define MX6_MMDC_P0_MAPSR 0x021b0404
  184. #define MX6_MMDC_P0_MPZQHWCTRL 0x021b0800
  185. #define MX6_MMDC_P0_MPWLDECTRL0 0x021b080c
  186. #define MX6_MMDC_P0_MPWLDECTRL1 0x021b0810
  187. #define MX6_MMDC_P0_MPODTCTRL 0x021b0818
  188. #define MX6_MMDC_P0_MPRDDQBY0DL 0x021b081c
  189. #define MX6_MMDC_P0_MPRDDQBY1DL 0x021b0820
  190. #define MX6_MMDC_P0_MPRDDQBY2DL 0x021b0824
  191. #define MX6_MMDC_P0_MPRDDQBY3DL 0x021b0828
  192. #define MX6_MMDC_P0_MPDGCTRL0 0x021b083c
  193. #define MX6_MMDC_P0_MPDGCTRL1 0x021b0840
  194. #define MX6_MMDC_P0_MPRDDLCTL 0x021b0848
  195. #define MX6_MMDC_P0_MPWRDLCTL 0x021b0850
  196. #define MX6_MMDC_P0_MPMUR0 0x021b08b8
  197. #define MX6_MMDC_P1_MDCTL 0x021b4000
  198. #define MX6_MMDC_P1_MDPDC 0x021b4004
  199. #define MX6_MMDC_P1_MDOTC 0x021b4008
  200. #define MX6_MMDC_P1_MDCFG0 0x021b400c
  201. #define MX6_MMDC_P1_MDCFG1 0x021b4010
  202. #define MX6_MMDC_P1_MDCFG2 0x021b4014
  203. #define MX6_MMDC_P1_MDMISC 0x021b4018
  204. #define MX6_MMDC_P1_MDSCR 0x021b401c
  205. #define MX6_MMDC_P1_MDREF 0x021b4020
  206. #define MX6_MMDC_P1_MDRWD 0x021b402c
  207. #define MX6_MMDC_P1_MDOR 0x021b4030
  208. #define MX6_MMDC_P1_MDASP 0x021b4040
  209. #define MX6_MMDC_P1_MAPSR 0x021b4404
  210. #define MX6_MMDC_P1_MPZQHWCTRL 0x021b4800
  211. #define MX6_MMDC_P1_MPWLDECTRL0 0x021b480c
  212. #define MX6_MMDC_P1_MPWLDECTRL1 0x021b4810
  213. #define MX6_MMDC_P1_MPODTCTRL 0x021b4818
  214. #define MX6_MMDC_P1_MPRDDQBY0DL 0x021b481c
  215. #define MX6_MMDC_P1_MPRDDQBY1DL 0x021b4820
  216. #define MX6_MMDC_P1_MPRDDQBY2DL 0x021b4824
  217. #define MX6_MMDC_P1_MPRDDQBY3DL 0x021b4828
  218. #define MX6_MMDC_P1_MPDGCTRL0 0x021b483c
  219. #define MX6_MMDC_P1_MPDGCTRL1 0x021b4840
  220. #define MX6_MMDC_P1_MPRDDLCTL 0x021b4848
  221. #define MX6_MMDC_P1_MPWRDLCTL 0x021b4850
  222. #define MX6_MMDC_P1_MPMUR0 0x021b48b8
  223. #endif /*__ASM_ARCH_MX6_DDR_H__ */