mpc8308rdb.c 4.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2010 Freescale Semiconductor, Inc.
  4. * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
  5. */
  6. #include <common.h>
  7. #include <hwconfig.h>
  8. #include <i2c.h>
  9. #include <spi.h>
  10. #include <linux/libfdt.h>
  11. #include <fdt_support.h>
  12. #include <pci.h>
  13. #include <mpc83xx.h>
  14. #include <vsc7385.h>
  15. #include <netdev.h>
  16. #include <fsl_esdhc.h>
  17. #include <asm/io.h>
  18. #include <asm/fsl_serdes.h>
  19. #include <asm/fsl_mpc83xx_serdes.h>
  20. /*
  21. * The following are used to control the SPI chip selects for the SPI command.
  22. */
  23. #ifdef CONFIG_MPC8XXX_SPI
  24. #define SPI_CS_MASK 0x00400000
  25. int spi_cs_is_valid(unsigned int bus, unsigned int cs)
  26. {
  27. return bus == 0 && cs == 0;
  28. }
  29. void spi_cs_activate(struct spi_slave *slave)
  30. {
  31. immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
  32. /* active low */
  33. clrbits_be32(&immr->gpio[0].dat, SPI_CS_MASK);
  34. }
  35. void spi_cs_deactivate(struct spi_slave *slave)
  36. {
  37. immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
  38. /* inactive high */
  39. setbits_be32(&immr->gpio[0].dat, SPI_CS_MASK);
  40. }
  41. #endif /* CONFIG_MPC8XXX_SPI */
  42. #ifdef CONFIG_FSL_ESDHC
  43. int board_mmc_init(bd_t *bd)
  44. {
  45. return fsl_esdhc_mmc_init(bd);
  46. }
  47. #endif
  48. static u8 read_board_info(void)
  49. {
  50. u8 val8;
  51. i2c_set_bus_num(0);
  52. if (i2c_read(CONFIG_SYS_I2C_PCF8574A_ADDR, 0, 0, &val8, 1) == 0)
  53. return val8;
  54. else
  55. return 0;
  56. }
  57. int checkboard(void)
  58. {
  59. static const char * const rev_str[] = {
  60. "1.0",
  61. "<reserved>",
  62. "<reserved>",
  63. "<reserved>",
  64. "<unknown>",
  65. };
  66. u8 info;
  67. int i;
  68. info = read_board_info();
  69. i = (!info) ? 4 : info & 0x03;
  70. printf("Board: Freescale MPC8308RDB Rev %s\n", rev_str[i]);
  71. return 0;
  72. }
  73. static struct pci_region pcie_regions_0[] = {
  74. {
  75. .bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
  76. .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
  77. .size = CONFIG_SYS_PCIE1_MEM_SIZE,
  78. .flags = PCI_REGION_MEM,
  79. },
  80. {
  81. .bus_start = CONFIG_SYS_PCIE1_IO_BASE,
  82. .phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
  83. .size = CONFIG_SYS_PCIE1_IO_SIZE,
  84. .flags = PCI_REGION_IO,
  85. },
  86. };
  87. void pci_init_board(void)
  88. {
  89. immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
  90. sysconf83xx_t *sysconf = &immr->sysconf;
  91. law83xx_t *pcie_law = sysconf->pcielaw;
  92. struct pci_region *pcie_reg[] = { pcie_regions_0 };
  93. fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX,
  94. FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
  95. /* Deassert the resets in the control register */
  96. out_be32(&sysconf->pecr1, 0xE0008000);
  97. udelay(2000);
  98. /* Configure PCI Express Local Access Windows */
  99. out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
  100. out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
  101. mpc83xx_pcie_init(1, pcie_reg);
  102. }
  103. /*
  104. * Miscellaneous late-boot configurations
  105. *
  106. * If a VSC7385 microcode image is present, then upload it.
  107. */
  108. int misc_init_r(void)
  109. {
  110. #ifdef CONFIG_MPC8XXX_SPI
  111. immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
  112. sysconf83xx_t *sysconf = &immr->sysconf;
  113. /*
  114. * Set proper bits in SICRH to allow SPI on header J8
  115. *
  116. * NOTE: this breaks the TSEC2 interface, attached to the Vitesse
  117. * switch. The pinmux configuration does not have a fine enough
  118. * granularity to support both simultaneously.
  119. */
  120. clrsetbits_be32(&sysconf->sicrh, SICRH_GPIO_A_TSEC2, SICRH_GPIO_A_GPIO);
  121. puts("WARNING: SPI enabled, TSEC2 support is broken\n");
  122. /* Set header J8 SPI chip select output, disabled */
  123. setbits_be32(&immr->gpio[0].dir, SPI_CS_MASK);
  124. setbits_be32(&immr->gpio[0].dat, SPI_CS_MASK);
  125. #endif
  126. #ifdef CONFIG_VSC7385_IMAGE
  127. if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
  128. CONFIG_VSC7385_IMAGE_SIZE)) {
  129. puts("Failure uploading VSC7385 microcode.\n");
  130. return 1;
  131. }
  132. #endif
  133. return 0;
  134. }
  135. #if defined(CONFIG_OF_BOARD_SETUP)
  136. int ft_board_setup(void *blob, bd_t *bd)
  137. {
  138. ft_cpu_setup(blob, bd);
  139. fsl_fdt_fixup_dr_usb(blob, bd);
  140. fdt_fixup_esdhc(blob, bd);
  141. return 0;
  142. }
  143. #endif
  144. int board_eth_init(bd_t *bis)
  145. {
  146. int rv, num_if = 0;
  147. /* Initialize TSECs first */
  148. rv = cpu_eth_init(bis);
  149. if (rv >= 0)
  150. num_if += rv;
  151. else
  152. printf("ERROR: failed to initialize TSECs.\n");
  153. rv = pci_eth_init(bis);
  154. if (rv >= 0)
  155. num_if += rv;
  156. else
  157. printf("ERROR: failed to initialize PCI Ethernet.\n");
  158. return num_if;
  159. }