stm32_qspi.c 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2016
  4. *
  5. * Michael Kurz, <michi.kurz@gmail.com>
  6. *
  7. * STM32 QSPI driver
  8. */
  9. #include <common.h>
  10. #include <clk.h>
  11. #include <dm.h>
  12. #include <errno.h>
  13. #include <malloc.h>
  14. #include <spi.h>
  15. #include <spi_flash.h>
  16. #include <asm/io.h>
  17. #include <asm/arch/stm32.h>
  18. DECLARE_GLOBAL_DATA_PTR;
  19. struct stm32_qspi_regs {
  20. u32 cr; /* 0x00 */
  21. u32 dcr; /* 0x04 */
  22. u32 sr; /* 0x08 */
  23. u32 fcr; /* 0x0C */
  24. u32 dlr; /* 0x10 */
  25. u32 ccr; /* 0x14 */
  26. u32 ar; /* 0x18 */
  27. u32 abr; /* 0x1C */
  28. u32 dr; /* 0x20 */
  29. u32 psmkr; /* 0x24 */
  30. u32 psmar; /* 0x28 */
  31. u32 pir; /* 0x2C */
  32. u32 lptr; /* 0x30 */
  33. };
  34. /*
  35. * QUADSPI control register
  36. */
  37. #define STM32_QSPI_CR_EN BIT(0)
  38. #define STM32_QSPI_CR_ABORT BIT(1)
  39. #define STM32_QSPI_CR_DMAEN BIT(2)
  40. #define STM32_QSPI_CR_TCEN BIT(3)
  41. #define STM32_QSPI_CR_SSHIFT BIT(4)
  42. #define STM32_QSPI_CR_DFM BIT(6)
  43. #define STM32_QSPI_CR_FSEL BIT(7)
  44. #define STM32_QSPI_CR_FTHRES_MASK GENMASK(4, 0)
  45. #define STM32_QSPI_CR_FTHRES_SHIFT (8)
  46. #define STM32_QSPI_CR_TEIE BIT(16)
  47. #define STM32_QSPI_CR_TCIE BIT(17)
  48. #define STM32_QSPI_CR_FTIE BIT(18)
  49. #define STM32_QSPI_CR_SMIE BIT(19)
  50. #define STM32_QSPI_CR_TOIE BIT(20)
  51. #define STM32_QSPI_CR_APMS BIT(22)
  52. #define STM32_QSPI_CR_PMM BIT(23)
  53. #define STM32_QSPI_CR_PRESCALER_MASK GENMASK(7, 0)
  54. #define STM32_QSPI_CR_PRESCALER_SHIFT (24)
  55. /*
  56. * QUADSPI device configuration register
  57. */
  58. #define STM32_QSPI_DCR_CKMODE BIT(0)
  59. #define STM32_QSPI_DCR_CSHT_MASK GENMASK(2, 0)
  60. #define STM32_QSPI_DCR_CSHT_SHIFT (8)
  61. #define STM32_QSPI_DCR_FSIZE_MASK GENMASK(4, 0)
  62. #define STM32_QSPI_DCR_FSIZE_SHIFT (16)
  63. /*
  64. * QUADSPI status register
  65. */
  66. #define STM32_QSPI_SR_TEF BIT(0)
  67. #define STM32_QSPI_SR_TCF BIT(1)
  68. #define STM32_QSPI_SR_FTF BIT(2)
  69. #define STM32_QSPI_SR_SMF BIT(3)
  70. #define STM32_QSPI_SR_TOF BIT(4)
  71. #define STM32_QSPI_SR_BUSY BIT(5)
  72. #define STM32_QSPI_SR_FLEVEL_MASK GENMASK(5, 0)
  73. #define STM32_QSPI_SR_FLEVEL_SHIFT (8)
  74. /*
  75. * QUADSPI flag clear register
  76. */
  77. #define STM32_QSPI_FCR_CTEF BIT(0)
  78. #define STM32_QSPI_FCR_CTCF BIT(1)
  79. #define STM32_QSPI_FCR_CSMF BIT(3)
  80. #define STM32_QSPI_FCR_CTOF BIT(4)
  81. /*
  82. * QUADSPI communication configuration register
  83. */
  84. #define STM32_QSPI_CCR_DDRM BIT(31)
  85. #define STM32_QSPI_CCR_DHHC BIT(30)
  86. #define STM32_QSPI_CCR_SIOO BIT(28)
  87. #define STM32_QSPI_CCR_FMODE_SHIFT (26)
  88. #define STM32_QSPI_CCR_DMODE_SHIFT (24)
  89. #define STM32_QSPI_CCR_DCYC_SHIFT (18)
  90. #define STM32_QSPI_CCR_DCYC_MASK GENMASK(4, 0)
  91. #define STM32_QSPI_CCR_ABSIZE_SHIFT (16)
  92. #define STM32_QSPI_CCR_ABMODE_SHIFT (14)
  93. #define STM32_QSPI_CCR_ADSIZE_SHIFT (12)
  94. #define STM32_QSPI_CCR_ADMODE_SHIFT (10)
  95. #define STM32_QSPI_CCR_IMODE_SHIFT (8)
  96. #define STM32_QSPI_CCR_INSTRUCTION_MASK GENMASK(7, 0)
  97. enum STM32_QSPI_CCR_IMODE {
  98. STM32_QSPI_CCR_IMODE_NONE = 0,
  99. STM32_QSPI_CCR_IMODE_ONE_LINE = 1,
  100. STM32_QSPI_CCR_IMODE_TWO_LINE = 2,
  101. STM32_QSPI_CCR_IMODE_FOUR_LINE = 3,
  102. };
  103. enum STM32_QSPI_CCR_ADMODE {
  104. STM32_QSPI_CCR_ADMODE_NONE = 0,
  105. STM32_QSPI_CCR_ADMODE_ONE_LINE = 1,
  106. STM32_QSPI_CCR_ADMODE_TWO_LINE = 2,
  107. STM32_QSPI_CCR_ADMODE_FOUR_LINE = 3,
  108. };
  109. enum STM32_QSPI_CCR_ADSIZE {
  110. STM32_QSPI_CCR_ADSIZE_8BIT = 0,
  111. STM32_QSPI_CCR_ADSIZE_16BIT = 1,
  112. STM32_QSPI_CCR_ADSIZE_24BIT = 2,
  113. STM32_QSPI_CCR_ADSIZE_32BIT = 3,
  114. };
  115. enum STM32_QSPI_CCR_ABMODE {
  116. STM32_QSPI_CCR_ABMODE_NONE = 0,
  117. STM32_QSPI_CCR_ABMODE_ONE_LINE = 1,
  118. STM32_QSPI_CCR_ABMODE_TWO_LINE = 2,
  119. STM32_QSPI_CCR_ABMODE_FOUR_LINE = 3,
  120. };
  121. enum STM32_QSPI_CCR_ABSIZE {
  122. STM32_QSPI_CCR_ABSIZE_8BIT = 0,
  123. STM32_QSPI_CCR_ABSIZE_16BIT = 1,
  124. STM32_QSPI_CCR_ABSIZE_24BIT = 2,
  125. STM32_QSPI_CCR_ABSIZE_32BIT = 3,
  126. };
  127. enum STM32_QSPI_CCR_DMODE {
  128. STM32_QSPI_CCR_DMODE_NONE = 0,
  129. STM32_QSPI_CCR_DMODE_ONE_LINE = 1,
  130. STM32_QSPI_CCR_DMODE_TWO_LINE = 2,
  131. STM32_QSPI_CCR_DMODE_FOUR_LINE = 3,
  132. };
  133. enum STM32_QSPI_CCR_FMODE {
  134. STM32_QSPI_CCR_IND_WRITE = 0,
  135. STM32_QSPI_CCR_IND_READ = 1,
  136. STM32_QSPI_CCR_AUTO_POLL = 2,
  137. STM32_QSPI_CCR_MEM_MAP = 3,
  138. };
  139. /* default SCK frequency, unit: HZ */
  140. #define STM32_QSPI_DEFAULT_SCK_FREQ 108000000
  141. struct stm32_qspi_platdata {
  142. u32 base;
  143. u32 memory_map;
  144. u32 max_hz;
  145. };
  146. struct stm32_qspi_priv {
  147. struct stm32_qspi_regs *regs;
  148. ulong clock_rate;
  149. u32 max_hz;
  150. u32 mode;
  151. u32 command;
  152. u32 address;
  153. u32 dummycycles;
  154. #define CMD_HAS_ADR BIT(24)
  155. #define CMD_HAS_DUMMY BIT(25)
  156. #define CMD_HAS_DATA BIT(26)
  157. };
  158. static void _stm32_qspi_disable(struct stm32_qspi_priv *priv)
  159. {
  160. clrbits_le32(&priv->regs->cr, STM32_QSPI_CR_EN);
  161. }
  162. static void _stm32_qspi_enable(struct stm32_qspi_priv *priv)
  163. {
  164. setbits_le32(&priv->regs->cr, STM32_QSPI_CR_EN);
  165. }
  166. static void _stm32_qspi_wait_for_not_busy(struct stm32_qspi_priv *priv)
  167. {
  168. while (readl(&priv->regs->sr) & STM32_QSPI_SR_BUSY)
  169. ;
  170. }
  171. static void _stm32_qspi_wait_for_complete(struct stm32_qspi_priv *priv)
  172. {
  173. while (!(readl(&priv->regs->sr) & STM32_QSPI_SR_TCF))
  174. ;
  175. }
  176. static void _stm32_qspi_wait_for_ftf(struct stm32_qspi_priv *priv)
  177. {
  178. while (!(readl(&priv->regs->sr) & STM32_QSPI_SR_FTF))
  179. ;
  180. }
  181. static void _stm32_qspi_set_flash_size(struct stm32_qspi_priv *priv, u32 size)
  182. {
  183. u32 fsize = fls(size) - 1;
  184. clrsetbits_le32(&priv->regs->dcr,
  185. STM32_QSPI_DCR_FSIZE_MASK << STM32_QSPI_DCR_FSIZE_SHIFT,
  186. fsize << STM32_QSPI_DCR_FSIZE_SHIFT);
  187. }
  188. static unsigned int _stm32_qspi_gen_ccr(struct stm32_qspi_priv *priv)
  189. {
  190. unsigned int ccr_reg = 0;
  191. u8 imode, admode, dmode;
  192. u32 mode = priv->mode;
  193. u32 cmd = (priv->command & STM32_QSPI_CCR_INSTRUCTION_MASK);
  194. imode = STM32_QSPI_CCR_IMODE_ONE_LINE;
  195. admode = STM32_QSPI_CCR_ADMODE_ONE_LINE;
  196. if (mode & SPI_RX_QUAD) {
  197. dmode = STM32_QSPI_CCR_DMODE_FOUR_LINE;
  198. if (mode & SPI_TX_QUAD) {
  199. imode = STM32_QSPI_CCR_IMODE_FOUR_LINE;
  200. admode = STM32_QSPI_CCR_ADMODE_FOUR_LINE;
  201. }
  202. } else if (mode & SPI_RX_DUAL) {
  203. dmode = STM32_QSPI_CCR_DMODE_TWO_LINE;
  204. if (mode & SPI_TX_DUAL) {
  205. imode = STM32_QSPI_CCR_IMODE_TWO_LINE;
  206. admode = STM32_QSPI_CCR_ADMODE_TWO_LINE;
  207. }
  208. } else {
  209. dmode = STM32_QSPI_CCR_DMODE_ONE_LINE;
  210. }
  211. if (priv->command & CMD_HAS_DATA)
  212. ccr_reg |= (dmode << STM32_QSPI_CCR_DMODE_SHIFT);
  213. if (priv->command & CMD_HAS_DUMMY)
  214. ccr_reg |= ((priv->dummycycles & STM32_QSPI_CCR_DCYC_MASK)
  215. << STM32_QSPI_CCR_DCYC_SHIFT);
  216. if (priv->command & CMD_HAS_ADR) {
  217. ccr_reg |= (STM32_QSPI_CCR_ADSIZE_24BIT
  218. << STM32_QSPI_CCR_ADSIZE_SHIFT);
  219. ccr_reg |= (admode << STM32_QSPI_CCR_ADMODE_SHIFT);
  220. }
  221. ccr_reg |= (imode << STM32_QSPI_CCR_IMODE_SHIFT);
  222. ccr_reg |= cmd;
  223. return ccr_reg;
  224. }
  225. static void _stm32_qspi_enable_mmap(struct stm32_qspi_priv *priv,
  226. struct spi_flash *flash)
  227. {
  228. unsigned int ccr_reg;
  229. priv->command = flash->read_cmd | CMD_HAS_ADR | CMD_HAS_DATA
  230. | CMD_HAS_DUMMY;
  231. priv->dummycycles = flash->dummy_byte * 8;
  232. ccr_reg = _stm32_qspi_gen_ccr(priv);
  233. ccr_reg |= (STM32_QSPI_CCR_MEM_MAP << STM32_QSPI_CCR_FMODE_SHIFT);
  234. _stm32_qspi_wait_for_not_busy(priv);
  235. writel(ccr_reg, &priv->regs->ccr);
  236. priv->dummycycles = 0;
  237. }
  238. static void _stm32_qspi_disable_mmap(struct stm32_qspi_priv *priv)
  239. {
  240. setbits_le32(&priv->regs->cr, STM32_QSPI_CR_ABORT);
  241. }
  242. static void _stm32_qspi_set_xfer_length(struct stm32_qspi_priv *priv,
  243. u32 length)
  244. {
  245. writel(length - 1, &priv->regs->dlr);
  246. }
  247. static void _stm32_qspi_start_xfer(struct stm32_qspi_priv *priv, u32 cr_reg)
  248. {
  249. writel(cr_reg, &priv->regs->ccr);
  250. if (priv->command & CMD_HAS_ADR)
  251. writel(priv->address, &priv->regs->ar);
  252. }
  253. static int _stm32_qspi_xfer(struct stm32_qspi_priv *priv,
  254. struct spi_flash *flash, unsigned int bitlen,
  255. const u8 *dout, u8 *din, unsigned long flags)
  256. {
  257. unsigned int words = bitlen / 8;
  258. u32 ccr_reg;
  259. int i;
  260. if (flags & SPI_XFER_MMAP) {
  261. _stm32_qspi_enable_mmap(priv, flash);
  262. return 0;
  263. } else if (flags & SPI_XFER_MMAP_END) {
  264. _stm32_qspi_disable_mmap(priv);
  265. return 0;
  266. }
  267. if (bitlen == 0)
  268. return -1;
  269. if (bitlen % 8) {
  270. debug("spi_xfer: Non byte aligned SPI transfer\n");
  271. return -1;
  272. }
  273. if (dout && din) {
  274. debug("spi_xfer: QSPI cannot have data in and data out set\n");
  275. return -1;
  276. }
  277. if (!dout && (flags & SPI_XFER_BEGIN)) {
  278. debug("spi_xfer: QSPI transfer must begin with command\n");
  279. return -1;
  280. }
  281. if (dout) {
  282. if (flags & SPI_XFER_BEGIN) {
  283. /* data is command */
  284. priv->command = dout[0] | CMD_HAS_DATA;
  285. if (words >= 4) {
  286. /* address is here too */
  287. priv->address = (dout[1] << 16) |
  288. (dout[2] << 8) | dout[3];
  289. priv->command |= CMD_HAS_ADR;
  290. }
  291. if (words > 4) {
  292. /* rest is dummy bytes */
  293. priv->dummycycles = (words - 4) * 8;
  294. priv->command |= CMD_HAS_DUMMY;
  295. }
  296. if (flags & SPI_XFER_END) {
  297. /* command without data */
  298. priv->command &= ~(CMD_HAS_DATA);
  299. }
  300. }
  301. if (flags & SPI_XFER_END) {
  302. ccr_reg = _stm32_qspi_gen_ccr(priv);
  303. ccr_reg |= STM32_QSPI_CCR_IND_WRITE
  304. << STM32_QSPI_CCR_FMODE_SHIFT;
  305. _stm32_qspi_wait_for_not_busy(priv);
  306. if (priv->command & CMD_HAS_DATA)
  307. _stm32_qspi_set_xfer_length(priv, words);
  308. _stm32_qspi_start_xfer(priv, ccr_reg);
  309. debug("%s: write: ccr:0x%08x adr:0x%08x\n",
  310. __func__, priv->regs->ccr, priv->regs->ar);
  311. if (priv->command & CMD_HAS_DATA) {
  312. _stm32_qspi_wait_for_ftf(priv);
  313. debug("%s: words:%d data:", __func__, words);
  314. i = 0;
  315. while (words > i) {
  316. writeb(dout[i], &priv->regs->dr);
  317. debug("%02x ", dout[i]);
  318. i++;
  319. }
  320. debug("\n");
  321. _stm32_qspi_wait_for_complete(priv);
  322. } else {
  323. _stm32_qspi_wait_for_not_busy(priv);
  324. }
  325. }
  326. } else if (din) {
  327. ccr_reg = _stm32_qspi_gen_ccr(priv);
  328. ccr_reg |= STM32_QSPI_CCR_IND_READ
  329. << STM32_QSPI_CCR_FMODE_SHIFT;
  330. _stm32_qspi_wait_for_not_busy(priv);
  331. _stm32_qspi_set_xfer_length(priv, words);
  332. _stm32_qspi_start_xfer(priv, ccr_reg);
  333. debug("%s: read: ccr:0x%08x adr:0x%08x len:%d\n", __func__,
  334. priv->regs->ccr, priv->regs->ar, priv->regs->dlr);
  335. debug("%s: data:", __func__);
  336. i = 0;
  337. while (words > i) {
  338. din[i] = readb(&priv->regs->dr);
  339. debug("%02x ", din[i]);
  340. i++;
  341. }
  342. debug("\n");
  343. }
  344. return 0;
  345. }
  346. static int stm32_qspi_ofdata_to_platdata(struct udevice *bus)
  347. {
  348. struct fdt_resource res_regs, res_mem;
  349. struct stm32_qspi_platdata *plat = bus->platdata;
  350. const void *blob = gd->fdt_blob;
  351. int node = dev_of_offset(bus);
  352. int ret;
  353. ret = fdt_get_named_resource(blob, node, "reg", "reg-names",
  354. "QuadSPI", &res_regs);
  355. if (ret) {
  356. debug("Error: can't get regs base addresses(ret = %d)!\n", ret);
  357. return -ENOMEM;
  358. }
  359. ret = fdt_get_named_resource(blob, node, "reg", "reg-names",
  360. "QuadSPI-memory", &res_mem);
  361. if (ret) {
  362. debug("Error: can't get mmap base address(ret = %d)!\n", ret);
  363. return -ENOMEM;
  364. }
  365. plat->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency",
  366. STM32_QSPI_DEFAULT_SCK_FREQ);
  367. plat->base = res_regs.start;
  368. plat->memory_map = res_mem.start;
  369. debug("%s: regs=<0x%x> mapped=<0x%x>, max-frequency=%d\n",
  370. __func__,
  371. plat->base,
  372. plat->memory_map,
  373. plat->max_hz
  374. );
  375. return 0;
  376. }
  377. static int stm32_qspi_probe(struct udevice *bus)
  378. {
  379. struct stm32_qspi_platdata *plat = dev_get_platdata(bus);
  380. struct stm32_qspi_priv *priv = dev_get_priv(bus);
  381. struct dm_spi_bus *dm_spi_bus;
  382. struct clk clk;
  383. int ret;
  384. dm_spi_bus = bus->uclass_priv;
  385. dm_spi_bus->max_hz = plat->max_hz;
  386. priv->regs = (struct stm32_qspi_regs *)(uintptr_t)plat->base;
  387. priv->max_hz = plat->max_hz;
  388. ret = clk_get_by_index(bus, 0, &clk);
  389. if (ret < 0)
  390. return ret;
  391. ret = clk_enable(&clk);
  392. if (ret) {
  393. dev_err(bus, "failed to enable clock\n");
  394. return ret;
  395. }
  396. priv->clock_rate = clk_get_rate(&clk);
  397. if (priv->clock_rate < 0) {
  398. clk_disable(&clk);
  399. return priv->clock_rate;
  400. }
  401. setbits_le32(&priv->regs->cr, STM32_QSPI_CR_SSHIFT);
  402. return 0;
  403. }
  404. static int stm32_qspi_remove(struct udevice *bus)
  405. {
  406. return 0;
  407. }
  408. static int stm32_qspi_claim_bus(struct udevice *dev)
  409. {
  410. struct stm32_qspi_priv *priv;
  411. struct udevice *bus;
  412. struct spi_flash *flash;
  413. bus = dev->parent;
  414. priv = dev_get_priv(bus);
  415. flash = dev_get_uclass_priv(dev);
  416. _stm32_qspi_set_flash_size(priv, flash->size);
  417. _stm32_qspi_enable(priv);
  418. return 0;
  419. }
  420. static int stm32_qspi_release_bus(struct udevice *dev)
  421. {
  422. struct stm32_qspi_priv *priv;
  423. struct udevice *bus;
  424. bus = dev->parent;
  425. priv = dev_get_priv(bus);
  426. _stm32_qspi_disable(priv);
  427. return 0;
  428. }
  429. static int stm32_qspi_xfer(struct udevice *dev, unsigned int bitlen,
  430. const void *dout, void *din, unsigned long flags)
  431. {
  432. struct stm32_qspi_priv *priv;
  433. struct udevice *bus;
  434. struct spi_flash *flash;
  435. bus = dev->parent;
  436. priv = dev_get_priv(bus);
  437. flash = dev_get_uclass_priv(dev);
  438. return _stm32_qspi_xfer(priv, flash, bitlen, (const u8 *)dout,
  439. (u8 *)din, flags);
  440. }
  441. static int stm32_qspi_set_speed(struct udevice *bus, uint speed)
  442. {
  443. struct stm32_qspi_platdata *plat = bus->platdata;
  444. struct stm32_qspi_priv *priv = dev_get_priv(bus);
  445. u32 qspi_clk = priv->clock_rate;
  446. u32 prescaler = 255;
  447. u32 csht;
  448. if (speed > plat->max_hz)
  449. speed = plat->max_hz;
  450. if (speed > 0) {
  451. prescaler = DIV_ROUND_UP(qspi_clk, speed) - 1;
  452. if (prescaler > 255)
  453. prescaler = 255;
  454. else if (prescaler < 0)
  455. prescaler = 0;
  456. }
  457. csht = DIV_ROUND_UP((5 * qspi_clk) / (prescaler + 1), 100000000);
  458. csht = (csht - 1) & STM32_QSPI_DCR_CSHT_MASK;
  459. _stm32_qspi_wait_for_not_busy(priv);
  460. clrsetbits_le32(&priv->regs->cr,
  461. STM32_QSPI_CR_PRESCALER_MASK <<
  462. STM32_QSPI_CR_PRESCALER_SHIFT,
  463. prescaler << STM32_QSPI_CR_PRESCALER_SHIFT);
  464. clrsetbits_le32(&priv->regs->dcr,
  465. STM32_QSPI_DCR_CSHT_MASK << STM32_QSPI_DCR_CSHT_SHIFT,
  466. csht << STM32_QSPI_DCR_CSHT_SHIFT);
  467. debug("%s: regs=%p, speed=%d\n", __func__, priv->regs,
  468. (qspi_clk / (prescaler + 1)));
  469. return 0;
  470. }
  471. static int stm32_qspi_set_mode(struct udevice *bus, uint mode)
  472. {
  473. struct stm32_qspi_priv *priv = dev_get_priv(bus);
  474. _stm32_qspi_wait_for_not_busy(priv);
  475. if ((mode & SPI_CPHA) && (mode & SPI_CPOL))
  476. setbits_le32(&priv->regs->dcr, STM32_QSPI_DCR_CKMODE);
  477. else if (!(mode & SPI_CPHA) && !(mode & SPI_CPOL))
  478. clrbits_le32(&priv->regs->dcr, STM32_QSPI_DCR_CKMODE);
  479. else
  480. return -ENODEV;
  481. if (mode & SPI_CS_HIGH)
  482. return -ENODEV;
  483. if (mode & SPI_RX_QUAD)
  484. priv->mode |= SPI_RX_QUAD;
  485. else if (mode & SPI_RX_DUAL)
  486. priv->mode |= SPI_RX_DUAL;
  487. else
  488. priv->mode &= ~(SPI_RX_QUAD | SPI_RX_DUAL);
  489. if (mode & SPI_TX_QUAD)
  490. priv->mode |= SPI_TX_QUAD;
  491. else if (mode & SPI_TX_DUAL)
  492. priv->mode |= SPI_TX_DUAL;
  493. else
  494. priv->mode &= ~(SPI_TX_QUAD | SPI_TX_DUAL);
  495. debug("%s: regs=%p, mode=%d rx: ", __func__, priv->regs, mode);
  496. if (mode & SPI_RX_QUAD)
  497. debug("quad, tx: ");
  498. else if (mode & SPI_RX_DUAL)
  499. debug("dual, tx: ");
  500. else
  501. debug("single, tx: ");
  502. if (mode & SPI_TX_QUAD)
  503. debug("quad\n");
  504. else if (mode & SPI_TX_DUAL)
  505. debug("dual\n");
  506. else
  507. debug("single\n");
  508. return 0;
  509. }
  510. static const struct dm_spi_ops stm32_qspi_ops = {
  511. .claim_bus = stm32_qspi_claim_bus,
  512. .release_bus = stm32_qspi_release_bus,
  513. .xfer = stm32_qspi_xfer,
  514. .set_speed = stm32_qspi_set_speed,
  515. .set_mode = stm32_qspi_set_mode,
  516. };
  517. static const struct udevice_id stm32_qspi_ids[] = {
  518. { .compatible = "st,stm32-qspi" },
  519. { }
  520. };
  521. U_BOOT_DRIVER(stm32_qspi) = {
  522. .name = "stm32_qspi",
  523. .id = UCLASS_SPI,
  524. .of_match = stm32_qspi_ids,
  525. .ops = &stm32_qspi_ops,
  526. .ofdata_to_platdata = stm32_qspi_ofdata_to_platdata,
  527. .platdata_auto_alloc_size = sizeof(struct stm32_qspi_platdata),
  528. .priv_auto_alloc_size = sizeof(struct stm32_qspi_priv),
  529. .probe = stm32_qspi_probe,
  530. .remove = stm32_qspi_remove,
  531. };