evm.c 6.1 KB

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  1. /*
  2. * (C) Copyright 2010
  3. * Texas Instruments Incorporated, <www.ti.com>
  4. * Aneesh V <aneesh@ti.com>
  5. * Steve Sakoman <steve@sakoman.com>
  6. *
  7. * SPDX-License-Identifier: GPL-2.0+
  8. */
  9. #include <common.h>
  10. #include <palmas.h>
  11. #include <asm/arch/omap.h>
  12. #include <asm/arch/sys_proto.h>
  13. #include <asm/arch/mmc_host_def.h>
  14. #include <tca642x.h>
  15. #include <usb.h>
  16. #include <linux/usb/gadget.h>
  17. #include <dwc3-uboot.h>
  18. #include <dwc3-omap-uboot.h>
  19. #include <ti-usb-phy-uboot.h>
  20. #include "mux_data.h"
  21. #if defined(CONFIG_USB_EHCI_HCD) || defined(CONFIG_USB_XHCI_OMAP)
  22. #include <sata.h>
  23. #include <usb.h>
  24. #include <asm/gpio.h>
  25. #include <asm/arch/clock.h>
  26. #include <asm/arch/ehci.h>
  27. #include <asm/ehci-omap.h>
  28. #include <asm/arch/sata.h>
  29. #define DIE_ID_REG_BASE (OMAP54XX_L4_CORE_BASE + 0x2000)
  30. #define DIE_ID_REG_OFFSET 0x200
  31. #endif
  32. DECLARE_GLOBAL_DATA_PTR;
  33. const struct omap_sysinfo sysinfo = {
  34. "Board: OMAP5432 uEVM\n"
  35. };
  36. /**
  37. * @brief tca642x_init - uEVM default values for the GPIO expander
  38. * input reg, output reg, polarity reg, configuration reg
  39. */
  40. struct tca642x_bank_info tca642x_init[] = {
  41. { .input_reg = 0x00,
  42. .output_reg = 0x04,
  43. .polarity_reg = 0x00,
  44. .configuration_reg = 0x80 },
  45. { .input_reg = 0x00,
  46. .output_reg = 0x00,
  47. .polarity_reg = 0x00,
  48. .configuration_reg = 0xff },
  49. { .input_reg = 0x00,
  50. .output_reg = 0x00,
  51. .polarity_reg = 0x00,
  52. .configuration_reg = 0x40 },
  53. };
  54. #ifdef CONFIG_USB_DWC3
  55. static struct dwc3_device usb_otg_ss = {
  56. .maximum_speed = USB_SPEED_SUPER,
  57. .base = OMAP5XX_USB_OTG_SS_BASE,
  58. .tx_fifo_resize = false,
  59. .index = 0,
  60. };
  61. static struct dwc3_omap_device usb_otg_ss_glue = {
  62. .base = (void *)OMAP5XX_USB_OTG_SS_GLUE_BASE,
  63. .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
  64. .index = 0,
  65. };
  66. static struct ti_usb_phy_device usb_phy_device = {
  67. .pll_ctrl_base = (void *)OMAP5XX_USB3_PHY_PLL_CTRL,
  68. .usb2_phy_power = (void *)OMAP5XX_USB2_PHY_POWER,
  69. .usb3_phy_power = (void *)OMAP5XX_USB3_PHY_POWER,
  70. .index = 0,
  71. };
  72. int board_usb_init(int index, enum usb_init_type init)
  73. {
  74. if (index) {
  75. printf("Invalid Controller Index\n");
  76. return -EINVAL;
  77. }
  78. if (init == USB_INIT_DEVICE) {
  79. usb_otg_ss.dr_mode = USB_DR_MODE_PERIPHERAL;
  80. usb_otg_ss_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
  81. } else {
  82. usb_otg_ss.dr_mode = USB_DR_MODE_HOST;
  83. usb_otg_ss_glue.vbus_id_status = OMAP_DWC3_ID_GROUND;
  84. }
  85. enable_usb_clocks(index);
  86. ti_usb_phy_uboot_init(&usb_phy_device);
  87. dwc3_omap_uboot_init(&usb_otg_ss_glue);
  88. dwc3_uboot_init(&usb_otg_ss);
  89. return 0;
  90. }
  91. int board_usb_cleanup(int index, enum usb_init_type init)
  92. {
  93. if (index) {
  94. printf("Invalid Controller Index\n");
  95. return -EINVAL;
  96. }
  97. ti_usb_phy_uboot_exit(index);
  98. dwc3_uboot_exit(index);
  99. dwc3_omap_uboot_exit(index);
  100. disable_usb_clocks(index);
  101. return 0;
  102. }
  103. int usb_gadget_handle_interrupts(int index)
  104. {
  105. u32 status;
  106. status = dwc3_omap_uboot_interrupt_status(index);
  107. if (status)
  108. dwc3_uboot_handle_interrupt(index);
  109. return 0;
  110. }
  111. #endif
  112. /**
  113. * @brief board_init
  114. *
  115. * @return 0
  116. */
  117. int board_init(void)
  118. {
  119. gpmc_init();
  120. gd->bd->bi_arch_number = MACH_TYPE_OMAP5_SEVM;
  121. gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */
  122. tca642x_set_inital_state(CONFIG_SYS_I2C_TCA642X_ADDR, tca642x_init);
  123. return 0;
  124. }
  125. int board_eth_init(bd_t *bis)
  126. {
  127. return 0;
  128. }
  129. #if defined(CONFIG_USB_EHCI_HCD) || defined(CONFIG_USB_XHCI_OMAP)
  130. static void enable_host_clocks(void)
  131. {
  132. int auxclk;
  133. int hs_clk_ctrl_val = (OPTFCLKEN_HSIC60M_P3_CLK |
  134. OPTFCLKEN_HSIC480M_P3_CLK |
  135. OPTFCLKEN_HSIC60M_P2_CLK |
  136. OPTFCLKEN_HSIC480M_P2_CLK |
  137. OPTFCLKEN_UTMI_P3_CLK | OPTFCLKEN_UTMI_P2_CLK);
  138. /* Enable port 2 and 3 clocks*/
  139. setbits_le32((*prcm)->cm_l3init_hsusbhost_clkctrl, hs_clk_ctrl_val);
  140. /* Enable port 2 and 3 usb host ports tll clocks*/
  141. setbits_le32((*prcm)->cm_l3init_hsusbtll_clkctrl,
  142. (OPTFCLKEN_USB_CH1_CLK_ENABLE | OPTFCLKEN_USB_CH2_CLK_ENABLE));
  143. #ifdef CONFIG_USB_XHCI_OMAP
  144. /* Enable the USB OTG Super speed clocks */
  145. setbits_le32((*prcm)->cm_l3init_usb_otg_ss_clkctrl,
  146. (OPTFCLKEN_REFCLK960M | OTG_SS_CLKCTRL_MODULEMODE_HW));
  147. #endif
  148. auxclk = readl((*prcm)->scrm_auxclk1);
  149. /* Request auxilary clock */
  150. auxclk |= AUXCLK_ENABLE_MASK;
  151. writel(auxclk, (*prcm)->scrm_auxclk1);
  152. }
  153. #endif
  154. /**
  155. * @brief misc_init_r - Configure EVM board specific configurations
  156. * such as power configurations, ethernet initialization as phase2 of
  157. * boot sequence
  158. *
  159. * @return 0
  160. */
  161. int misc_init_r(void)
  162. {
  163. #ifdef CONFIG_PALMAS_POWER
  164. palmas_init_settings();
  165. #endif
  166. omap_die_id_usbethaddr();
  167. return 0;
  168. }
  169. void set_muxconf_regs(void)
  170. {
  171. do_set_mux((*ctrl)->control_padconf_core_base,
  172. core_padconf_array_essential,
  173. sizeof(core_padconf_array_essential) /
  174. sizeof(struct pad_conf_entry));
  175. do_set_mux((*ctrl)->control_padconf_wkup_base,
  176. wkup_padconf_array_essential,
  177. sizeof(wkup_padconf_array_essential) /
  178. sizeof(struct pad_conf_entry));
  179. }
  180. #if defined(CONFIG_GENERIC_MMC)
  181. int board_mmc_init(bd_t *bis)
  182. {
  183. omap_mmc_init(0, 0, 0, -1, -1);
  184. omap_mmc_init(1, 0, 0, -1, -1);
  185. return 0;
  186. }
  187. #endif
  188. #ifdef CONFIG_USB_EHCI_HCD
  189. static struct omap_usbhs_board_data usbhs_bdata = {
  190. .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
  191. .port_mode[1] = OMAP_EHCI_PORT_MODE_HSIC,
  192. .port_mode[2] = OMAP_EHCI_PORT_MODE_HSIC,
  193. };
  194. int ehci_hcd_init(int index, enum usb_init_type init,
  195. struct ehci_hccr **hccr, struct ehci_hcor **hcor)
  196. {
  197. int ret;
  198. enable_host_clocks();
  199. ret = omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
  200. if (ret < 0) {
  201. puts("Failed to initialize ehci\n");
  202. return ret;
  203. }
  204. return 0;
  205. }
  206. int ehci_hcd_stop(void)
  207. {
  208. return omap_ehci_hcd_stop();
  209. }
  210. void usb_hub_reset_devices(int port)
  211. {
  212. /* The LAN9730 needs to be reset after the port power has been set. */
  213. if (port == 3) {
  214. gpio_direction_output(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO, 0);
  215. udelay(10);
  216. gpio_direction_output(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO, 1);
  217. }
  218. }
  219. #endif
  220. #ifdef CONFIG_USB_XHCI_OMAP
  221. /**
  222. * @brief board_usb_init - Configure EVM board specific configurations
  223. * for the LDO's and clocks for the USB blocks.
  224. *
  225. * @return 0
  226. */
  227. int board_usb_init(int index, enum usb_init_type init)
  228. {
  229. int ret;
  230. #ifdef CONFIG_PALMAS_USB_SS_PWR
  231. ret = palmas_enable_ss_ldo();
  232. #endif
  233. enable_host_clocks();
  234. return 0;
  235. }
  236. #endif