soc.c 2.1 KB

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  1. /*
  2. * Copyright 2014-2015 Freescale Semiconductor
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. */
  6. #include <common.h>
  7. #include <fsl_ifc.h>
  8. #include <asm/arch/soc.h>
  9. #include <asm/io.h>
  10. #include <asm/global_data.h>
  11. DECLARE_GLOBAL_DATA_PTR;
  12. #ifdef CONFIG_LS2085A
  13. static void erratum_a008751(void)
  14. {
  15. #ifdef CONFIG_SYS_FSL_ERRATUM_A008751
  16. u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
  17. writel(0x27672b2a, scfg + SCFG_USB3PRM1CR / 4);
  18. #endif
  19. }
  20. static void erratum_rcw_src(void)
  21. {
  22. #if defined(CONFIG_SPL)
  23. u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
  24. u32 __iomem *dcfg_dcsr = (u32 __iomem *)DCFG_DCSR_BASE;
  25. u32 val;
  26. val = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4);
  27. val &= ~DCFG_PORSR1_RCW_SRC;
  28. val |= DCFG_PORSR1_RCW_SRC_NOR;
  29. out_le32(dcfg_dcsr + DCFG_DCSR_PORCR1 / 4, val);
  30. #endif
  31. }
  32. #define I2C_DEBUG_REG 0x6
  33. #define I2C_GLITCH_EN 0x8
  34. /*
  35. * This erratum requires setting glitch_en bit to enable
  36. * digital glitch filter to improve clock stability.
  37. */
  38. static void erratum_a009203(void)
  39. {
  40. u8 __iomem *ptr;
  41. #ifdef CONFIG_SYS_I2C
  42. #ifdef I2C1_BASE_ADDR
  43. ptr = (u8 __iomem *)(I2C1_BASE_ADDR + I2C_DEBUG_REG);
  44. writeb(I2C_GLITCH_EN, ptr);
  45. #endif
  46. #ifdef I2C2_BASE_ADDR
  47. ptr = (u8 __iomem *)(I2C2_BASE_ADDR + I2C_DEBUG_REG);
  48. writeb(I2C_GLITCH_EN, ptr);
  49. #endif
  50. #ifdef I2C3_BASE_ADDR
  51. ptr = (u8 __iomem *)(I2C3_BASE_ADDR + I2C_DEBUG_REG);
  52. writeb(I2C_GLITCH_EN, ptr);
  53. #endif
  54. #ifdef I2C4_BASE_ADDR
  55. ptr = (u8 __iomem *)(I2C4_BASE_ADDR + I2C_DEBUG_REG);
  56. writeb(I2C_GLITCH_EN, ptr);
  57. #endif
  58. #endif
  59. }
  60. void fsl_lsch3_early_init_f(void)
  61. {
  62. erratum_a008751();
  63. erratum_rcw_src();
  64. init_early_memctl_regs(); /* tighten IFC timing */
  65. erratum_a009203();
  66. }
  67. #elif defined(CONFIG_LS1043A)
  68. void fsl_lsch2_early_init_f(void)
  69. {
  70. struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
  71. #ifdef CONFIG_FSL_IFC
  72. init_early_memctl_regs(); /* tighten IFC timing */
  73. #endif
  74. /*
  75. * Enable snoop requests and DVM message requests for
  76. * Slave insterface S4 (A53 core cluster)
  77. */
  78. out_le32(&cci->slave[4].snoop_ctrl,
  79. CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
  80. }
  81. #endif
  82. #ifdef CONFIG_BOARD_LATE_INIT
  83. int board_late_init(void)
  84. {
  85. return 0;
  86. }
  87. #endif