fsl_lsch2_serdes.c 2.5 KB

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  1. /*
  2. * Copyright 2015 Freescale Semiconductor, Inc.
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. */
  6. #include <common.h>
  7. #include <asm/io.h>
  8. #include <asm/errno.h>
  9. #include <asm/arch/fsl_serdes.h>
  10. #include <asm/arch/soc.h>
  11. #ifdef CONFIG_SYS_FSL_SRDS_1
  12. static u8 serdes1_prtcl_map[SERDES_PRCTL_COUNT];
  13. #endif
  14. int is_serdes_configured(enum srds_prtcl device)
  15. {
  16. int ret = 0;
  17. #ifdef CONFIG_SYS_FSL_SRDS_1
  18. ret |= serdes1_prtcl_map[device];
  19. #endif
  20. return !!ret;
  21. }
  22. int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
  23. {
  24. struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  25. u32 cfg = gur_in32(&gur->rcwsr[4]);
  26. int i;
  27. switch (sd) {
  28. #ifdef CONFIG_SYS_FSL_SRDS_1
  29. case FSL_SRDS_1:
  30. cfg &= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
  31. cfg >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
  32. break;
  33. #endif
  34. default:
  35. printf("invalid SerDes%d\n", sd);
  36. break;
  37. }
  38. /* Is serdes enabled at all? */
  39. if (unlikely(cfg == 0))
  40. return -ENODEV;
  41. for (i = 0; i < SRDS_MAX_LANES; i++) {
  42. if (serdes_get_prtcl(sd, cfg, i) == device)
  43. return i;
  44. }
  45. return -ENODEV;
  46. }
  47. int get_serdes_protocol(void)
  48. {
  49. struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  50. u32 cfg = gur_in32(&gur->rcwsr[4]) &
  51. FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
  52. cfg >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
  53. return cfg;
  54. }
  55. const char *serdes_clock_to_string(u32 clock)
  56. {
  57. switch (clock) {
  58. case SRDS_PLLCR0_RFCK_SEL_100:
  59. return "100";
  60. case SRDS_PLLCR0_RFCK_SEL_125:
  61. return "125";
  62. case SRDS_PLLCR0_RFCK_SEL_156_25:
  63. return "156.25";
  64. default:
  65. return "100";
  66. }
  67. }
  68. void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift,
  69. u8 serdes_prtcl_map[SERDES_PRCTL_COUNT])
  70. {
  71. struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  72. u32 cfg;
  73. int lane;
  74. memset(serdes_prtcl_map, 0, sizeof(serdes_prtcl_map));
  75. cfg = gur_in32(&gur->rcwsr[4]) & sd_prctl_mask;
  76. cfg >>= sd_prctl_shift;
  77. printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg);
  78. if (!is_serdes_prtcl_valid(sd, cfg))
  79. printf("SERDES%d[PRTCL] = 0x%x is not valid\n", sd + 1, cfg);
  80. for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
  81. enum srds_prtcl lane_prtcl = serdes_get_prtcl(sd, cfg, lane);
  82. if (unlikely(lane_prtcl >= SERDES_PRCTL_COUNT))
  83. debug("Unknown SerDes lane protocol %d\n", lane_prtcl);
  84. else
  85. serdes_prtcl_map[lane_prtcl] = 1;
  86. }
  87. }
  88. void fsl_serdes_init(void)
  89. {
  90. #ifdef CONFIG_SYS_FSL_SRDS_1
  91. serdes_init(FSL_SRDS_1,
  92. CONFIG_SYS_FSL_SERDES_ADDR,
  93. FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK,
  94. FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT,
  95. serdes1_prtcl_map);
  96. #endif
  97. }