chromebox_panther.dts 1.4 KB

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  1. /dts-v1/;
  2. /include/ "skeleton.dtsi"
  3. /include/ "serial.dtsi"
  4. /include/ "rtc.dtsi"
  5. /include/ "tsc_timer.dtsi"
  6. / {
  7. model = "Google Panther";
  8. compatible = "google,panther", "intel,haswell";
  9. aliases {
  10. spi0 = &spi;
  11. };
  12. config {
  13. silent-console = <0>;
  14. no-keyboard;
  15. };
  16. gpioa {
  17. compatible = "intel,ich6-gpio";
  18. u-boot,dm-pre-reloc;
  19. reg = <0 0x10>;
  20. bank-name = "A";
  21. };
  22. gpiob {
  23. compatible = "intel,ich6-gpio";
  24. u-boot,dm-pre-reloc;
  25. reg = <0x30 0x10>;
  26. bank-name = "B";
  27. };
  28. gpioc {
  29. compatible = "intel,ich6-gpio";
  30. u-boot,dm-pre-reloc;
  31. reg = <0x40 0x10>;
  32. bank-name = "C";
  33. };
  34. chosen {
  35. stdout-path = "/serial";
  36. };
  37. pci {
  38. compatible = "pci-x86";
  39. #address-cells = <3>;
  40. #size-cells = <2>;
  41. u-boot,dm-pre-reloc;
  42. ranges = <0x02000000 0x0 0xe0000000 0xe0000000 0 0x10000000
  43. 0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000
  44. 0x01000000 0x0 0x1000 0x1000 0 0xf000>;
  45. pch@1f,0 {
  46. reg = <0x0000f800 0 0 0 0>;
  47. compatible = "intel,pch9";
  48. spi: spi {
  49. #address-cells = <1>;
  50. #size-cells = <0>;
  51. compatible = "intel,ich-spi";
  52. spi-flash@0 {
  53. #size-cells = <1>;
  54. #address-cells = <1>;
  55. reg = <0>;
  56. compatible = "winbond,w25q64",
  57. "spi-flash";
  58. memory-map = <0xff800000 0x00800000>;
  59. rw-mrc-cache {
  60. label = "rw-mrc-cache";
  61. reg = <0x003e0000 0x00010000>;
  62. };
  63. };
  64. };
  65. };
  66. };
  67. tpm {
  68. reg = <0xfed40000 0x5000>;
  69. compatible = "infineon,slb9635lpc";
  70. };
  71. };