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altera
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nios2-generic
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custom_fpga.h

custom_fpga.h 2.9 KB
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  1. /*
    2. 

  2.  * This header is generated by sopc2dts
    3. 

  3.  * Sopc2dts is written by Walter Goossens <waltergoossens@home.nl>
    4. 

  4.  * in cooperation with the nios2 community <Nios2-dev@sopc.et.ntust.edu.tw>
    5. 

  5.  *
    6. 

  6.  * SPDX-License-Identifier:	GPL-2.0+
    7. 

  7.  */
    8. 

  8. #ifndef _CUSTOM_FPGA_H_
    9. 

  9. #define _CUSTOM_FPGA_H_
    10. 

  10. 

  11. /* generated from qsys_ghrd_3c120.sopcinfo */
    12. 

  12. 

  13. /* Dumping slaves of cpu.data_master */
    14. 

  14. 

  15. /* cpu.jtag_debug_module is a altera_nios2_qsys */
    16. 

  16. #define CONFIG_SYS_CLK_FREQ	125000000
    17. 

  17. #define CONFIG_SYS_DCACHE_SIZE	32768
    18. 

  18. #define CONFIG_SYS_DCACHELINE_SIZE	32
    19. 

  19. #define CONFIG_SYS_ICACHELINE_SIZE	32
    20. 

  20. #define CONFIG_SYS_EXCEPTION_ADDR	0xd0000020
    21. 

  21. #define CONFIG_SYS_ICACHE_SIZE	32768
    22. 

  22. #define CONFIG_SYS_RESET_ADDR	0xc2800000
    23. 

  23. #define IO_REGION_BASE	0xE0000000
    24. 

  24. 

  25. /* pb_cpu_to_ddr2_bot.s0 is a altera_avalon_mm_bridge */
    26. 

  26. /* Dumping slaves of pb_cpu_to_ddr2_bot.m0 */
    27. 

  27. 

  28. /* ddr2_bot.s1 is a altmemddr2 */
    29. 

  29. #define CONFIG_SYS_SDRAM_BASE	0xD0000000
    30. 

  30. #define CONFIG_SYS_SDRAM_SIZE	0x08000000
    31. 

  31. 

  32. /* pb_cpu_to_io.s0 is a altera_avalon_mm_bridge */
    33. 

  33. /* Dumping slaves of pb_cpu_to_io.m0 */
    34. 

  34. 

  35. /* timer_1ms.s1 is a altera_avalon_timer */
    36. 

  36. #define CONFIG_SYS_TIMER_IRQ	11
    37. 

  37. #define CONFIG_SYS_TIMER_FREQ	125000000
    38. 

  38. #define CONFIG_SYS_TIMER_BASE	0xE8400000
    39. 

  39. 

  40. /* sysid.control_slave is a altera_avalon_sysid_qsys */
    41. 

  41. #define CONFIG_SYS_SYSID_BASE	0xE8004D40
    42. 

  42. 

  43. /* jtag_uart.avalon_jtag_slave is a altera_avalon_jtag_uart */
    44. 

  44. #define CONFIG_SYS_JTAG_UART_BASE	0xE8004D50
    45. 

  45. 

  46. /* tse_mac.control_port is a triple_speed_ethernet */
    47. 

  47. #define CONFIG_SYS_ALTERA_TSE_RX_FIFO	2048
    48. 

  48. #define CONFIG_SYS_ALTERA_TSE_SGDMA_TX_BASE	0xE8004800
    49. 

  49. #define CONFIG_SYS_ALTERA_TSE_SGDMA_RX_BASE	0xE8004400
    50. 

  50. #define CONFIG_SYS_ALTERA_TSE_TX_FIFO	2048
    51. 

  51. #define CONFIG_SYS_ALTERA_TSE_DESC_SIZE	0x00002000
    52. 

  52. #define CONFIG_SYS_ALTERA_TSE_MAC_BASE	0xE8004000
    53. 

  53. #define CONFIG_SYS_ALTERA_TSE_DESC_BASE	0xE8002000
    54. 

  54. #define CONFIG_ALTERA_TSE
    55. 

  55. #define CONFIG_MII
    56. 

  56. #define CONFIG_CMD_MII
    57. 

  57. #define CONFIG_SYS_ALTERA_TSE_PHY_ADDR 18
    58. 

  58. #define CONFIG_SYS_ALTERA_TSE_FLAGS 1
    59. 

  59. 

  60. /* uart.s1 is a altera_avalon_uart */
    61. 

  61. #define CONFIG_SYS_UART_BAUD	115200
    62. 

  62. #define CONFIG_SYS_UART_BASE	0xE8004C80
    63. 

  63. #define CONFIG_SYS_UART_FREQ	62500000
    64. 

  64. 

  65. /* user_led_pio_8out.s1 is a altera_avalon_pio */
    66. 

  66. #define USER_LED_PIO_8OUT_BASE	0xE8004CC0
    67. 

  67. 

  68. /* user_dipsw_pio_8in.s1 is a altera_avalon_pio */
    69. 

  69. #define USER_DIPSW_PIO_8IN_BASE	0xE8004CE0
    70. 

  70. #define USER_DIPSW_PIO_8IN_IRQ	8
    71. 

  71. 

  72. /* user_pb_pio_4in.s1 is a altera_avalon_pio */
    73. 

  73. #define USER_PB_PIO_4IN_BASE	0xE8004D00
    74. 

  74. #define USER_PB_PIO_4IN_IRQ	9
    75. 

  75. 

  76. /* cfi_flash_64m.uas is a altera_generic_tristate_controller */
    77. 

  77. #define CFI_FLASH_64M_BASE	0xE0000000
    78. 

  78. 

  79. /* ext_flash.s1 is a altera_avalon_cfi_flash */
    80. 

  80. #define CONFIG_SYS_FLASH_BASE CFI_FLASH_64M_BASE
    81. 

  81. #define CONFIG_FLASH_CFI_DRIVER
    82. 

  82. #define CONFIG_SYS_CFI_FLASH_STATUS_POLL /* fix amd flash issue */
    83. 

  83. #define CONFIG_SYS_FLASH_CFI
    84. 

  84. #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
    85. 

  85. #define CONFIG_SYS_FLASH_PROTECTION
    86. 

  86. #define CONFIG_SYS_MAX_FLASH_BANKS 1
    87. 

  87. #define CONFIG_SYS_MAX_FLASH_SECT 512
    88. 

  88. 

  89. #endif /* _CUSTOM_FPGA_H_ */
    90.