serial_pl01x.h 5.3 KB

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  1. /*
  2. * (C) Copyright 2003, 2004
  3. * ARM Ltd.
  4. * Philippe Robin, <philippe.robin@arm.com>
  5. *
  6. * See file CREDITS for list of people who contributed to this
  7. * project.
  8. *
  9. * This program is free software; you can redistribute it and/or
  10. * modify it under the terms of the GNU General Public License as
  11. * published by the Free Software Foundation; either version 2 of
  12. * the License, or (at your option) any later version.
  13. *
  14. * This program is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * You should have received a copy of the GNU General Public License
  20. * along with this program; if not, write to the Free Software
  21. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22. * MA 02111-1307 USA
  23. */
  24. /*
  25. * ARM PrimeCell UART's (PL010 & PL011)
  26. * ------------------------------------
  27. *
  28. * Definitions common to both PL010 & PL011
  29. *
  30. */
  31. #ifndef __ASSEMBLY__
  32. /*
  33. * We can use a combined structure for PL010 and PL011, because they overlap
  34. * only in common registers.
  35. */
  36. struct pl01x_regs {
  37. u32 dr; /* 0x00 Data register */
  38. u32 ecr; /* 0x04 Error clear register (Write) */
  39. u32 pl010_lcrh; /* 0x08 Line control register, high byte */
  40. u32 pl010_lcrm; /* 0x0C Line control register, middle byte */
  41. u32 pl010_lcrl; /* 0x10 Line control register, low byte */
  42. u32 pl010_cr; /* 0x14 Control register */
  43. u32 fr; /* 0x18 Flag register (Read only) */
  44. #ifdef CONFIG_PL011_SERIAL_RLCR
  45. u32 pl011_rlcr; /* 0x1c Receive line control register */
  46. #else
  47. u32 reserved;
  48. #endif
  49. u32 ilpr; /* 0x20 IrDA low-power counter register */
  50. u32 pl011_ibrd; /* 0x24 Integer baud rate register */
  51. u32 pl011_fbrd; /* 0x28 Fractional baud rate register */
  52. u32 pl011_lcrh; /* 0x2C Line control register */
  53. u32 pl011_cr; /* 0x30 Control register */
  54. };
  55. #endif
  56. #define UART_PL01x_RSR_OE 0x08
  57. #define UART_PL01x_RSR_BE 0x04
  58. #define UART_PL01x_RSR_PE 0x02
  59. #define UART_PL01x_RSR_FE 0x01
  60. #define UART_PL01x_FR_TXFE 0x80
  61. #define UART_PL01x_FR_RXFF 0x40
  62. #define UART_PL01x_FR_TXFF 0x20
  63. #define UART_PL01x_FR_RXFE 0x10
  64. #define UART_PL01x_FR_BUSY 0x08
  65. #define UART_PL01x_FR_TMSK (UART_PL01x_FR_TXFF + UART_PL01x_FR_BUSY)
  66. /*
  67. * PL010 definitions
  68. *
  69. */
  70. #define UART_PL010_CR_LPE (1 << 7)
  71. #define UART_PL010_CR_RTIE (1 << 6)
  72. #define UART_PL010_CR_TIE (1 << 5)
  73. #define UART_PL010_CR_RIE (1 << 4)
  74. #define UART_PL010_CR_MSIE (1 << 3)
  75. #define UART_PL010_CR_IIRLP (1 << 2)
  76. #define UART_PL010_CR_SIREN (1 << 1)
  77. #define UART_PL010_CR_UARTEN (1 << 0)
  78. #define UART_PL010_LCRH_WLEN_8 (3 << 5)
  79. #define UART_PL010_LCRH_WLEN_7 (2 << 5)
  80. #define UART_PL010_LCRH_WLEN_6 (1 << 5)
  81. #define UART_PL010_LCRH_WLEN_5 (0 << 5)
  82. #define UART_PL010_LCRH_FEN (1 << 4)
  83. #define UART_PL010_LCRH_STP2 (1 << 3)
  84. #define UART_PL010_LCRH_EPS (1 << 2)
  85. #define UART_PL010_LCRH_PEN (1 << 1)
  86. #define UART_PL010_LCRH_BRK (1 << 0)
  87. #define UART_PL010_BAUD_460800 1
  88. #define UART_PL010_BAUD_230400 3
  89. #define UART_PL010_BAUD_115200 7
  90. #define UART_PL010_BAUD_57600 15
  91. #define UART_PL010_BAUD_38400 23
  92. #define UART_PL010_BAUD_19200 47
  93. #define UART_PL010_BAUD_14400 63
  94. #define UART_PL010_BAUD_9600 95
  95. #define UART_PL010_BAUD_4800 191
  96. #define UART_PL010_BAUD_2400 383
  97. #define UART_PL010_BAUD_1200 767
  98. /*
  99. * PL011 definitions
  100. *
  101. */
  102. #define UART_PL011_LCRH_SPS (1 << 7)
  103. #define UART_PL011_LCRH_WLEN_8 (3 << 5)
  104. #define UART_PL011_LCRH_WLEN_7 (2 << 5)
  105. #define UART_PL011_LCRH_WLEN_6 (1 << 5)
  106. #define UART_PL011_LCRH_WLEN_5 (0 << 5)
  107. #define UART_PL011_LCRH_FEN (1 << 4)
  108. #define UART_PL011_LCRH_STP2 (1 << 3)
  109. #define UART_PL011_LCRH_EPS (1 << 2)
  110. #define UART_PL011_LCRH_PEN (1 << 1)
  111. #define UART_PL011_LCRH_BRK (1 << 0)
  112. #define UART_PL011_CR_CTSEN (1 << 15)
  113. #define UART_PL011_CR_RTSEN (1 << 14)
  114. #define UART_PL011_CR_OUT2 (1 << 13)
  115. #define UART_PL011_CR_OUT1 (1 << 12)
  116. #define UART_PL011_CR_RTS (1 << 11)
  117. #define UART_PL011_CR_DTR (1 << 10)
  118. #define UART_PL011_CR_RXE (1 << 9)
  119. #define UART_PL011_CR_TXE (1 << 8)
  120. #define UART_PL011_CR_LPE (1 << 7)
  121. #define UART_PL011_CR_IIRLP (1 << 2)
  122. #define UART_PL011_CR_SIREN (1 << 1)
  123. #define UART_PL011_CR_UARTEN (1 << 0)
  124. #define UART_PL011_IMSC_OEIM (1 << 10)
  125. #define UART_PL011_IMSC_BEIM (1 << 9)
  126. #define UART_PL011_IMSC_PEIM (1 << 8)
  127. #define UART_PL011_IMSC_FEIM (1 << 7)
  128. #define UART_PL011_IMSC_RTIM (1 << 6)
  129. #define UART_PL011_IMSC_TXIM (1 << 5)
  130. #define UART_PL011_IMSC_RXIM (1 << 4)
  131. #define UART_PL011_IMSC_DSRMIM (1 << 3)
  132. #define UART_PL011_IMSC_DCDMIM (1 << 2)
  133. #define UART_PL011_IMSC_CTSMIM (1 << 1)
  134. #define UART_PL011_IMSC_RIMIM (1 << 0)