marvell.c 21 KB

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  1. /*
  2. * Marvell PHY drivers
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. *
  6. * Copyright 2010-2011 Freescale Semiconductor, Inc.
  7. * author Andy Fleming
  8. */
  9. #include <config.h>
  10. #include <common.h>
  11. #include <errno.h>
  12. #include <phy.h>
  13. #define PHY_AUTONEGOTIATE_TIMEOUT 5000
  14. #define MII_MARVELL_PHY_PAGE 22
  15. /* 88E1011 PHY Status Register */
  16. #define MIIM_88E1xxx_PHY_STATUS 0x11
  17. #define MIIM_88E1xxx_PHYSTAT_SPEED 0xc000
  18. #define MIIM_88E1xxx_PHYSTAT_GBIT 0x8000
  19. #define MIIM_88E1xxx_PHYSTAT_100 0x4000
  20. #define MIIM_88E1xxx_PHYSTAT_DUPLEX 0x2000
  21. #define MIIM_88E1xxx_PHYSTAT_SPDDONE 0x0800
  22. #define MIIM_88E1xxx_PHYSTAT_LINK 0x0400
  23. #define MIIM_88E1xxx_PHY_SCR 0x10
  24. #define MIIM_88E1xxx_PHY_MDI_X_AUTO 0x0060
  25. /* 88E1111 PHY LED Control Register */
  26. #define MIIM_88E1111_PHY_LED_CONTROL 24
  27. #define MIIM_88E1111_PHY_LED_DIRECT 0x4100
  28. #define MIIM_88E1111_PHY_LED_COMBINE 0x411C
  29. /* 88E1111 Extended PHY Specific Control Register */
  30. #define MIIM_88E1111_PHY_EXT_CR 0x14
  31. #define MIIM_88E1111_RX_DELAY 0x80
  32. #define MIIM_88E1111_TX_DELAY 0x2
  33. /* 88E1111 Extended PHY Specific Status Register */
  34. #define MIIM_88E1111_PHY_EXT_SR 0x1b
  35. #define MIIM_88E1111_HWCFG_MODE_MASK 0xf
  36. #define MIIM_88E1111_HWCFG_MODE_COPPER_RGMII 0xb
  37. #define MIIM_88E1111_HWCFG_MODE_FIBER_RGMII 0x3
  38. #define MIIM_88E1111_HWCFG_MODE_SGMII_NO_CLK 0x4
  39. #define MIIM_88E1111_HWCFG_MODE_COPPER_RTBI 0x9
  40. #define MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO 0x8000
  41. #define MIIM_88E1111_HWCFG_FIBER_COPPER_RES 0x2000
  42. #define MIIM_88E1111_COPPER 0
  43. #define MIIM_88E1111_FIBER 1
  44. /* 88E1118 PHY defines */
  45. #define MIIM_88E1118_PHY_PAGE 22
  46. #define MIIM_88E1118_PHY_LED_PAGE 3
  47. /* 88E1121 PHY LED Control Register */
  48. #define MIIM_88E1121_PHY_LED_CTRL 16
  49. #define MIIM_88E1121_PHY_LED_PAGE 3
  50. #define MIIM_88E1121_PHY_LED_DEF 0x0030
  51. /* 88E1121 PHY IRQ Enable/Status Register */
  52. #define MIIM_88E1121_PHY_IRQ_EN 18
  53. #define MIIM_88E1121_PHY_IRQ_STATUS 19
  54. #define MIIM_88E1121_PHY_PAGE 22
  55. /* 88E1145 Extended PHY Specific Control Register */
  56. #define MIIM_88E1145_PHY_EXT_CR 20
  57. #define MIIM_M88E1145_RGMII_RX_DELAY 0x0080
  58. #define MIIM_M88E1145_RGMII_TX_DELAY 0x0002
  59. #define MIIM_88E1145_PHY_LED_CONTROL 24
  60. #define MIIM_88E1145_PHY_LED_DIRECT 0x4100
  61. #define MIIM_88E1145_PHY_PAGE 29
  62. #define MIIM_88E1145_PHY_CAL_OV 30
  63. #define MIIM_88E1149_PHY_PAGE 29
  64. /* 88E1310 PHY defines */
  65. #define MIIM_88E1310_PHY_LED_CTRL 16
  66. #define MIIM_88E1310_PHY_IRQ_EN 18
  67. #define MIIM_88E1310_PHY_RGMII_CTRL 21
  68. #define MIIM_88E1310_PHY_PAGE 22
  69. /* 88E151x PHY defines */
  70. /* Page 2 registers */
  71. #define MIIM_88E151x_PHY_MSCR 21
  72. #define MIIM_88E151x_RGMII_RX_DELAY BIT(5)
  73. #define MIIM_88E151x_RGMII_TX_DELAY BIT(4)
  74. #define MIIM_88E151x_RGMII_RXTX_DELAY (BIT(5) | BIT(4))
  75. /* Page 3 registers */
  76. #define MIIM_88E151x_LED_FUNC_CTRL 16
  77. #define MIIM_88E151x_LED_FLD_SZ 4
  78. #define MIIM_88E151x_LED0_OFFS (0 * MIIM_88E151x_LED_FLD_SZ)
  79. #define MIIM_88E151x_LED1_OFFS (1 * MIIM_88E151x_LED_FLD_SZ)
  80. #define MIIM_88E151x_LED0_ACT 3
  81. #define MIIM_88E151x_LED1_100_1000_LINK 6
  82. #define MIIM_88E151x_LED_TIMER_CTRL 18
  83. #define MIIM_88E151x_INT_EN_OFFS 7
  84. /* Page 18 registers */
  85. #define MIIM_88E151x_GENERAL_CTRL 20
  86. #define MIIM_88E151x_MODE_SGMII 1
  87. #define MIIM_88E151x_RESET_OFFS 15
  88. static int m88e1xxx_phy_extread(struct phy_device *phydev, int addr,
  89. int devaddr, int regnum)
  90. {
  91. int oldpage = phy_read(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE);
  92. int val;
  93. phy_write(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE, devaddr);
  94. val = phy_read(phydev, MDIO_DEVAD_NONE, regnum);
  95. phy_write(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE, oldpage);
  96. return val;
  97. }
  98. static int m88e1xxx_phy_extwrite(struct phy_device *phydev, int addr,
  99. int devaddr, int regnum, u16 val)
  100. {
  101. int oldpage = phy_read(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE);
  102. phy_write(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE, devaddr);
  103. phy_write(phydev, MDIO_DEVAD_NONE, regnum, val);
  104. phy_write(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE, oldpage);
  105. return 0;
  106. }
  107. /* Marvell 88E1011S */
  108. static int m88e1011s_config(struct phy_device *phydev)
  109. {
  110. /* Reset and configure the PHY */
  111. phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET);
  112. phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
  113. phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x200c);
  114. phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
  115. phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0);
  116. phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
  117. phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET);
  118. genphy_config_aneg(phydev);
  119. return 0;
  120. }
  121. /* Parse the 88E1011's status register for speed and duplex
  122. * information
  123. */
  124. static int m88e1xxx_parse_status(struct phy_device *phydev)
  125. {
  126. unsigned int speed;
  127. unsigned int mii_reg;
  128. mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1xxx_PHY_STATUS);
  129. if ((mii_reg & MIIM_88E1xxx_PHYSTAT_LINK) &&
  130. !(mii_reg & MIIM_88E1xxx_PHYSTAT_SPDDONE)) {
  131. int i = 0;
  132. puts("Waiting for PHY realtime link");
  133. while (!(mii_reg & MIIM_88E1xxx_PHYSTAT_SPDDONE)) {
  134. /* Timeout reached ? */
  135. if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
  136. puts(" TIMEOUT !\n");
  137. phydev->link = 0;
  138. return -ETIMEDOUT;
  139. }
  140. if ((i++ % 1000) == 0)
  141. putc('.');
  142. udelay(1000);
  143. mii_reg = phy_read(phydev, MDIO_DEVAD_NONE,
  144. MIIM_88E1xxx_PHY_STATUS);
  145. }
  146. puts(" done\n");
  147. mdelay(500); /* another 500 ms (results in faster booting) */
  148. } else {
  149. if (mii_reg & MIIM_88E1xxx_PHYSTAT_LINK)
  150. phydev->link = 1;
  151. else
  152. phydev->link = 0;
  153. }
  154. if (mii_reg & MIIM_88E1xxx_PHYSTAT_DUPLEX)
  155. phydev->duplex = DUPLEX_FULL;
  156. else
  157. phydev->duplex = DUPLEX_HALF;
  158. speed = mii_reg & MIIM_88E1xxx_PHYSTAT_SPEED;
  159. switch (speed) {
  160. case MIIM_88E1xxx_PHYSTAT_GBIT:
  161. phydev->speed = SPEED_1000;
  162. break;
  163. case MIIM_88E1xxx_PHYSTAT_100:
  164. phydev->speed = SPEED_100;
  165. break;
  166. default:
  167. phydev->speed = SPEED_10;
  168. break;
  169. }
  170. return 0;
  171. }
  172. static int m88e1011s_startup(struct phy_device *phydev)
  173. {
  174. int ret;
  175. ret = genphy_update_link(phydev);
  176. if (ret)
  177. return ret;
  178. return m88e1xxx_parse_status(phydev);
  179. }
  180. /* Marvell 88E1111S */
  181. static int m88e1111s_config(struct phy_device *phydev)
  182. {
  183. int reg;
  184. if (phy_interface_is_rgmii(phydev)) {
  185. reg = phy_read(phydev,
  186. MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_CR);
  187. if ((phydev->interface == PHY_INTERFACE_MODE_RGMII) ||
  188. (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)) {
  189. reg |= (MIIM_88E1111_RX_DELAY | MIIM_88E1111_TX_DELAY);
  190. } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
  191. reg &= ~MIIM_88E1111_TX_DELAY;
  192. reg |= MIIM_88E1111_RX_DELAY;
  193. } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
  194. reg &= ~MIIM_88E1111_RX_DELAY;
  195. reg |= MIIM_88E1111_TX_DELAY;
  196. }
  197. phy_write(phydev,
  198. MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_CR, reg);
  199. reg = phy_read(phydev,
  200. MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_SR);
  201. reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK);
  202. if (reg & MIIM_88E1111_HWCFG_FIBER_COPPER_RES)
  203. reg |= MIIM_88E1111_HWCFG_MODE_FIBER_RGMII;
  204. else
  205. reg |= MIIM_88E1111_HWCFG_MODE_COPPER_RGMII;
  206. phy_write(phydev,
  207. MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_SR, reg);
  208. }
  209. if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
  210. reg = phy_read(phydev,
  211. MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_SR);
  212. reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK);
  213. reg |= MIIM_88E1111_HWCFG_MODE_SGMII_NO_CLK;
  214. reg |= MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO;
  215. phy_write(phydev, MDIO_DEVAD_NONE,
  216. MIIM_88E1111_PHY_EXT_SR, reg);
  217. }
  218. if (phydev->interface == PHY_INTERFACE_MODE_RTBI) {
  219. reg = phy_read(phydev,
  220. MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_CR);
  221. reg |= (MIIM_88E1111_RX_DELAY | MIIM_88E1111_TX_DELAY);
  222. phy_write(phydev,
  223. MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_CR, reg);
  224. reg = phy_read(phydev, MDIO_DEVAD_NONE,
  225. MIIM_88E1111_PHY_EXT_SR);
  226. reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK |
  227. MIIM_88E1111_HWCFG_FIBER_COPPER_RES);
  228. reg |= 0x7 | MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO;
  229. phy_write(phydev, MDIO_DEVAD_NONE,
  230. MIIM_88E1111_PHY_EXT_SR, reg);
  231. /* soft reset */
  232. phy_reset(phydev);
  233. reg = phy_read(phydev, MDIO_DEVAD_NONE,
  234. MIIM_88E1111_PHY_EXT_SR);
  235. reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK |
  236. MIIM_88E1111_HWCFG_FIBER_COPPER_RES);
  237. reg |= MIIM_88E1111_HWCFG_MODE_COPPER_RTBI |
  238. MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO;
  239. phy_write(phydev, MDIO_DEVAD_NONE,
  240. MIIM_88E1111_PHY_EXT_SR, reg);
  241. }
  242. /* soft reset */
  243. phy_reset(phydev);
  244. genphy_config_aneg(phydev);
  245. genphy_restart_aneg(phydev);
  246. return 0;
  247. }
  248. /**
  249. * m88e1518_phy_writebits - write bits to a register
  250. */
  251. void m88e1518_phy_writebits(struct phy_device *phydev,
  252. u8 reg_num, u16 offset, u16 len, u16 data)
  253. {
  254. u16 reg, mask;
  255. if ((len + offset) >= 16)
  256. mask = 0 - (1 << offset);
  257. else
  258. mask = (1 << (len + offset)) - (1 << offset);
  259. reg = phy_read(phydev, MDIO_DEVAD_NONE, reg_num);
  260. reg &= ~mask;
  261. reg |= data << offset;
  262. phy_write(phydev, MDIO_DEVAD_NONE, reg_num, reg);
  263. }
  264. static int m88e1518_config(struct phy_device *phydev)
  265. {
  266. u16 reg;
  267. /*
  268. * As per Marvell Release Notes - Alaska 88E1510/88E1518/88E1512
  269. * /88E1514 Rev A0, Errata Section 3.1
  270. */
  271. /* EEE initialization */
  272. phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x00ff);
  273. phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x214B);
  274. phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x2144);
  275. phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x0C28);
  276. phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x2146);
  277. phy_write(phydev, MDIO_DEVAD_NONE, 17, 0xB233);
  278. phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x214D);
  279. phy_write(phydev, MDIO_DEVAD_NONE, 17, 0xCC0C);
  280. phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x2159);
  281. phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0000);
  282. /* SGMII-to-Copper mode initialization */
  283. if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
  284. /* Select page 18 */
  285. phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 18);
  286. /* In reg 20, write MODE[2:0] = 0x1 (SGMII to Copper) */
  287. m88e1518_phy_writebits(phydev, MIIM_88E151x_GENERAL_CTRL,
  288. 0, 3, MIIM_88E151x_MODE_SGMII);
  289. /* PHY reset is necessary after changing MODE[2:0] */
  290. m88e1518_phy_writebits(phydev, MIIM_88E151x_GENERAL_CTRL,
  291. MIIM_88E151x_RESET_OFFS, 1, 1);
  292. /* Reset page selection */
  293. phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0);
  294. udelay(100);
  295. }
  296. if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
  297. reg = phy_read(phydev, MDIO_DEVAD_NONE,
  298. MIIM_88E1111_PHY_EXT_SR);
  299. reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK);
  300. reg |= MIIM_88E1111_HWCFG_MODE_SGMII_NO_CLK;
  301. reg |= MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO;
  302. phy_write(phydev, MDIO_DEVAD_NONE,
  303. MIIM_88E1111_PHY_EXT_SR, reg);
  304. }
  305. if (phy_interface_is_rgmii(phydev)) {
  306. phy_write(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE, 2);
  307. reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E151x_PHY_MSCR);
  308. reg &= ~MIIM_88E151x_RGMII_RXTX_DELAY;
  309. if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
  310. reg |= MIIM_88E151x_RGMII_RXTX_DELAY;
  311. else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
  312. reg |= MIIM_88E151x_RGMII_RX_DELAY;
  313. else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
  314. reg |= MIIM_88E151x_RGMII_TX_DELAY;
  315. phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E151x_PHY_MSCR, reg);
  316. phy_write(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE, 0);
  317. }
  318. /* soft reset */
  319. phy_reset(phydev);
  320. genphy_config_aneg(phydev);
  321. genphy_restart_aneg(phydev);
  322. return 0;
  323. }
  324. /* Marvell 88E1510 */
  325. static int m88e1510_config(struct phy_device *phydev)
  326. {
  327. /* Select page 3 */
  328. phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE,
  329. MIIM_88E1118_PHY_LED_PAGE);
  330. /* Enable INTn output on LED[2] */
  331. m88e1518_phy_writebits(phydev, MIIM_88E151x_LED_TIMER_CTRL,
  332. MIIM_88E151x_INT_EN_OFFS, 1, 1);
  333. /* Configure LEDs */
  334. /* LED[0]:0011 (ACT) */
  335. m88e1518_phy_writebits(phydev, MIIM_88E151x_LED_FUNC_CTRL,
  336. MIIM_88E151x_LED0_OFFS, MIIM_88E151x_LED_FLD_SZ,
  337. MIIM_88E151x_LED0_ACT);
  338. /* LED[1]:0110 (LINK 100/1000 Mbps) */
  339. m88e1518_phy_writebits(phydev, MIIM_88E151x_LED_FUNC_CTRL,
  340. MIIM_88E151x_LED1_OFFS, MIIM_88E151x_LED_FLD_SZ,
  341. MIIM_88E151x_LED1_100_1000_LINK);
  342. /* Reset page selection */
  343. phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0);
  344. return m88e1518_config(phydev);
  345. }
  346. /* Marvell 88E1118 */
  347. static int m88e1118_config(struct phy_device *phydev)
  348. {
  349. /* Change Page Number */
  350. phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0002);
  351. /* Delay RGMII TX and RX */
  352. phy_write(phydev, MDIO_DEVAD_NONE, 0x15, 0x1070);
  353. /* Change Page Number */
  354. phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0003);
  355. /* Adjust LED control */
  356. phy_write(phydev, MDIO_DEVAD_NONE, 0x10, 0x021e);
  357. /* Change Page Number */
  358. phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0000);
  359. return genphy_config_aneg(phydev);
  360. }
  361. static int m88e1118_startup(struct phy_device *phydev)
  362. {
  363. int ret;
  364. /* Change Page Number */
  365. phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0000);
  366. ret = genphy_update_link(phydev);
  367. if (ret)
  368. return ret;
  369. return m88e1xxx_parse_status(phydev);
  370. }
  371. /* Marvell 88E1121R */
  372. static int m88e1121_config(struct phy_device *phydev)
  373. {
  374. int pg;
  375. /* Configure the PHY */
  376. genphy_config_aneg(phydev);
  377. /* Switch the page to access the led register */
  378. pg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_PAGE);
  379. phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_PAGE,
  380. MIIM_88E1121_PHY_LED_PAGE);
  381. /* Configure leds */
  382. phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_LED_CTRL,
  383. MIIM_88E1121_PHY_LED_DEF);
  384. /* Restore the page pointer */
  385. phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_PAGE, pg);
  386. /* Disable IRQs and de-assert interrupt */
  387. phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_IRQ_EN, 0);
  388. phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_IRQ_STATUS);
  389. return 0;
  390. }
  391. /* Marvell 88E1145 */
  392. static int m88e1145_config(struct phy_device *phydev)
  393. {
  394. int reg;
  395. /* Errata E0, E1 */
  396. phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_PAGE, 0x001b);
  397. phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_CAL_OV, 0x418f);
  398. phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_PAGE, 0x0016);
  399. phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_CAL_OV, 0xa2da);
  400. phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1xxx_PHY_SCR,
  401. MIIM_88E1xxx_PHY_MDI_X_AUTO);
  402. reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_EXT_CR);
  403. if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
  404. reg |= MIIM_M88E1145_RGMII_RX_DELAY |
  405. MIIM_M88E1145_RGMII_TX_DELAY;
  406. phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_EXT_CR, reg);
  407. genphy_config_aneg(phydev);
  408. /* soft reset */
  409. reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR);
  410. reg |= BMCR_RESET;
  411. phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, reg);
  412. return 0;
  413. }
  414. static int m88e1145_startup(struct phy_device *phydev)
  415. {
  416. int ret;
  417. ret = genphy_update_link(phydev);
  418. if (ret)
  419. return ret;
  420. phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_LED_CONTROL,
  421. MIIM_88E1145_PHY_LED_DIRECT);
  422. return m88e1xxx_parse_status(phydev);
  423. }
  424. /* Marvell 88E1149S */
  425. static int m88e1149_config(struct phy_device *phydev)
  426. {
  427. phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1149_PHY_PAGE, 0x1f);
  428. phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x200c);
  429. phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1149_PHY_PAGE, 0x5);
  430. phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x0);
  431. phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
  432. genphy_config_aneg(phydev);
  433. phy_reset(phydev);
  434. return 0;
  435. }
  436. /* Marvell 88E1310 */
  437. static int m88e1310_config(struct phy_device *phydev)
  438. {
  439. u16 reg;
  440. /* LED link and activity */
  441. phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0003);
  442. reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_LED_CTRL);
  443. reg = (reg & ~0xf) | 0x1;
  444. phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_LED_CTRL, reg);
  445. /* Set LED2/INT to INT mode, low active */
  446. phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0003);
  447. reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_IRQ_EN);
  448. reg = (reg & 0x77ff) | 0x0880;
  449. phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_IRQ_EN, reg);
  450. /* Set RGMII delay */
  451. phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0002);
  452. reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_RGMII_CTRL);
  453. reg |= 0x0030;
  454. phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_RGMII_CTRL, reg);
  455. /* Ensure to return to page 0 */
  456. phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0000);
  457. return genphy_config_aneg(phydev);
  458. }
  459. static int m88e1680_config(struct phy_device *phydev)
  460. {
  461. /*
  462. * As per Marvell Release Notes - Alaska V 88E1680 Rev A2
  463. * Errata Section 4.1
  464. */
  465. u16 reg;
  466. int res;
  467. /* Matrix LED mode (not neede if single LED mode is used */
  468. phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0004);
  469. reg = phy_read(phydev, MDIO_DEVAD_NONE, 27);
  470. reg |= (1 << 5);
  471. phy_write(phydev, MDIO_DEVAD_NONE, 27, reg);
  472. /* QSGMII TX amplitude change */
  473. phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x00fd);
  474. phy_write(phydev, MDIO_DEVAD_NONE, 8, 0x0b53);
  475. phy_write(phydev, MDIO_DEVAD_NONE, 7, 0x200d);
  476. phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0000);
  477. /* EEE initialization */
  478. phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x00ff);
  479. phy_write(phydev, MDIO_DEVAD_NONE, 17, 0xb030);
  480. phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x215c);
  481. phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x00fc);
  482. phy_write(phydev, MDIO_DEVAD_NONE, 24, 0x888c);
  483. phy_write(phydev, MDIO_DEVAD_NONE, 25, 0x888c);
  484. phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0000);
  485. phy_write(phydev, MDIO_DEVAD_NONE, 0, 0x9140);
  486. res = genphy_config_aneg(phydev);
  487. if (res < 0)
  488. return res;
  489. /* soft reset */
  490. reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR);
  491. reg |= BMCR_RESET;
  492. phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, reg);
  493. return 0;
  494. }
  495. static struct phy_driver M88E1011S_driver = {
  496. .name = "Marvell 88E1011S",
  497. .uid = 0x1410c60,
  498. .mask = 0xffffff0,
  499. .features = PHY_GBIT_FEATURES,
  500. .config = &m88e1011s_config,
  501. .startup = &m88e1011s_startup,
  502. .shutdown = &genphy_shutdown,
  503. };
  504. static struct phy_driver M88E1111S_driver = {
  505. .name = "Marvell 88E1111S",
  506. .uid = 0x1410cc0,
  507. .mask = 0xffffff0,
  508. .features = PHY_GBIT_FEATURES,
  509. .config = &m88e1111s_config,
  510. .startup = &m88e1011s_startup,
  511. .shutdown = &genphy_shutdown,
  512. };
  513. static struct phy_driver M88E1118_driver = {
  514. .name = "Marvell 88E1118",
  515. .uid = 0x1410e10,
  516. .mask = 0xffffff0,
  517. .features = PHY_GBIT_FEATURES,
  518. .config = &m88e1118_config,
  519. .startup = &m88e1118_startup,
  520. .shutdown = &genphy_shutdown,
  521. };
  522. static struct phy_driver M88E1118R_driver = {
  523. .name = "Marvell 88E1118R",
  524. .uid = 0x1410e40,
  525. .mask = 0xffffff0,
  526. .features = PHY_GBIT_FEATURES,
  527. .config = &m88e1118_config,
  528. .startup = &m88e1118_startup,
  529. .shutdown = &genphy_shutdown,
  530. };
  531. static struct phy_driver M88E1121R_driver = {
  532. .name = "Marvell 88E1121R",
  533. .uid = 0x1410cb0,
  534. .mask = 0xffffff0,
  535. .features = PHY_GBIT_FEATURES,
  536. .config = &m88e1121_config,
  537. .startup = &genphy_startup,
  538. .shutdown = &genphy_shutdown,
  539. };
  540. static struct phy_driver M88E1145_driver = {
  541. .name = "Marvell 88E1145",
  542. .uid = 0x1410cd0,
  543. .mask = 0xffffff0,
  544. .features = PHY_GBIT_FEATURES,
  545. .config = &m88e1145_config,
  546. .startup = &m88e1145_startup,
  547. .shutdown = &genphy_shutdown,
  548. };
  549. static struct phy_driver M88E1149S_driver = {
  550. .name = "Marvell 88E1149S",
  551. .uid = 0x1410ca0,
  552. .mask = 0xffffff0,
  553. .features = PHY_GBIT_FEATURES,
  554. .config = &m88e1149_config,
  555. .startup = &m88e1011s_startup,
  556. .shutdown = &genphy_shutdown,
  557. };
  558. static struct phy_driver M88E1510_driver = {
  559. .name = "Marvell 88E1510",
  560. .uid = 0x1410dd0,
  561. .mask = 0xfffffff,
  562. .features = PHY_GBIT_FEATURES,
  563. .config = &m88e1510_config,
  564. .startup = &m88e1011s_startup,
  565. .shutdown = &genphy_shutdown,
  566. .readext = &m88e1xxx_phy_extread,
  567. .writeext = &m88e1xxx_phy_extwrite,
  568. };
  569. /*
  570. * This supports:
  571. * 88E1518, uid 0x1410dd1
  572. * 88E1512, uid 0x1410dd4
  573. */
  574. static struct phy_driver M88E1518_driver = {
  575. .name = "Marvell 88E1518",
  576. .uid = 0x1410dd0,
  577. .mask = 0xffffffa,
  578. .features = PHY_GBIT_FEATURES,
  579. .config = &m88e1518_config,
  580. .startup = &m88e1011s_startup,
  581. .shutdown = &genphy_shutdown,
  582. .readext = &m88e1xxx_phy_extread,
  583. .writeext = &m88e1xxx_phy_extwrite,
  584. };
  585. static struct phy_driver M88E1310_driver = {
  586. .name = "Marvell 88E1310",
  587. .uid = 0x01410e90,
  588. .mask = 0xffffff0,
  589. .features = PHY_GBIT_FEATURES,
  590. .config = &m88e1310_config,
  591. .startup = &m88e1011s_startup,
  592. .shutdown = &genphy_shutdown,
  593. };
  594. static struct phy_driver M88E1680_driver = {
  595. .name = "Marvell 88E1680",
  596. .uid = 0x1410ed0,
  597. .mask = 0xffffff0,
  598. .features = PHY_GBIT_FEATURES,
  599. .config = &m88e1680_config,
  600. .startup = &genphy_startup,
  601. .shutdown = &genphy_shutdown,
  602. };
  603. int phy_marvell_init(void)
  604. {
  605. phy_register(&M88E1310_driver);
  606. phy_register(&M88E1149S_driver);
  607. phy_register(&M88E1145_driver);
  608. phy_register(&M88E1121R_driver);
  609. phy_register(&M88E1118_driver);
  610. phy_register(&M88E1118R_driver);
  611. phy_register(&M88E1111S_driver);
  612. phy_register(&M88E1011S_driver);
  613. phy_register(&M88E1510_driver);
  614. phy_register(&M88E1518_driver);
  615. phy_register(&M88E1680_driver);
  616. return 0;
  617. }