coreboot.c 2.7 KB

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  1. /*
  2. * Copyright (c) 2011 The Chromium OS Authors.
  3. * (C) Copyright 2008
  4. * Graeme Russ, graeme.russ@gmail.com.
  5. *
  6. * SPDX-License-Identifier: GPL-2.0+
  7. */
  8. #include <common.h>
  9. #include <asm/u-boot-x86.h>
  10. #include <flash.h>
  11. #include <netdev.h>
  12. #include <ns16550.h>
  13. #include <asm/msr.h>
  14. #include <asm/cache.h>
  15. #include <asm/io.h>
  16. #include <asm/arch-coreboot/tables.h>
  17. #include <asm/arch-coreboot/sysinfo.h>
  18. #include <asm/arch/timestamp.h>
  19. DECLARE_GLOBAL_DATA_PTR;
  20. int arch_cpu_init(void)
  21. {
  22. int ret = get_coreboot_info(&lib_sysinfo);
  23. if (ret != 0) {
  24. printf("Failed to parse coreboot tables.\n");
  25. return ret;
  26. }
  27. timestamp_init();
  28. return x86_cpu_init_f();
  29. }
  30. int board_early_init_f(void)
  31. {
  32. return 0;
  33. }
  34. int board_early_init_r(void)
  35. {
  36. /* CPU Speed to 100MHz */
  37. gd->cpu_clk = 100000000;
  38. /* Crystal is 33.000MHz */
  39. gd->bus_clk = 33000000;
  40. return 0;
  41. }
  42. void show_boot_progress(int val)
  43. {
  44. #if MIN_PORT80_KCLOCKS_DELAY
  45. /*
  46. * Scale the time counter reading to avoid using 64 bit arithmetics.
  47. * Can't use get_timer() here becuase it could be not yet
  48. * initialized or even implemented.
  49. */
  50. if (!gd->arch.tsc_prev) {
  51. gd->arch.tsc_base_kclocks = rdtsc() / 1000;
  52. gd->arch.tsc_prev = 0;
  53. } else {
  54. uint32_t now;
  55. do {
  56. now = rdtsc() / 1000 - gd->arch.tsc_base_kclocks;
  57. } while (now < (gd->arch.tsc_prev + MIN_PORT80_KCLOCKS_DELAY));
  58. gd->arch.tsc_prev = now;
  59. }
  60. #endif
  61. outb(val, 0x80);
  62. }
  63. int print_cpuinfo(void)
  64. {
  65. return default_print_cpuinfo();
  66. }
  67. int last_stage_init(void)
  68. {
  69. if (gd->flags & GD_FLG_COLD_BOOT)
  70. timestamp_add_to_bootstage();
  71. return 0;
  72. }
  73. #ifndef CONFIG_SYS_NO_FLASH
  74. ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
  75. {
  76. return 0;
  77. }
  78. #endif
  79. int board_eth_init(bd_t *bis)
  80. {
  81. return pci_eth_init(bis);
  82. }
  83. #define MTRR_TYPE_WP 5
  84. #define MTRRcap_MSR 0xfe
  85. #define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg))
  86. #define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1)
  87. void board_final_cleanup(void)
  88. {
  89. /* Un-cache the ROM so the kernel has one
  90. * more MTRR available.
  91. *
  92. * Coreboot should have assigned this to the
  93. * top available variable MTRR.
  94. */
  95. u8 top_mtrr = (native_read_msr(MTRRcap_MSR) & 0xff) - 1;
  96. u8 top_type = native_read_msr(MTRRphysBase_MSR(top_mtrr)) & 0xff;
  97. /* Make sure this MTRR is the correct Write-Protected type */
  98. if (top_type == MTRR_TYPE_WP) {
  99. disable_caches();
  100. wrmsrl(MTRRphysBase_MSR(top_mtrr), 0);
  101. wrmsrl(MTRRphysMask_MSR(top_mtrr), 0);
  102. enable_caches();
  103. }
  104. /* Issue SMI to Coreboot to lock down ME and registers */
  105. printf("Finalizing Coreboot\n");
  106. outb(0xcb, 0xb2);
  107. }
  108. void panic_puts(const char *str)
  109. {
  110. NS16550_t port = (NS16550_t)0x3f8;
  111. NS16550_init(port, 1);
  112. while (*str)
  113. NS16550_putc(port, *str++);
  114. }