exynos5250-spring.dts 14 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596
  1. /*
  2. * Google Spring board device tree source
  3. *
  4. * Copyright (c) 2013 Google, Inc
  5. * Copyright (c) 2014 SUSE LINUX Products GmbH
  6. *
  7. * SPDX-License-Identifier: GPL-2.0
  8. */
  9. /dts-v1/;
  10. #include <dt-bindings/gpio/gpio.h>
  11. #include <dt-bindings/interrupt-controller/irq.h>
  12. #include <dt-bindings/input/input.h>
  13. #include "exynos5250.dtsi"
  14. / {
  15. model = "Google Spring";
  16. compatible = "google,spring", "samsung,exynos5250", "samsung,exynos5";
  17. aliases {
  18. i2c0 = "/i2c@12C60000";
  19. i2c1 = "/i2c@12C70000";
  20. i2c2 = "/i2c@12C80000";
  21. i2c3 = "/i2c@12C90000";
  22. i2c4 = "/i2c@12CA0000";
  23. i2c5 = "/i2c@12CB0000";
  24. i2c6 = "/i2c@12CC0000";
  25. i2c7 = "/i2c@12CD0000";
  26. i2c104 = &cros_ec_ldo_tunnel;
  27. spi0 = "/spi@12d20000";
  28. spi1 = "/spi@12d30000";
  29. spi2 = "/spi@12d40000";
  30. spi3 = "/spi@131a0000";
  31. spi4 = "/spi@131b0000";
  32. mmc0 = "/mmc@12000000";
  33. serial0 = "/serial@12C30000";
  34. console = "/serial@12C30000";
  35. i2s = "/sound@3830000";
  36. };
  37. memory {
  38. reg = <0x40000000 0x80000000>;
  39. };
  40. flash@0 {
  41. spl { /* spl size override */
  42. size = <0x8000>;
  43. };
  44. };
  45. chosen {
  46. bootargs = "console=tty1";
  47. stdout-path = "serial3:115200n8";
  48. };
  49. board-rev {
  50. compatible = "google,board-revision";
  51. google,board-rev-gpios = <&gpy4 0 0>, <&gpy4 1 0>,
  52. <&gpy4 2 0>;
  53. };
  54. i2c@12C90000 {
  55. clock-frequency = <100000>;
  56. tpm@20 {
  57. reg = <0x20>;
  58. compatible = "infineon,slb9645tt";
  59. };
  60. };
  61. mmc@12200000 {
  62. samsung,bus-width = <8>;
  63. samsung,timing = <1 3 3>;
  64. samsung,removable = <0>;
  65. };
  66. mmc@12210000 {
  67. status = "disabled";
  68. };
  69. mmc@12220000 {
  70. /* MMC2 pins are used as GPIO for eDP bridge */
  71. status = "disabled";
  72. };
  73. mmc@12230000 {
  74. status = "disabled";
  75. };
  76. ehci@12110000 {
  77. samsung,vbus-gpio = <&gpx1 1 GPIO_ACTIVE_HIGH>;
  78. status = "okay";
  79. };
  80. xhci@12000000 {
  81. samsung,vbus-gpio = <&gpx2 7 GPIO_ACTIVE_HIGH>;
  82. };
  83. spi@12d30000 {
  84. spi-max-frequency = <50000000>;
  85. firmware_storage_spi: flash@0 {
  86. compatible = "spi-flash";
  87. reg = <0>;
  88. };
  89. };
  90. tmu@10060000 {
  91. samsung,min-temp = <25>;
  92. samsung,max-temp = <125>;
  93. samsung,start-warning = <95>;
  94. samsung,start-tripping = <105>;
  95. samsung,hw-tripping = <110>;
  96. samsung,efuse-min-value = <40>;
  97. samsung,efuse-value = <55>;
  98. samsung,efuse-max-value = <100>;
  99. samsung,slope = <274761730>;
  100. samsung,dc-value = <25>;
  101. };
  102. fimd@14400000 {
  103. samsung,vl-freq = <60>;
  104. samsung,vl-col = <1366>;
  105. samsung,vl-row = <768>;
  106. samsung,vl-width = <1366>;
  107. samsung,vl-height = <768>;
  108. samsung,vl-clkp;
  109. samsung,vl-dp;
  110. samsung,vl-hsp;
  111. samsung,vl-vsp;
  112. samsung,vl-bpix = <4>;
  113. samsung,vl-hspw = <32>;
  114. samsung,vl-hbpd = <80>;
  115. samsung,vl-hfpd = <48>;
  116. samsung,vl-vspw = <5>;
  117. samsung,vl-vbpd = <14>;
  118. samsung,vl-vfpd = <3>;
  119. samsung,vl-cmd-allow-len = <0xf>;
  120. samsung,winid = <0>;
  121. samsung,interface-mode = <1>;
  122. samsung,dp-enabled = <1>;
  123. samsung,dual-lcd-enabled = <0>;
  124. };
  125. dp@145b0000 {
  126. samsung,lt-status = <0>;
  127. samsung,master-mode = <0>;
  128. samsung,bist-mode = <0>;
  129. samsung,bist-pattern = <0>;
  130. samsung,h-sync-polarity = <0>;
  131. samsung,v-sync-polarity = <0>;
  132. samsung,interlaced = <0>;
  133. samsung,color-space = <0>;
  134. samsung,dynamic-range = <0>;
  135. samsung,ycbcr-coeff = <0>;
  136. samsung,color-depth = <1>;
  137. };
  138. };
  139. &i2c_0 {
  140. status = "okay";
  141. samsung,i2c-sda-delay = <100>;
  142. samsung,i2c-max-bus-freq = <378000>;
  143. s5m8767-pmic@66 {
  144. compatible = "samsung,s5m8767-pmic";
  145. reg = <0x66>;
  146. interrupt-parent = <&gpx3>;
  147. wakeup-source;
  148. s5m8767,pmic-buck-dvs-gpios = <&gpd1 0 GPIO_ACTIVE_LOW>, /* DVS1 */
  149. <&gpd1 1 GPIO_ACTIVE_LOW>, /* DVS2 */
  150. <&gpd1 2 GPIO_ACTIVE_LOW>; /* DVS3 */
  151. s5m8767,pmic-buck-ds-gpios = <&gpx2 3 GPIO_ACTIVE_LOW>, /* SET1 */
  152. <&gpx2 4 GPIO_ACTIVE_LOW>, /* SET2 */
  153. <&gpx2 5 GPIO_ACTIVE_LOW>; /* SET3 */
  154. /*
  155. * The following arrays of DVS voltages are not used, since we are
  156. * not using GPIOs to control PMIC bucks, but they must be defined
  157. * to please the driver.
  158. */
  159. s5m8767,pmic-buck2-dvs-voltage = <1350000>, <1300000>,
  160. <1250000>, <1200000>,
  161. <1150000>, <1100000>,
  162. <1000000>, <950000>;
  163. s5m8767,pmic-buck3-dvs-voltage = <1100000>, <1100000>,
  164. <1100000>, <1100000>,
  165. <1000000>, <1000000>,
  166. <1000000>, <1000000>;
  167. s5m8767,pmic-buck4-dvs-voltage = <1200000>, <1200000>,
  168. <1200000>, <1200000>,
  169. <1200000>, <1200000>,
  170. <1200000>, <1200000>;
  171. clocks {
  172. compatible = "samsung,s5m8767-clk";
  173. #clock-cells = <1>;
  174. clock-output-names = "en32khz_ap",
  175. "en32khz_cp",
  176. "en32khz_bt";
  177. };
  178. regulators {
  179. ldo4_reg: LDO4 {
  180. regulator-name = "P1.0V_LDO_OUT4";
  181. regulator-min-microvolt = <1000000>;
  182. regulator-max-microvolt = <1000000>;
  183. regulator-always-on;
  184. op_mode = <0>;
  185. };
  186. ldo5_reg: LDO5 {
  187. regulator-name = "P1.8V_LDO_OUT5";
  188. regulator-min-microvolt = <1800000>;
  189. regulator-max-microvolt = <1800000>;
  190. regulator-always-on;
  191. op_mode = <0>;
  192. };
  193. ldo6_reg: LDO6 {
  194. regulator-name = "vdd_mydp";
  195. regulator-min-microvolt = <1200000>;
  196. regulator-max-microvolt = <1200000>;
  197. regulator-always-on;
  198. op_mode = <3>;
  199. };
  200. ldo7_reg: LDO7 {
  201. regulator-name = "P1.1V_LDO_OUT7";
  202. regulator-min-microvolt = <1100000>;
  203. regulator-max-microvolt = <1100000>;
  204. regulator-always-on;
  205. op_mode = <3>;
  206. };
  207. ldo8_reg: LDO8 {
  208. regulator-name = "P1.0V_LDO_OUT8";
  209. regulator-min-microvolt = <1000000>;
  210. regulator-max-microvolt = <1000000>;
  211. regulator-always-on;
  212. op_mode = <3>;
  213. };
  214. ldo10_reg: LDO10 {
  215. regulator-name = "P1.8V_LDO_OUT10";
  216. regulator-min-microvolt = <1800000>;
  217. regulator-max-microvolt = <1800000>;
  218. regulator-always-on;
  219. op_mode = <3>;
  220. };
  221. ldo11_reg: LDO11 {
  222. regulator-name = "P1.8V_LDO_OUT11";
  223. regulator-min-microvolt = <1800000>;
  224. regulator-max-microvolt = <1800000>;
  225. regulator-always-on;
  226. op_mode = <0>;
  227. };
  228. ldo12_reg: LDO12 {
  229. regulator-name = "P3.0V_LDO_OUT12";
  230. regulator-min-microvolt = <3000000>;
  231. regulator-max-microvolt = <3000000>;
  232. regulator-always-on;
  233. op_mode = <3>;
  234. };
  235. ldo13_reg: LDO13 {
  236. regulator-name = "P1.8V_LDO_OUT13";
  237. regulator-min-microvolt = <1800000>;
  238. regulator-max-microvolt = <1800000>;
  239. regulator-always-on;
  240. op_mode = <0>;
  241. };
  242. ldo14_reg: LDO14 {
  243. regulator-name = "P1.8V_LDO_OUT14";
  244. regulator-min-microvolt = <1800000>;
  245. regulator-max-microvolt = <1800000>;
  246. regulator-always-on;
  247. op_mode = <3>;
  248. };
  249. ldo15_reg: LDO15 {
  250. regulator-name = "P1.0V_LDO_OUT15";
  251. regulator-min-microvolt = <1000000>;
  252. regulator-max-microvolt = <1000000>;
  253. regulator-always-on;
  254. op_mode = <3>;
  255. };
  256. ldo16_reg: LDO16 {
  257. regulator-name = "P1.8V_LDO_OUT16";
  258. regulator-min-microvolt = <1800000>;
  259. regulator-max-microvolt = <1800000>;
  260. regulator-always-on;
  261. op_mode = <3>;
  262. };
  263. ldo17_reg: LDO17 {
  264. regulator-name = "P1.2V_LDO_OUT17";
  265. regulator-min-microvolt = <1200000>;
  266. regulator-max-microvolt = <1200000>;
  267. regulator-always-on;
  268. op_mode = <0>;
  269. };
  270. ldo25_reg: LDO25 {
  271. regulator-name = "vdd_bridge";
  272. regulator-min-microvolt = <1200000>;
  273. regulator-max-microvolt = <1200000>;
  274. regulator-always-on;
  275. op_mode = <1>;
  276. };
  277. buck1_reg: BUCK1 {
  278. regulator-name = "vdd_mif";
  279. regulator-min-microvolt = <950000>;
  280. regulator-max-microvolt = <1300000>;
  281. regulator-always-on;
  282. regulator-boot-on;
  283. op_mode = <3>;
  284. };
  285. buck2_reg: BUCK2 {
  286. regulator-name = "vdd_arm";
  287. regulator-min-microvolt = <850000>;
  288. regulator-max-microvolt = <1350000>;
  289. regulator-always-on;
  290. regulator-boot-on;
  291. op_mode = <3>;
  292. };
  293. buck3_reg: BUCK3 {
  294. regulator-name = "vdd_int";
  295. regulator-min-microvolt = <900000>;
  296. regulator-max-microvolt = <1200000>;
  297. regulator-always-on;
  298. regulator-boot-on;
  299. op_mode = <3>;
  300. };
  301. buck4_reg: BUCK4 {
  302. regulator-name = "vdd_g3d";
  303. regulator-min-microvolt = <850000>;
  304. regulator-max-microvolt = <1300000>;
  305. regulator-boot-on;
  306. op_mode = <3>;
  307. };
  308. buck5_reg: BUCK5 {
  309. regulator-name = "P1.8V_BUCK_OUT5";
  310. regulator-min-microvolt = <1800000>;
  311. regulator-max-microvolt = <1800000>;
  312. regulator-always-on;
  313. regulator-boot-on;
  314. op_mode = <1>;
  315. };
  316. buck6_reg: BUCK6 {
  317. regulator-name = "P1.2V_BUCK_OUT6";
  318. regulator-min-microvolt = <2050000>;
  319. regulator-max-microvolt = <2050000>;
  320. regulator-always-on;
  321. regulator-boot-on;
  322. op_mode = <0>;
  323. };
  324. buck9_reg: BUCK9 {
  325. regulator-name = "vdd_ummc";
  326. regulator-min-microvolt = <950000>;
  327. regulator-max-microvolt = <3000000>;
  328. regulator-always-on;
  329. regulator-boot-on;
  330. op_mode = <3>;
  331. };
  332. };
  333. };
  334. };
  335. &i2c_1 {
  336. status = "okay";
  337. samsung,i2c-sda-delay = <100>;
  338. samsung,i2c-max-bus-freq = <378000>;
  339. };
  340. &i2c_2 {
  341. status = "okay";
  342. samsung,i2c-sda-delay = <100>;
  343. samsung,i2c-max-bus-freq = <66000>;
  344. };
  345. &i2c_3 {
  346. status = "okay";
  347. samsung,i2c-sda-delay = <100>;
  348. samsung,i2c-max-bus-freq = <66000>;
  349. };
  350. &i2c_4 {
  351. status = "okay";
  352. samsung,i2c-sda-delay = <100>;
  353. samsung,i2c-max-bus-freq = <66000>;
  354. clock-frequency = <66000>;
  355. cros_ec: embedded-controller {
  356. compatible = "google,cros-ec-i2c";
  357. reg = <0x1e>;
  358. interrupts = <6 IRQ_TYPE_NONE>;
  359. interrupt-parent = <&gpx1>;
  360. wakeup-source;
  361. u-boot,i2c-offset-len = <0>;
  362. ec-interrupt = <&gpx1 6 GPIO_ACTIVE_LOW>;
  363. cros_ec_ldo_tunnel: cros-ec-ldo-tunnel {
  364. compatible = "google,cros-ec-ldo-tunnel";
  365. #address-cells = <1>;
  366. #size-cells = <0>;
  367. power-regulator {
  368. compatible = "ti,tps65090";
  369. reg = <0x48>;
  370. regulators {
  371. dcdc1 {
  372. ti,enable-ext-control;
  373. };
  374. dcdc2 {
  375. ti,enable-ext-control;
  376. };
  377. dcdc3 {
  378. ti,enable-ext-control;
  379. };
  380. fet1: fet1 {
  381. regulator-name = "vcd_led";
  382. ti,overcurrent-wait = <3>;
  383. };
  384. tps65090_fet2: fet2 {
  385. regulator-name = "video_mid";
  386. regulator-always-on;
  387. ti,overcurrent-wait = <3>;
  388. };
  389. fet3 {
  390. regulator-name = "wwan_r";
  391. regulator-always-on;
  392. ti,overcurrent-wait = <3>;
  393. };
  394. fet4 {
  395. regulator-name = "sdcard";
  396. ti,overcurrent-wait = <3>;
  397. };
  398. fet5 {
  399. regulator-name = "camout";
  400. regulator-always-on;
  401. ti,overcurrent-wait = <3>;
  402. };
  403. fet6: fet6 {
  404. regulator-name = "lcd_vdd";
  405. ti,overcurrent-wait = <3>;
  406. };
  407. tps65090_fet7: fet7 {
  408. regulator-name = "video_mid_1a";
  409. regulator-always-on;
  410. ti,overcurrent-wait = <3>;
  411. };
  412. ldo1 {
  413. };
  414. ldo2 {
  415. };
  416. };
  417. };
  418. };
  419. };
  420. };
  421. &i2c_5 {
  422. status = "okay";
  423. samsung,i2c-sda-delay = <100>;
  424. samsung,i2c-max-bus-freq = <66000>;
  425. };
  426. &i2c_7 {
  427. status = "okay";
  428. samsung,i2c-sda-delay = <100>;
  429. samsung,i2c-max-bus-freq = <66000>;
  430. ps8622-bridge@8 {
  431. compatible = "parade,ps8622";
  432. reg = <0x8>;
  433. sleep-gpios = <&gpc3 6 GPIO_ACTIVE_LOW>;
  434. reset-gpios = <&gpc3 1 GPIO_ACTIVE_LOW>;
  435. hotplug-gpios = <&gpc3 0 GPIO_ACTIVE_HIGH>;
  436. power-supply = <&ldo6_reg>;
  437. parade,regs = /bits/ 8 <
  438. 0x02 0xa1 0x01 /* HPD low */
  439. /*
  440. * SW setting: [1:0] SW output 1.2V voltage is
  441. * lower to 96%
  442. */
  443. 0x04 0x14 0x01
  444. /* RCO SS setting: [5:4] = b01 0.5%, b10 1%, b11 1.5% */
  445. 0x04 0xe3 0x20
  446. 0x04 0xe2 0x80 /* [7] RCO SS enable */
  447. /*
  448. * RPHY Setting: [3:2] CDR tune wait cycle before
  449. * measure for fine tune b00: 1us,
  450. * 01: 0.5us, 10:2us, 11:4us
  451. */
  452. 0x04 0x8a 0x0c
  453. 0x04 0x89 0x08 /* [3] RFD always on */
  454. /*
  455. * CTN lock in/out: 20000ppm/80000ppm. Lock out 2 times
  456. */
  457. 0x04 0x71 0x2d
  458. /* 2.7G CDR settings */
  459. 0x04 0x7d 0x07 /* NOF=40LSB for HBR CDR setting */
  460. 0x04 0x7b 0x00 /* [1:0] Fmin=+4bands */
  461. 0x04 0x7a 0xfd /* [7:5] DCO_FTRNG=+-40% */
  462. /*
  463. * 1.62G CDR settings:
  464. * [5:2]NOF=64LSB [1:0]DCO scale is 2/5
  465. */
  466. 0x04 0xc0 0x12
  467. 0x04 0xc1 0x92 /* Gitune=-37% */
  468. 0x04 0xc2 0x1c /* Fbstep=100% */
  469. 0x04 0x32 0x80 /* [7] LOS signal disable */
  470. /* RPIO Setting */
  471. /* [7:4] LVDS driver bias current 75% (250mV swing) */
  472. 0x04 0x00 0xb0
  473. /* [7:6] Right-bar GPIO output strength is 8mA */
  474. 0x04 0x15 0x40
  475. /* EQ Training State Machine Setting */
  476. 0x04 0x54 0x10 /* RCO calibration start */
  477. /* [4:0] MAX_LANE_COUNT set to one lane */
  478. 0x01 0x02 0x81
  479. /* [4:0] LANE_COUNT_SET set to one lane */
  480. 0x01 0x21 0x81
  481. 0x00 0x52 0x20
  482. 0x00 0xf1 0x03 /* HPD CP toggle enable */
  483. 0x00 0x62 0x41
  484. /* Counter number add 1ms counter delay */
  485. 0x00 0xf6 0x01
  486. /*
  487. * [6]PWM function control by DPCD0040f[7], default
  488. * is PWM block always works
  489. */
  490. 0x00 0x77 0x06
  491. 0x00 0x4c 0x04
  492. /*
  493. * 04h Adjust VTotal tolerance to fix the 30Hz no-
  494. * display issue
  495. * DPCD00400='h00 Parade OUI = 'h001cf8
  496. */
  497. 0x01 0xc0 0x00
  498. 0x01 0xc1 0x1c /* DPCD00401='h1c */
  499. 0x01 0xc2 0xf8 /* DPCD00402='hf8 */
  500. /* DPCD403~408 = ASCII code D2SLV5='h4432534c5635 */
  501. 0x01 0xc3 0x44
  502. 0x01 0xc4 0x32 /* DPCD404 */
  503. 0x01 0xc5 0x53 /* DPCD405 */
  504. 0x01 0xc6 0x4c /* DPCD406 */
  505. 0x01 0xc7 0x56 /* DPCD407 */
  506. 0x01 0xc8 0x35 /* DPCD408 */
  507. /* DPCD40A Initial Code major revision '01' */
  508. 0x01 0xca 0x01
  509. /* DPCD40B Initial Code minor revision '05' */
  510. 0x01 0xcb 0x05
  511. 0x01 0xa5 0xa0 /* DPCD720, Select internal PWM */
  512. /*
  513. * 0xff for 100% PWM of brightness, 0h for 0% brightness
  514. */
  515. 0x01 0xa7 0x00
  516. /*
  517. * Set LVDS output as 6bit-VESA mapping, single LVDS
  518. * channel
  519. */
  520. 0x01 0xcc 0x13
  521. 0x02 0xb1 0x20 /* Enable SSC set by register */
  522. /* Set SSC enabled and +/-1% central spreading */
  523. 0x04 0x10 0x16
  524. 0x04 0x59 0x60 /* MPU Clock source: LC => RCO */
  525. 0x04 0x54 0x14 /* LC -> RCO */
  526. 0x02 0xa1 0x91>; /* HPD high */
  527. };
  528. soundcodec@20 {
  529. reg = <0x20>;
  530. compatible = "maxim,max98088-codec";
  531. };
  532. };
  533. #include "cros-ec-keyboard.dtsi"