clock-k2e.c 3.1 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117
  1. /*
  2. * Keystone2: get clk rate for K2E
  3. *
  4. * (C) Copyright 2012-2014
  5. * Texas Instruments Incorporated, <www.ti.com>
  6. *
  7. * SPDX-License-Identifier: GPL-2.0+
  8. */
  9. #include <common.h>
  10. #include <asm/arch/clock.h>
  11. #include <asm/arch/clock_defs.h>
  12. const struct keystone_pll_regs keystone_pll_regs[] = {
  13. [CORE_PLL] = {KS2_MAINPLLCTL0, KS2_MAINPLLCTL1},
  14. [PASS_PLL] = {KS2_PASSPLLCTL0, KS2_PASSPLLCTL1},
  15. [DDR3_PLL] = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1},
  16. };
  17. int dev_speeds[] = {
  18. SPD800,
  19. SPD850,
  20. SPD1000,
  21. SPD1250,
  22. SPD1350,
  23. SPD1400,
  24. SPD1500,
  25. SPD1400,
  26. SPD1350,
  27. SPD1250,
  28. SPD1000,
  29. SPD850,
  30. SPD800
  31. };
  32. /**
  33. * pll_freq_get - get pll frequency
  34. * Fout = Fref * NF(mult) / NR(prediv) / OD
  35. * @pll: pll identifier
  36. */
  37. static unsigned long pll_freq_get(int pll)
  38. {
  39. unsigned long mult = 1, prediv = 1, output_div = 2;
  40. unsigned long ret;
  41. u32 tmp, reg;
  42. if (pll == CORE_PLL) {
  43. ret = external_clk[sys_clk];
  44. if (pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN) {
  45. /* PLL mode */
  46. tmp = __raw_readl(KS2_MAINPLLCTL0);
  47. prediv = (tmp & PLL_DIV_MASK) + 1;
  48. mult = (((tmp & PLLM_MULT_HI_SMASK) >> 6) |
  49. (pllctl_reg_read(pll, mult) &
  50. PLLM_MULT_LO_MASK)) + 1;
  51. output_div = ((pllctl_reg_read(pll, secctl) >>
  52. PLL_CLKOD_SHIFT) & PLL_CLKOD_MASK) + 1;
  53. ret = ret / prediv / output_div * mult;
  54. }
  55. } else {
  56. switch (pll) {
  57. case PASS_PLL:
  58. ret = external_clk[pa_clk];
  59. reg = KS2_PASSPLLCTL0;
  60. break;
  61. case DDR3_PLL:
  62. ret = external_clk[ddr3_clk];
  63. reg = KS2_DDR3APLLCTL0;
  64. break;
  65. default:
  66. return 0;
  67. }
  68. tmp = __raw_readl(reg);
  69. if (!(tmp & PLLCTL_BYPASS)) {
  70. /* Bypass disabled */
  71. prediv = (tmp & PLL_DIV_MASK) + 1;
  72. mult = ((tmp >> PLL_MULT_SHIFT) & PLL_MULT_MASK) + 1;
  73. output_div = ((tmp >> PLL_CLKOD_SHIFT) &
  74. PLL_CLKOD_MASK) + 1;
  75. ret = ((ret / prediv) * mult) / output_div;
  76. }
  77. }
  78. return ret;
  79. }
  80. unsigned long clk_get_rate(unsigned int clk)
  81. {
  82. switch (clk) {
  83. case core_pll_clk: return pll_freq_get(CORE_PLL);
  84. case pass_pll_clk: return pll_freq_get(PASS_PLL);
  85. case ddr3_pll_clk: return pll_freq_get(DDR3_PLL);
  86. case sys_clk0_1_clk:
  87. case sys_clk0_clk: return pll_freq_get(CORE_PLL) / pll0div_read(1);
  88. case sys_clk1_clk: return pll_freq_get(CORE_PLL) / pll0div_read(2);
  89. case sys_clk2_clk: return pll_freq_get(CORE_PLL) / pll0div_read(3);
  90. case sys_clk3_clk: return pll_freq_get(CORE_PLL) / pll0div_read(4);
  91. case sys_clk0_2_clk: return clk_get_rate(sys_clk0_clk) / 2;
  92. case sys_clk0_3_clk: return clk_get_rate(sys_clk0_clk) / 3;
  93. case sys_clk0_4_clk: return clk_get_rate(sys_clk0_clk) / 4;
  94. case sys_clk0_6_clk: return clk_get_rate(sys_clk0_clk) / 6;
  95. case sys_clk0_8_clk: return clk_get_rate(sys_clk0_clk) / 8;
  96. case sys_clk0_12_clk: return clk_get_rate(sys_clk0_clk) / 12;
  97. case sys_clk0_24_clk: return clk_get_rate(sys_clk0_clk) / 24;
  98. case sys_clk1_3_clk: return clk_get_rate(sys_clk1_clk) / 3;
  99. case sys_clk1_4_clk: return clk_get_rate(sys_clk1_clk) / 4;
  100. case sys_clk1_6_clk: return clk_get_rate(sys_clk1_clk) / 6;
  101. case sys_clk1_12_clk: return clk_get_rate(sys_clk1_clk) / 12;
  102. default:
  103. break;
  104. }
  105. return 0;
  106. }