mmc.c 41 KB

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  1. /*
  2. * Copyright 2008, Freescale Semiconductor, Inc
  3. * Andy Fleming
  4. *
  5. * Based vaguely on the Linux code
  6. *
  7. * SPDX-License-Identifier: GPL-2.0+
  8. */
  9. #include <config.h>
  10. #include <common.h>
  11. #include <command.h>
  12. #include <errno.h>
  13. #include <mmc.h>
  14. #include <part.h>
  15. #include <malloc.h>
  16. #include <linux/list.h>
  17. #include <div64.h>
  18. #include "mmc_private.h"
  19. static struct list_head mmc_devices;
  20. static int cur_dev_num = -1;
  21. __weak int board_mmc_getwp(struct mmc *mmc)
  22. {
  23. return -1;
  24. }
  25. int mmc_getwp(struct mmc *mmc)
  26. {
  27. int wp;
  28. wp = board_mmc_getwp(mmc);
  29. if (wp < 0) {
  30. if (mmc->cfg->ops->getwp)
  31. wp = mmc->cfg->ops->getwp(mmc);
  32. else
  33. wp = 0;
  34. }
  35. return wp;
  36. }
  37. __weak int board_mmc_getcd(struct mmc *mmc)
  38. {
  39. return -1;
  40. }
  41. int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
  42. {
  43. int ret;
  44. #ifdef CONFIG_MMC_TRACE
  45. int i;
  46. u8 *ptr;
  47. printf("CMD_SEND:%d\n", cmd->cmdidx);
  48. printf("\t\tARG\t\t\t 0x%08X\n", cmd->cmdarg);
  49. ret = mmc->cfg->ops->send_cmd(mmc, cmd, data);
  50. switch (cmd->resp_type) {
  51. case MMC_RSP_NONE:
  52. printf("\t\tMMC_RSP_NONE\n");
  53. break;
  54. case MMC_RSP_R1:
  55. printf("\t\tMMC_RSP_R1,5,6,7 \t 0x%08X \n",
  56. cmd->response[0]);
  57. break;
  58. case MMC_RSP_R1b:
  59. printf("\t\tMMC_RSP_R1b\t\t 0x%08X \n",
  60. cmd->response[0]);
  61. break;
  62. case MMC_RSP_R2:
  63. printf("\t\tMMC_RSP_R2\t\t 0x%08X \n",
  64. cmd->response[0]);
  65. printf("\t\t \t\t 0x%08X \n",
  66. cmd->response[1]);
  67. printf("\t\t \t\t 0x%08X \n",
  68. cmd->response[2]);
  69. printf("\t\t \t\t 0x%08X \n",
  70. cmd->response[3]);
  71. printf("\n");
  72. printf("\t\t\t\t\tDUMPING DATA\n");
  73. for (i = 0; i < 4; i++) {
  74. int j;
  75. printf("\t\t\t\t\t%03d - ", i*4);
  76. ptr = (u8 *)&cmd->response[i];
  77. ptr += 3;
  78. for (j = 0; j < 4; j++)
  79. printf("%02X ", *ptr--);
  80. printf("\n");
  81. }
  82. break;
  83. case MMC_RSP_R3:
  84. printf("\t\tMMC_RSP_R3,4\t\t 0x%08X \n",
  85. cmd->response[0]);
  86. break;
  87. default:
  88. printf("\t\tERROR MMC rsp not supported\n");
  89. break;
  90. }
  91. #else
  92. ret = mmc->cfg->ops->send_cmd(mmc, cmd, data);
  93. #endif
  94. return ret;
  95. }
  96. int mmc_send_status(struct mmc *mmc, int timeout)
  97. {
  98. struct mmc_cmd cmd;
  99. int err, retries = 5;
  100. #ifdef CONFIG_MMC_TRACE
  101. int status;
  102. #endif
  103. cmd.cmdidx = MMC_CMD_SEND_STATUS;
  104. cmd.resp_type = MMC_RSP_R1;
  105. if (!mmc_host_is_spi(mmc))
  106. cmd.cmdarg = mmc->rca << 16;
  107. do {
  108. err = mmc_send_cmd(mmc, &cmd, NULL);
  109. if (!err) {
  110. if ((cmd.response[0] & MMC_STATUS_RDY_FOR_DATA) &&
  111. (cmd.response[0] & MMC_STATUS_CURR_STATE) !=
  112. MMC_STATE_PRG)
  113. break;
  114. else if (cmd.response[0] & MMC_STATUS_MASK) {
  115. #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
  116. printf("Status Error: 0x%08X\n",
  117. cmd.response[0]);
  118. #endif
  119. return COMM_ERR;
  120. }
  121. } else if (--retries < 0)
  122. return err;
  123. udelay(1000);
  124. } while (timeout--);
  125. #ifdef CONFIG_MMC_TRACE
  126. status = (cmd.response[0] & MMC_STATUS_CURR_STATE) >> 9;
  127. printf("CURR STATE:%d\n", status);
  128. #endif
  129. if (timeout <= 0) {
  130. #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
  131. printf("Timeout waiting card ready\n");
  132. #endif
  133. return TIMEOUT;
  134. }
  135. if (cmd.response[0] & MMC_STATUS_SWITCH_ERROR)
  136. return SWITCH_ERR;
  137. return 0;
  138. }
  139. int mmc_set_blocklen(struct mmc *mmc, int len)
  140. {
  141. struct mmc_cmd cmd;
  142. if (mmc->ddr_mode)
  143. return 0;
  144. cmd.cmdidx = MMC_CMD_SET_BLOCKLEN;
  145. cmd.resp_type = MMC_RSP_R1;
  146. cmd.cmdarg = len;
  147. return mmc_send_cmd(mmc, &cmd, NULL);
  148. }
  149. struct mmc *find_mmc_device(int dev_num)
  150. {
  151. struct mmc *m;
  152. struct list_head *entry;
  153. list_for_each(entry, &mmc_devices) {
  154. m = list_entry(entry, struct mmc, link);
  155. if (m->block_dev.dev == dev_num)
  156. return m;
  157. }
  158. #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
  159. printf("MMC Device %d not found\n", dev_num);
  160. #endif
  161. return NULL;
  162. }
  163. static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start,
  164. lbaint_t blkcnt)
  165. {
  166. struct mmc_cmd cmd;
  167. struct mmc_data data;
  168. if (blkcnt > 1)
  169. cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK;
  170. else
  171. cmd.cmdidx = MMC_CMD_READ_SINGLE_BLOCK;
  172. if (mmc->high_capacity)
  173. cmd.cmdarg = start;
  174. else
  175. cmd.cmdarg = start * mmc->read_bl_len;
  176. cmd.resp_type = MMC_RSP_R1;
  177. data.dest = dst;
  178. data.blocks = blkcnt;
  179. data.blocksize = mmc->read_bl_len;
  180. data.flags = MMC_DATA_READ;
  181. if (mmc_send_cmd(mmc, &cmd, &data))
  182. return 0;
  183. if (blkcnt > 1) {
  184. cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
  185. cmd.cmdarg = 0;
  186. cmd.resp_type = MMC_RSP_R1b;
  187. if (mmc_send_cmd(mmc, &cmd, NULL)) {
  188. #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
  189. printf("mmc fail to send stop cmd\n");
  190. #endif
  191. return 0;
  192. }
  193. }
  194. return blkcnt;
  195. }
  196. static ulong mmc_bread(int dev_num, lbaint_t start, lbaint_t blkcnt, void *dst)
  197. {
  198. lbaint_t cur, blocks_todo = blkcnt;
  199. if (blkcnt == 0)
  200. return 0;
  201. struct mmc *mmc = find_mmc_device(dev_num);
  202. if (!mmc)
  203. return 0;
  204. if ((start + blkcnt) > mmc->block_dev.lba) {
  205. #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
  206. printf("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n",
  207. start + blkcnt, mmc->block_dev.lba);
  208. #endif
  209. return 0;
  210. }
  211. if (mmc_set_blocklen(mmc, mmc->read_bl_len))
  212. return 0;
  213. do {
  214. cur = (blocks_todo > mmc->cfg->b_max) ?
  215. mmc->cfg->b_max : blocks_todo;
  216. if(mmc_read_blocks(mmc, dst, start, cur) != cur)
  217. return 0;
  218. blocks_todo -= cur;
  219. start += cur;
  220. dst += cur * mmc->read_bl_len;
  221. } while (blocks_todo > 0);
  222. return blkcnt;
  223. }
  224. static int mmc_go_idle(struct mmc *mmc)
  225. {
  226. struct mmc_cmd cmd;
  227. int err;
  228. udelay(1000);
  229. cmd.cmdidx = MMC_CMD_GO_IDLE_STATE;
  230. cmd.cmdarg = 0;
  231. cmd.resp_type = MMC_RSP_NONE;
  232. err = mmc_send_cmd(mmc, &cmd, NULL);
  233. if (err)
  234. return err;
  235. udelay(2000);
  236. return 0;
  237. }
  238. static int sd_send_op_cond(struct mmc *mmc)
  239. {
  240. int timeout = 1000;
  241. int err;
  242. struct mmc_cmd cmd;
  243. do {
  244. cmd.cmdidx = MMC_CMD_APP_CMD;
  245. cmd.resp_type = MMC_RSP_R1;
  246. cmd.cmdarg = 0;
  247. err = mmc_send_cmd(mmc, &cmd, NULL);
  248. if (err)
  249. return err;
  250. cmd.cmdidx = SD_CMD_APP_SEND_OP_COND;
  251. cmd.resp_type = MMC_RSP_R3;
  252. /*
  253. * Most cards do not answer if some reserved bits
  254. * in the ocr are set. However, Some controller
  255. * can set bit 7 (reserved for low voltages), but
  256. * how to manage low voltages SD card is not yet
  257. * specified.
  258. */
  259. cmd.cmdarg = mmc_host_is_spi(mmc) ? 0 :
  260. (mmc->cfg->voltages & 0xff8000);
  261. if (mmc->version == SD_VERSION_2)
  262. cmd.cmdarg |= OCR_HCS;
  263. err = mmc_send_cmd(mmc, &cmd, NULL);
  264. if (err)
  265. return err;
  266. udelay(1000);
  267. } while ((!(cmd.response[0] & OCR_BUSY)) && timeout--);
  268. if (timeout <= 0)
  269. return UNUSABLE_ERR;
  270. if (mmc->version != SD_VERSION_2)
  271. mmc->version = SD_VERSION_1_0;
  272. if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
  273. cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
  274. cmd.resp_type = MMC_RSP_R3;
  275. cmd.cmdarg = 0;
  276. err = mmc_send_cmd(mmc, &cmd, NULL);
  277. if (err)
  278. return err;
  279. }
  280. mmc->ocr = cmd.response[0];
  281. mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
  282. mmc->rca = 0;
  283. return 0;
  284. }
  285. /* We pass in the cmd since otherwise the init seems to fail */
  286. static int mmc_send_op_cond_iter(struct mmc *mmc, struct mmc_cmd *cmd,
  287. int use_arg)
  288. {
  289. int err;
  290. cmd->cmdidx = MMC_CMD_SEND_OP_COND;
  291. cmd->resp_type = MMC_RSP_R3;
  292. cmd->cmdarg = 0;
  293. if (use_arg && !mmc_host_is_spi(mmc)) {
  294. cmd->cmdarg =
  295. (mmc->cfg->voltages &
  296. (mmc->op_cond_response & OCR_VOLTAGE_MASK)) |
  297. (mmc->op_cond_response & OCR_ACCESS_MODE);
  298. if (mmc->cfg->host_caps & MMC_MODE_HC)
  299. cmd->cmdarg |= OCR_HCS;
  300. }
  301. err = mmc_send_cmd(mmc, cmd, NULL);
  302. if (err)
  303. return err;
  304. mmc->op_cond_response = cmd->response[0];
  305. return 0;
  306. }
  307. static int mmc_send_op_cond(struct mmc *mmc)
  308. {
  309. struct mmc_cmd cmd;
  310. int err, i;
  311. /* Some cards seem to need this */
  312. mmc_go_idle(mmc);
  313. /* Asking to the card its capabilities */
  314. mmc->op_cond_pending = 1;
  315. for (i = 0; i < 2; i++) {
  316. err = mmc_send_op_cond_iter(mmc, &cmd, i != 0);
  317. if (err)
  318. return err;
  319. /* exit if not busy (flag seems to be inverted) */
  320. if (mmc->op_cond_response & OCR_BUSY)
  321. return 0;
  322. }
  323. return IN_PROGRESS;
  324. }
  325. static int mmc_complete_op_cond(struct mmc *mmc)
  326. {
  327. struct mmc_cmd cmd;
  328. int timeout = 1000;
  329. uint start;
  330. int err;
  331. mmc->op_cond_pending = 0;
  332. start = get_timer(0);
  333. do {
  334. err = mmc_send_op_cond_iter(mmc, &cmd, 1);
  335. if (err)
  336. return err;
  337. if (get_timer(start) > timeout)
  338. return UNUSABLE_ERR;
  339. udelay(100);
  340. } while (!(mmc->op_cond_response & OCR_BUSY));
  341. if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
  342. cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
  343. cmd.resp_type = MMC_RSP_R3;
  344. cmd.cmdarg = 0;
  345. err = mmc_send_cmd(mmc, &cmd, NULL);
  346. if (err)
  347. return err;
  348. }
  349. mmc->version = MMC_VERSION_UNKNOWN;
  350. mmc->ocr = cmd.response[0];
  351. mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
  352. mmc->rca = 1;
  353. return 0;
  354. }
  355. static int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd)
  356. {
  357. struct mmc_cmd cmd;
  358. struct mmc_data data;
  359. int err;
  360. /* Get the Card Status Register */
  361. cmd.cmdidx = MMC_CMD_SEND_EXT_CSD;
  362. cmd.resp_type = MMC_RSP_R1;
  363. cmd.cmdarg = 0;
  364. data.dest = (char *)ext_csd;
  365. data.blocks = 1;
  366. data.blocksize = MMC_MAX_BLOCK_LEN;
  367. data.flags = MMC_DATA_READ;
  368. err = mmc_send_cmd(mmc, &cmd, &data);
  369. return err;
  370. }
  371. static int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value)
  372. {
  373. struct mmc_cmd cmd;
  374. int timeout = 1000;
  375. int ret;
  376. cmd.cmdidx = MMC_CMD_SWITCH;
  377. cmd.resp_type = MMC_RSP_R1b;
  378. cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) |
  379. (index << 16) |
  380. (value << 8);
  381. ret = mmc_send_cmd(mmc, &cmd, NULL);
  382. /* Waiting for the ready status */
  383. if (!ret)
  384. ret = mmc_send_status(mmc, timeout);
  385. return ret;
  386. }
  387. static int mmc_change_freq(struct mmc *mmc)
  388. {
  389. ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
  390. char cardtype;
  391. int err;
  392. mmc->card_caps = 0;
  393. if (mmc_host_is_spi(mmc))
  394. return 0;
  395. /* Only version 4 supports high-speed */
  396. if (mmc->version < MMC_VERSION_4)
  397. return 0;
  398. mmc->card_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT;
  399. err = mmc_send_ext_csd(mmc, ext_csd);
  400. if (err)
  401. return err;
  402. cardtype = ext_csd[EXT_CSD_CARD_TYPE] & 0xf;
  403. err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING, 1);
  404. if (err)
  405. return err == SWITCH_ERR ? 0 : err;
  406. /* Now check to see that it worked */
  407. err = mmc_send_ext_csd(mmc, ext_csd);
  408. if (err)
  409. return err;
  410. /* No high-speed support */
  411. if (!ext_csd[EXT_CSD_HS_TIMING])
  412. return 0;
  413. /* High Speed is set, there are two types: 52MHz and 26MHz */
  414. if (cardtype & EXT_CSD_CARD_TYPE_52) {
  415. if (cardtype & EXT_CSD_CARD_TYPE_DDR_1_8V)
  416. mmc->card_caps |= MMC_MODE_DDR_52MHz;
  417. mmc->card_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
  418. } else {
  419. mmc->card_caps |= MMC_MODE_HS;
  420. }
  421. return 0;
  422. }
  423. static int mmc_set_capacity(struct mmc *mmc, int part_num)
  424. {
  425. switch (part_num) {
  426. case 0:
  427. mmc->capacity = mmc->capacity_user;
  428. break;
  429. case 1:
  430. case 2:
  431. mmc->capacity = mmc->capacity_boot;
  432. break;
  433. case 3:
  434. mmc->capacity = mmc->capacity_rpmb;
  435. break;
  436. case 4:
  437. case 5:
  438. case 6:
  439. case 7:
  440. mmc->capacity = mmc->capacity_gp[part_num - 4];
  441. break;
  442. default:
  443. return -1;
  444. }
  445. mmc->block_dev.lba = lldiv(mmc->capacity, mmc->read_bl_len);
  446. return 0;
  447. }
  448. int mmc_select_hwpart(int dev_num, int hwpart)
  449. {
  450. struct mmc *mmc = find_mmc_device(dev_num);
  451. int ret;
  452. if (!mmc)
  453. return -ENODEV;
  454. if (mmc->part_num == hwpart)
  455. return 0;
  456. if (mmc->part_config == MMCPART_NOAVAILABLE) {
  457. printf("Card doesn't support part_switch\n");
  458. return -EMEDIUMTYPE;
  459. }
  460. ret = mmc_switch_part(dev_num, hwpart);
  461. if (ret)
  462. return ret;
  463. mmc->part_num = hwpart;
  464. return 0;
  465. }
  466. int mmc_switch_part(int dev_num, unsigned int part_num)
  467. {
  468. struct mmc *mmc = find_mmc_device(dev_num);
  469. int ret;
  470. if (!mmc)
  471. return -1;
  472. ret = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF,
  473. (mmc->part_config & ~PART_ACCESS_MASK)
  474. | (part_num & PART_ACCESS_MASK));
  475. /*
  476. * Set the capacity if the switch succeeded or was intended
  477. * to return to representing the raw device.
  478. */
  479. if ((ret == 0) || ((ret == -ENODEV) && (part_num == 0)))
  480. ret = mmc_set_capacity(mmc, part_num);
  481. return ret;
  482. }
  483. int mmc_hwpart_config(struct mmc *mmc,
  484. const struct mmc_hwpart_conf *conf,
  485. enum mmc_hwpart_conf_mode mode)
  486. {
  487. u8 part_attrs = 0;
  488. u32 enh_size_mult;
  489. u32 enh_start_addr;
  490. u32 gp_size_mult[4];
  491. u32 max_enh_size_mult;
  492. u32 tot_enh_size_mult = 0;
  493. u8 wr_rel_set;
  494. int i, pidx, err;
  495. ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
  496. if (mode < MMC_HWPART_CONF_CHECK || mode > MMC_HWPART_CONF_COMPLETE)
  497. return -EINVAL;
  498. if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4_41)) {
  499. printf("eMMC >= 4.4 required for enhanced user data area\n");
  500. return -EMEDIUMTYPE;
  501. }
  502. if (!(mmc->part_support & PART_SUPPORT)) {
  503. printf("Card does not support partitioning\n");
  504. return -EMEDIUMTYPE;
  505. }
  506. if (!mmc->hc_wp_grp_size) {
  507. printf("Card does not define HC WP group size\n");
  508. return -EMEDIUMTYPE;
  509. }
  510. /* check partition alignment and total enhanced size */
  511. if (conf->user.enh_size) {
  512. if (conf->user.enh_size % mmc->hc_wp_grp_size ||
  513. conf->user.enh_start % mmc->hc_wp_grp_size) {
  514. printf("User data enhanced area not HC WP group "
  515. "size aligned\n");
  516. return -EINVAL;
  517. }
  518. part_attrs |= EXT_CSD_ENH_USR;
  519. enh_size_mult = conf->user.enh_size / mmc->hc_wp_grp_size;
  520. if (mmc->high_capacity) {
  521. enh_start_addr = conf->user.enh_start;
  522. } else {
  523. enh_start_addr = (conf->user.enh_start << 9);
  524. }
  525. } else {
  526. enh_size_mult = 0;
  527. enh_start_addr = 0;
  528. }
  529. tot_enh_size_mult += enh_size_mult;
  530. for (pidx = 0; pidx < 4; pidx++) {
  531. if (conf->gp_part[pidx].size % mmc->hc_wp_grp_size) {
  532. printf("GP%i partition not HC WP group size "
  533. "aligned\n", pidx+1);
  534. return -EINVAL;
  535. }
  536. gp_size_mult[pidx] = conf->gp_part[pidx].size / mmc->hc_wp_grp_size;
  537. if (conf->gp_part[pidx].size && conf->gp_part[pidx].enhanced) {
  538. part_attrs |= EXT_CSD_ENH_GP(pidx);
  539. tot_enh_size_mult += gp_size_mult[pidx];
  540. }
  541. }
  542. if (part_attrs && ! (mmc->part_support & ENHNCD_SUPPORT)) {
  543. printf("Card does not support enhanced attribute\n");
  544. return -EMEDIUMTYPE;
  545. }
  546. err = mmc_send_ext_csd(mmc, ext_csd);
  547. if (err)
  548. return err;
  549. max_enh_size_mult =
  550. (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+2] << 16) +
  551. (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+1] << 8) +
  552. ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT];
  553. if (tot_enh_size_mult > max_enh_size_mult) {
  554. printf("Total enhanced size exceeds maximum (%u > %u)\n",
  555. tot_enh_size_mult, max_enh_size_mult);
  556. return -EMEDIUMTYPE;
  557. }
  558. /* The default value of EXT_CSD_WR_REL_SET is device
  559. * dependent, the values can only be changed if the
  560. * EXT_CSD_HS_CTRL_REL bit is set. The values can be
  561. * changed only once and before partitioning is completed. */
  562. wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
  563. if (conf->user.wr_rel_change) {
  564. if (conf->user.wr_rel_set)
  565. wr_rel_set |= EXT_CSD_WR_DATA_REL_USR;
  566. else
  567. wr_rel_set &= ~EXT_CSD_WR_DATA_REL_USR;
  568. }
  569. for (pidx = 0; pidx < 4; pidx++) {
  570. if (conf->gp_part[pidx].wr_rel_change) {
  571. if (conf->gp_part[pidx].wr_rel_set)
  572. wr_rel_set |= EXT_CSD_WR_DATA_REL_GP(pidx);
  573. else
  574. wr_rel_set &= ~EXT_CSD_WR_DATA_REL_GP(pidx);
  575. }
  576. }
  577. if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET] &&
  578. !(ext_csd[EXT_CSD_WR_REL_PARAM] & EXT_CSD_HS_CTRL_REL)) {
  579. puts("Card does not support host controlled partition write "
  580. "reliability settings\n");
  581. return -EMEDIUMTYPE;
  582. }
  583. if (ext_csd[EXT_CSD_PARTITION_SETTING] &
  584. EXT_CSD_PARTITION_SETTING_COMPLETED) {
  585. printf("Card already partitioned\n");
  586. return -EPERM;
  587. }
  588. if (mode == MMC_HWPART_CONF_CHECK)
  589. return 0;
  590. /* Partitioning requires high-capacity size definitions */
  591. if (!(ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01)) {
  592. err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
  593. EXT_CSD_ERASE_GROUP_DEF, 1);
  594. if (err)
  595. return err;
  596. ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
  597. /* update erase group size to be high-capacity */
  598. mmc->erase_grp_size =
  599. ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
  600. }
  601. /* all OK, write the configuration */
  602. for (i = 0; i < 4; i++) {
  603. err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
  604. EXT_CSD_ENH_START_ADDR+i,
  605. (enh_start_addr >> (i*8)) & 0xFF);
  606. if (err)
  607. return err;
  608. }
  609. for (i = 0; i < 3; i++) {
  610. err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
  611. EXT_CSD_ENH_SIZE_MULT+i,
  612. (enh_size_mult >> (i*8)) & 0xFF);
  613. if (err)
  614. return err;
  615. }
  616. for (pidx = 0; pidx < 4; pidx++) {
  617. for (i = 0; i < 3; i++) {
  618. err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
  619. EXT_CSD_GP_SIZE_MULT+pidx*3+i,
  620. (gp_size_mult[pidx] >> (i*8)) & 0xFF);
  621. if (err)
  622. return err;
  623. }
  624. }
  625. err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
  626. EXT_CSD_PARTITIONS_ATTRIBUTE, part_attrs);
  627. if (err)
  628. return err;
  629. if (mode == MMC_HWPART_CONF_SET)
  630. return 0;
  631. /* The WR_REL_SET is a write-once register but shall be
  632. * written before setting PART_SETTING_COMPLETED. As it is
  633. * write-once we can only write it when completing the
  634. * partitioning. */
  635. if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET]) {
  636. err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
  637. EXT_CSD_WR_REL_SET, wr_rel_set);
  638. if (err)
  639. return err;
  640. }
  641. /* Setting PART_SETTING_COMPLETED confirms the partition
  642. * configuration but it only becomes effective after power
  643. * cycle, so we do not adjust the partition related settings
  644. * in the mmc struct. */
  645. err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
  646. EXT_CSD_PARTITION_SETTING,
  647. EXT_CSD_PARTITION_SETTING_COMPLETED);
  648. if (err)
  649. return err;
  650. return 0;
  651. }
  652. int mmc_getcd(struct mmc *mmc)
  653. {
  654. int cd;
  655. cd = board_mmc_getcd(mmc);
  656. if (cd < 0) {
  657. if (mmc->cfg->ops->getcd)
  658. cd = mmc->cfg->ops->getcd(mmc);
  659. else
  660. cd = 1;
  661. }
  662. return cd;
  663. }
  664. static int sd_switch(struct mmc *mmc, int mode, int group, u8 value, u8 *resp)
  665. {
  666. struct mmc_cmd cmd;
  667. struct mmc_data data;
  668. /* Switch the frequency */
  669. cmd.cmdidx = SD_CMD_SWITCH_FUNC;
  670. cmd.resp_type = MMC_RSP_R1;
  671. cmd.cmdarg = (mode << 31) | 0xffffff;
  672. cmd.cmdarg &= ~(0xf << (group * 4));
  673. cmd.cmdarg |= value << (group * 4);
  674. data.dest = (char *)resp;
  675. data.blocksize = 64;
  676. data.blocks = 1;
  677. data.flags = MMC_DATA_READ;
  678. return mmc_send_cmd(mmc, &cmd, &data);
  679. }
  680. static int sd_change_freq(struct mmc *mmc)
  681. {
  682. int err;
  683. struct mmc_cmd cmd;
  684. ALLOC_CACHE_ALIGN_BUFFER(uint, scr, 2);
  685. ALLOC_CACHE_ALIGN_BUFFER(uint, switch_status, 16);
  686. struct mmc_data data;
  687. int timeout;
  688. mmc->card_caps = 0;
  689. if (mmc_host_is_spi(mmc))
  690. return 0;
  691. /* Read the SCR to find out if this card supports higher speeds */
  692. cmd.cmdidx = MMC_CMD_APP_CMD;
  693. cmd.resp_type = MMC_RSP_R1;
  694. cmd.cmdarg = mmc->rca << 16;
  695. err = mmc_send_cmd(mmc, &cmd, NULL);
  696. if (err)
  697. return err;
  698. cmd.cmdidx = SD_CMD_APP_SEND_SCR;
  699. cmd.resp_type = MMC_RSP_R1;
  700. cmd.cmdarg = 0;
  701. timeout = 3;
  702. retry_scr:
  703. data.dest = (char *)scr;
  704. data.blocksize = 8;
  705. data.blocks = 1;
  706. data.flags = MMC_DATA_READ;
  707. err = mmc_send_cmd(mmc, &cmd, &data);
  708. if (err) {
  709. if (timeout--)
  710. goto retry_scr;
  711. return err;
  712. }
  713. mmc->scr[0] = __be32_to_cpu(scr[0]);
  714. mmc->scr[1] = __be32_to_cpu(scr[1]);
  715. switch ((mmc->scr[0] >> 24) & 0xf) {
  716. case 0:
  717. mmc->version = SD_VERSION_1_0;
  718. break;
  719. case 1:
  720. mmc->version = SD_VERSION_1_10;
  721. break;
  722. case 2:
  723. mmc->version = SD_VERSION_2;
  724. if ((mmc->scr[0] >> 15) & 0x1)
  725. mmc->version = SD_VERSION_3;
  726. break;
  727. default:
  728. mmc->version = SD_VERSION_1_0;
  729. break;
  730. }
  731. if (mmc->scr[0] & SD_DATA_4BIT)
  732. mmc->card_caps |= MMC_MODE_4BIT;
  733. /* Version 1.0 doesn't support switching */
  734. if (mmc->version == SD_VERSION_1_0)
  735. return 0;
  736. timeout = 4;
  737. while (timeout--) {
  738. err = sd_switch(mmc, SD_SWITCH_CHECK, 0, 1,
  739. (u8 *)switch_status);
  740. if (err)
  741. return err;
  742. /* The high-speed function is busy. Try again */
  743. if (!(__be32_to_cpu(switch_status[7]) & SD_HIGHSPEED_BUSY))
  744. break;
  745. }
  746. /* If high-speed isn't supported, we return */
  747. if (!(__be32_to_cpu(switch_status[3]) & SD_HIGHSPEED_SUPPORTED))
  748. return 0;
  749. /*
  750. * If the host doesn't support SD_HIGHSPEED, do not switch card to
  751. * HIGHSPEED mode even if the card support SD_HIGHSPPED.
  752. * This can avoid furthur problem when the card runs in different
  753. * mode between the host.
  754. */
  755. if (!((mmc->cfg->host_caps & MMC_MODE_HS_52MHz) &&
  756. (mmc->cfg->host_caps & MMC_MODE_HS)))
  757. return 0;
  758. err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, 1, (u8 *)switch_status);
  759. if (err)
  760. return err;
  761. if ((__be32_to_cpu(switch_status[4]) & 0x0f000000) == 0x01000000)
  762. mmc->card_caps |= MMC_MODE_HS;
  763. return 0;
  764. }
  765. /* frequency bases */
  766. /* divided by 10 to be nice to platforms without floating point */
  767. static const int fbase[] = {
  768. 10000,
  769. 100000,
  770. 1000000,
  771. 10000000,
  772. };
  773. /* Multiplier values for TRAN_SPEED. Multiplied by 10 to be nice
  774. * to platforms without floating point.
  775. */
  776. static const int multipliers[] = {
  777. 0, /* reserved */
  778. 10,
  779. 12,
  780. 13,
  781. 15,
  782. 20,
  783. 25,
  784. 30,
  785. 35,
  786. 40,
  787. 45,
  788. 50,
  789. 55,
  790. 60,
  791. 70,
  792. 80,
  793. };
  794. static void mmc_set_ios(struct mmc *mmc)
  795. {
  796. if (mmc->cfg->ops->set_ios)
  797. mmc->cfg->ops->set_ios(mmc);
  798. }
  799. void mmc_set_clock(struct mmc *mmc, uint clock)
  800. {
  801. if (clock > mmc->cfg->f_max)
  802. clock = mmc->cfg->f_max;
  803. if (clock < mmc->cfg->f_min)
  804. clock = mmc->cfg->f_min;
  805. mmc->clock = clock;
  806. mmc_set_ios(mmc);
  807. }
  808. static void mmc_set_bus_width(struct mmc *mmc, uint width)
  809. {
  810. mmc->bus_width = width;
  811. mmc_set_ios(mmc);
  812. }
  813. static int mmc_startup(struct mmc *mmc)
  814. {
  815. int err, i;
  816. uint mult, freq;
  817. u64 cmult, csize, capacity;
  818. struct mmc_cmd cmd;
  819. ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
  820. ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
  821. int timeout = 1000;
  822. bool has_parts = false;
  823. bool part_completed;
  824. #ifdef CONFIG_MMC_SPI_CRC_ON
  825. if (mmc_host_is_spi(mmc)) { /* enable CRC check for spi */
  826. cmd.cmdidx = MMC_CMD_SPI_CRC_ON_OFF;
  827. cmd.resp_type = MMC_RSP_R1;
  828. cmd.cmdarg = 1;
  829. err = mmc_send_cmd(mmc, &cmd, NULL);
  830. if (err)
  831. return err;
  832. }
  833. #endif
  834. /* Put the Card in Identify Mode */
  835. cmd.cmdidx = mmc_host_is_spi(mmc) ? MMC_CMD_SEND_CID :
  836. MMC_CMD_ALL_SEND_CID; /* cmd not supported in spi */
  837. cmd.resp_type = MMC_RSP_R2;
  838. cmd.cmdarg = 0;
  839. err = mmc_send_cmd(mmc, &cmd, NULL);
  840. if (err)
  841. return err;
  842. memcpy(mmc->cid, cmd.response, 16);
  843. /*
  844. * For MMC cards, set the Relative Address.
  845. * For SD cards, get the Relatvie Address.
  846. * This also puts the cards into Standby State
  847. */
  848. if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
  849. cmd.cmdidx = SD_CMD_SEND_RELATIVE_ADDR;
  850. cmd.cmdarg = mmc->rca << 16;
  851. cmd.resp_type = MMC_RSP_R6;
  852. err = mmc_send_cmd(mmc, &cmd, NULL);
  853. if (err)
  854. return err;
  855. if (IS_SD(mmc))
  856. mmc->rca = (cmd.response[0] >> 16) & 0xffff;
  857. }
  858. /* Get the Card-Specific Data */
  859. cmd.cmdidx = MMC_CMD_SEND_CSD;
  860. cmd.resp_type = MMC_RSP_R2;
  861. cmd.cmdarg = mmc->rca << 16;
  862. err = mmc_send_cmd(mmc, &cmd, NULL);
  863. /* Waiting for the ready status */
  864. mmc_send_status(mmc, timeout);
  865. if (err)
  866. return err;
  867. mmc->csd[0] = cmd.response[0];
  868. mmc->csd[1] = cmd.response[1];
  869. mmc->csd[2] = cmd.response[2];
  870. mmc->csd[3] = cmd.response[3];
  871. if (mmc->version == MMC_VERSION_UNKNOWN) {
  872. int version = (cmd.response[0] >> 26) & 0xf;
  873. switch (version) {
  874. case 0:
  875. mmc->version = MMC_VERSION_1_2;
  876. break;
  877. case 1:
  878. mmc->version = MMC_VERSION_1_4;
  879. break;
  880. case 2:
  881. mmc->version = MMC_VERSION_2_2;
  882. break;
  883. case 3:
  884. mmc->version = MMC_VERSION_3;
  885. break;
  886. case 4:
  887. mmc->version = MMC_VERSION_4;
  888. break;
  889. default:
  890. mmc->version = MMC_VERSION_1_2;
  891. break;
  892. }
  893. }
  894. /* divide frequency by 10, since the mults are 10x bigger */
  895. freq = fbase[(cmd.response[0] & 0x7)];
  896. mult = multipliers[((cmd.response[0] >> 3) & 0xf)];
  897. mmc->tran_speed = freq * mult;
  898. mmc->dsr_imp = ((cmd.response[1] >> 12) & 0x1);
  899. mmc->read_bl_len = 1 << ((cmd.response[1] >> 16) & 0xf);
  900. if (IS_SD(mmc))
  901. mmc->write_bl_len = mmc->read_bl_len;
  902. else
  903. mmc->write_bl_len = 1 << ((cmd.response[3] >> 22) & 0xf);
  904. if (mmc->high_capacity) {
  905. csize = (mmc->csd[1] & 0x3f) << 16
  906. | (mmc->csd[2] & 0xffff0000) >> 16;
  907. cmult = 8;
  908. } else {
  909. csize = (mmc->csd[1] & 0x3ff) << 2
  910. | (mmc->csd[2] & 0xc0000000) >> 30;
  911. cmult = (mmc->csd[2] & 0x00038000) >> 15;
  912. }
  913. mmc->capacity_user = (csize + 1) << (cmult + 2);
  914. mmc->capacity_user *= mmc->read_bl_len;
  915. mmc->capacity_boot = 0;
  916. mmc->capacity_rpmb = 0;
  917. for (i = 0; i < 4; i++)
  918. mmc->capacity_gp[i] = 0;
  919. if (mmc->read_bl_len > MMC_MAX_BLOCK_LEN)
  920. mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
  921. if (mmc->write_bl_len > MMC_MAX_BLOCK_LEN)
  922. mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
  923. if ((mmc->dsr_imp) && (0xffffffff != mmc->dsr)) {
  924. cmd.cmdidx = MMC_CMD_SET_DSR;
  925. cmd.cmdarg = (mmc->dsr & 0xffff) << 16;
  926. cmd.resp_type = MMC_RSP_NONE;
  927. if (mmc_send_cmd(mmc, &cmd, NULL))
  928. printf("MMC: SET_DSR failed\n");
  929. }
  930. /* Select the card, and put it into Transfer Mode */
  931. if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
  932. cmd.cmdidx = MMC_CMD_SELECT_CARD;
  933. cmd.resp_type = MMC_RSP_R1;
  934. cmd.cmdarg = mmc->rca << 16;
  935. err = mmc_send_cmd(mmc, &cmd, NULL);
  936. if (err)
  937. return err;
  938. }
  939. /*
  940. * For SD, its erase group is always one sector
  941. */
  942. mmc->erase_grp_size = 1;
  943. mmc->part_config = MMCPART_NOAVAILABLE;
  944. if (!IS_SD(mmc) && (mmc->version >= MMC_VERSION_4)) {
  945. /* check ext_csd version and capacity */
  946. err = mmc_send_ext_csd(mmc, ext_csd);
  947. if (err)
  948. return err;
  949. if (ext_csd[EXT_CSD_REV] >= 2) {
  950. /*
  951. * According to the JEDEC Standard, the value of
  952. * ext_csd's capacity is valid if the value is more
  953. * than 2GB
  954. */
  955. capacity = ext_csd[EXT_CSD_SEC_CNT] << 0
  956. | ext_csd[EXT_CSD_SEC_CNT + 1] << 8
  957. | ext_csd[EXT_CSD_SEC_CNT + 2] << 16
  958. | ext_csd[EXT_CSD_SEC_CNT + 3] << 24;
  959. capacity *= MMC_MAX_BLOCK_LEN;
  960. if ((capacity >> 20) > 2 * 1024)
  961. mmc->capacity_user = capacity;
  962. }
  963. switch (ext_csd[EXT_CSD_REV]) {
  964. case 1:
  965. mmc->version = MMC_VERSION_4_1;
  966. break;
  967. case 2:
  968. mmc->version = MMC_VERSION_4_2;
  969. break;
  970. case 3:
  971. mmc->version = MMC_VERSION_4_3;
  972. break;
  973. case 5:
  974. mmc->version = MMC_VERSION_4_41;
  975. break;
  976. case 6:
  977. mmc->version = MMC_VERSION_4_5;
  978. break;
  979. case 7:
  980. mmc->version = MMC_VERSION_5_0;
  981. break;
  982. }
  983. /* The partition data may be non-zero but it is only
  984. * effective if PARTITION_SETTING_COMPLETED is set in
  985. * EXT_CSD, so ignore any data if this bit is not set,
  986. * except for enabling the high-capacity group size
  987. * definition (see below). */
  988. part_completed = !!(ext_csd[EXT_CSD_PARTITION_SETTING] &
  989. EXT_CSD_PARTITION_SETTING_COMPLETED);
  990. /* store the partition info of emmc */
  991. mmc->part_support = ext_csd[EXT_CSD_PARTITIONING_SUPPORT];
  992. if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) ||
  993. ext_csd[EXT_CSD_BOOT_MULT])
  994. mmc->part_config = ext_csd[EXT_CSD_PART_CONF];
  995. if (part_completed &&
  996. (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & ENHNCD_SUPPORT))
  997. mmc->part_attr = ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE];
  998. mmc->capacity_boot = ext_csd[EXT_CSD_BOOT_MULT] << 17;
  999. mmc->capacity_rpmb = ext_csd[EXT_CSD_RPMB_MULT] << 17;
  1000. for (i = 0; i < 4; i++) {
  1001. int idx = EXT_CSD_GP_SIZE_MULT + i * 3;
  1002. uint mult = (ext_csd[idx + 2] << 16) +
  1003. (ext_csd[idx + 1] << 8) + ext_csd[idx];
  1004. if (mult)
  1005. has_parts = true;
  1006. if (!part_completed)
  1007. continue;
  1008. mmc->capacity_gp[i] = mult;
  1009. mmc->capacity_gp[i] *=
  1010. ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
  1011. mmc->capacity_gp[i] *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
  1012. mmc->capacity_gp[i] <<= 19;
  1013. }
  1014. if (part_completed) {
  1015. mmc->enh_user_size =
  1016. (ext_csd[EXT_CSD_ENH_SIZE_MULT+2] << 16) +
  1017. (ext_csd[EXT_CSD_ENH_SIZE_MULT+1] << 8) +
  1018. ext_csd[EXT_CSD_ENH_SIZE_MULT];
  1019. mmc->enh_user_size *= ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
  1020. mmc->enh_user_size *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
  1021. mmc->enh_user_size <<= 19;
  1022. mmc->enh_user_start =
  1023. (ext_csd[EXT_CSD_ENH_START_ADDR+3] << 24) +
  1024. (ext_csd[EXT_CSD_ENH_START_ADDR+2] << 16) +
  1025. (ext_csd[EXT_CSD_ENH_START_ADDR+1] << 8) +
  1026. ext_csd[EXT_CSD_ENH_START_ADDR];
  1027. if (mmc->high_capacity)
  1028. mmc->enh_user_start <<= 9;
  1029. }
  1030. /*
  1031. * Host needs to enable ERASE_GRP_DEF bit if device is
  1032. * partitioned. This bit will be lost every time after a reset
  1033. * or power off. This will affect erase size.
  1034. */
  1035. if (part_completed)
  1036. has_parts = true;
  1037. if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) &&
  1038. (ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE] & PART_ENH_ATTRIB))
  1039. has_parts = true;
  1040. if (has_parts) {
  1041. err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
  1042. EXT_CSD_ERASE_GROUP_DEF, 1);
  1043. if (err)
  1044. return err;
  1045. else
  1046. ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
  1047. }
  1048. if (ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01) {
  1049. /* Read out group size from ext_csd */
  1050. mmc->erase_grp_size =
  1051. ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
  1052. /*
  1053. * if high capacity and partition setting completed
  1054. * SEC_COUNT is valid even if it is smaller than 2 GiB
  1055. * JEDEC Standard JESD84-B45, 6.2.4
  1056. */
  1057. if (mmc->high_capacity && part_completed) {
  1058. capacity = (ext_csd[EXT_CSD_SEC_CNT]) |
  1059. (ext_csd[EXT_CSD_SEC_CNT + 1] << 8) |
  1060. (ext_csd[EXT_CSD_SEC_CNT + 2] << 16) |
  1061. (ext_csd[EXT_CSD_SEC_CNT + 3] << 24);
  1062. capacity *= MMC_MAX_BLOCK_LEN;
  1063. mmc->capacity_user = capacity;
  1064. }
  1065. } else {
  1066. /* Calculate the group size from the csd value. */
  1067. int erase_gsz, erase_gmul;
  1068. erase_gsz = (mmc->csd[2] & 0x00007c00) >> 10;
  1069. erase_gmul = (mmc->csd[2] & 0x000003e0) >> 5;
  1070. mmc->erase_grp_size = (erase_gsz + 1)
  1071. * (erase_gmul + 1);
  1072. }
  1073. mmc->hc_wp_grp_size = 1024
  1074. * ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
  1075. * ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
  1076. mmc->wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
  1077. }
  1078. err = mmc_set_capacity(mmc, mmc->part_num);
  1079. if (err)
  1080. return err;
  1081. if (IS_SD(mmc))
  1082. err = sd_change_freq(mmc);
  1083. else
  1084. err = mmc_change_freq(mmc);
  1085. if (err)
  1086. return err;
  1087. /* Restrict card's capabilities by what the host can do */
  1088. mmc->card_caps &= mmc->cfg->host_caps;
  1089. if (IS_SD(mmc)) {
  1090. if (mmc->card_caps & MMC_MODE_4BIT) {
  1091. cmd.cmdidx = MMC_CMD_APP_CMD;
  1092. cmd.resp_type = MMC_RSP_R1;
  1093. cmd.cmdarg = mmc->rca << 16;
  1094. err = mmc_send_cmd(mmc, &cmd, NULL);
  1095. if (err)
  1096. return err;
  1097. cmd.cmdidx = SD_CMD_APP_SET_BUS_WIDTH;
  1098. cmd.resp_type = MMC_RSP_R1;
  1099. cmd.cmdarg = 2;
  1100. err = mmc_send_cmd(mmc, &cmd, NULL);
  1101. if (err)
  1102. return err;
  1103. mmc_set_bus_width(mmc, 4);
  1104. }
  1105. if (mmc->card_caps & MMC_MODE_HS)
  1106. mmc->tran_speed = 50000000;
  1107. else
  1108. mmc->tran_speed = 25000000;
  1109. } else if (mmc->version >= MMC_VERSION_4) {
  1110. /* Only version 4 of MMC supports wider bus widths */
  1111. int idx;
  1112. /* An array of possible bus widths in order of preference */
  1113. static unsigned ext_csd_bits[] = {
  1114. EXT_CSD_DDR_BUS_WIDTH_8,
  1115. EXT_CSD_DDR_BUS_WIDTH_4,
  1116. EXT_CSD_BUS_WIDTH_8,
  1117. EXT_CSD_BUS_WIDTH_4,
  1118. EXT_CSD_BUS_WIDTH_1,
  1119. };
  1120. /* An array to map CSD bus widths to host cap bits */
  1121. static unsigned ext_to_hostcaps[] = {
  1122. [EXT_CSD_DDR_BUS_WIDTH_4] =
  1123. MMC_MODE_DDR_52MHz | MMC_MODE_4BIT,
  1124. [EXT_CSD_DDR_BUS_WIDTH_8] =
  1125. MMC_MODE_DDR_52MHz | MMC_MODE_8BIT,
  1126. [EXT_CSD_BUS_WIDTH_4] = MMC_MODE_4BIT,
  1127. [EXT_CSD_BUS_WIDTH_8] = MMC_MODE_8BIT,
  1128. };
  1129. /* An array to map chosen bus width to an integer */
  1130. static unsigned widths[] = {
  1131. 8, 4, 8, 4, 1,
  1132. };
  1133. for (idx=0; idx < ARRAY_SIZE(ext_csd_bits); idx++) {
  1134. unsigned int extw = ext_csd_bits[idx];
  1135. unsigned int caps = ext_to_hostcaps[extw];
  1136. /*
  1137. * If the bus width is still not changed,
  1138. * don't try to set the default again.
  1139. * Otherwise, recover from switch attempts
  1140. * by switching to 1-bit bus width.
  1141. */
  1142. if (extw == EXT_CSD_BUS_WIDTH_1 &&
  1143. mmc->bus_width == 1) {
  1144. err = 0;
  1145. break;
  1146. }
  1147. /*
  1148. * Check to make sure the card and controller support
  1149. * these capabilities
  1150. */
  1151. if ((mmc->card_caps & caps) != caps)
  1152. continue;
  1153. err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
  1154. EXT_CSD_BUS_WIDTH, extw);
  1155. if (err)
  1156. continue;
  1157. mmc->ddr_mode = (caps & MMC_MODE_DDR_52MHz) ? 1 : 0;
  1158. mmc_set_bus_width(mmc, widths[idx]);
  1159. err = mmc_send_ext_csd(mmc, test_csd);
  1160. if (err)
  1161. continue;
  1162. /* Only compare read only fields */
  1163. if (ext_csd[EXT_CSD_PARTITIONING_SUPPORT]
  1164. == test_csd[EXT_CSD_PARTITIONING_SUPPORT] &&
  1165. ext_csd[EXT_CSD_HC_WP_GRP_SIZE]
  1166. == test_csd[EXT_CSD_HC_WP_GRP_SIZE] &&
  1167. ext_csd[EXT_CSD_REV]
  1168. == test_csd[EXT_CSD_REV] &&
  1169. ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
  1170. == test_csd[EXT_CSD_HC_ERASE_GRP_SIZE] &&
  1171. memcmp(&ext_csd[EXT_CSD_SEC_CNT],
  1172. &test_csd[EXT_CSD_SEC_CNT], 4) == 0)
  1173. break;
  1174. else
  1175. err = SWITCH_ERR;
  1176. }
  1177. if (err)
  1178. return err;
  1179. if (mmc->card_caps & MMC_MODE_HS) {
  1180. if (mmc->card_caps & MMC_MODE_HS_52MHz)
  1181. mmc->tran_speed = 52000000;
  1182. else
  1183. mmc->tran_speed = 26000000;
  1184. }
  1185. }
  1186. mmc_set_clock(mmc, mmc->tran_speed);
  1187. /* Fix the block length for DDR mode */
  1188. if (mmc->ddr_mode) {
  1189. mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
  1190. mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
  1191. }
  1192. /* fill in device description */
  1193. mmc->block_dev.lun = 0;
  1194. mmc->block_dev.type = 0;
  1195. mmc->block_dev.blksz = mmc->read_bl_len;
  1196. mmc->block_dev.log2blksz = LOG2(mmc->block_dev.blksz);
  1197. mmc->block_dev.lba = lldiv(mmc->capacity, mmc->read_bl_len);
  1198. #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
  1199. sprintf(mmc->block_dev.vendor, "Man %06x Snr %04x%04x",
  1200. mmc->cid[0] >> 24, (mmc->cid[2] & 0xffff),
  1201. (mmc->cid[3] >> 16) & 0xffff);
  1202. sprintf(mmc->block_dev.product, "%c%c%c%c%c%c", mmc->cid[0] & 0xff,
  1203. (mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff,
  1204. (mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff,
  1205. (mmc->cid[2] >> 24) & 0xff);
  1206. sprintf(mmc->block_dev.revision, "%d.%d", (mmc->cid[2] >> 20) & 0xf,
  1207. (mmc->cid[2] >> 16) & 0xf);
  1208. #else
  1209. mmc->block_dev.vendor[0] = 0;
  1210. mmc->block_dev.product[0] = 0;
  1211. mmc->block_dev.revision[0] = 0;
  1212. #endif
  1213. #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBDISK_SUPPORT)
  1214. init_part(&mmc->block_dev);
  1215. #endif
  1216. return 0;
  1217. }
  1218. static int mmc_send_if_cond(struct mmc *mmc)
  1219. {
  1220. struct mmc_cmd cmd;
  1221. int err;
  1222. cmd.cmdidx = SD_CMD_SEND_IF_COND;
  1223. /* We set the bit if the host supports voltages between 2.7 and 3.6 V */
  1224. cmd.cmdarg = ((mmc->cfg->voltages & 0xff8000) != 0) << 8 | 0xaa;
  1225. cmd.resp_type = MMC_RSP_R7;
  1226. err = mmc_send_cmd(mmc, &cmd, NULL);
  1227. if (err)
  1228. return err;
  1229. if ((cmd.response[0] & 0xff) != 0xaa)
  1230. return UNUSABLE_ERR;
  1231. else
  1232. mmc->version = SD_VERSION_2;
  1233. return 0;
  1234. }
  1235. /* not used any more */
  1236. int __deprecated mmc_register(struct mmc *mmc)
  1237. {
  1238. #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
  1239. printf("%s is deprecated! use mmc_create() instead.\n", __func__);
  1240. #endif
  1241. return -1;
  1242. }
  1243. struct mmc *mmc_create(const struct mmc_config *cfg, void *priv)
  1244. {
  1245. struct mmc *mmc;
  1246. /* quick validation */
  1247. if (cfg == NULL || cfg->ops == NULL || cfg->ops->send_cmd == NULL ||
  1248. cfg->f_min == 0 || cfg->f_max == 0 || cfg->b_max == 0)
  1249. return NULL;
  1250. mmc = calloc(1, sizeof(*mmc));
  1251. if (mmc == NULL)
  1252. return NULL;
  1253. mmc->cfg = cfg;
  1254. mmc->priv = priv;
  1255. /* the following chunk was mmc_register() */
  1256. /* Setup dsr related values */
  1257. mmc->dsr_imp = 0;
  1258. mmc->dsr = 0xffffffff;
  1259. /* Setup the universal parts of the block interface just once */
  1260. mmc->block_dev.if_type = IF_TYPE_MMC;
  1261. mmc->block_dev.dev = cur_dev_num++;
  1262. mmc->block_dev.removable = 1;
  1263. mmc->block_dev.block_read = mmc_bread;
  1264. mmc->block_dev.block_write = mmc_bwrite;
  1265. mmc->block_dev.block_erase = mmc_berase;
  1266. /* setup initial part type */
  1267. mmc->block_dev.part_type = mmc->cfg->part_type;
  1268. INIT_LIST_HEAD(&mmc->link);
  1269. list_add_tail(&mmc->link, &mmc_devices);
  1270. return mmc;
  1271. }
  1272. void mmc_destroy(struct mmc *mmc)
  1273. {
  1274. /* only freeing memory for now */
  1275. free(mmc);
  1276. }
  1277. #ifdef CONFIG_PARTITIONS
  1278. block_dev_desc_t *mmc_get_dev(int dev)
  1279. {
  1280. struct mmc *mmc = find_mmc_device(dev);
  1281. if (!mmc || mmc_init(mmc))
  1282. return NULL;
  1283. return &mmc->block_dev;
  1284. }
  1285. #endif
  1286. /* board-specific MMC power initializations. */
  1287. __weak void board_mmc_power_init(void)
  1288. {
  1289. }
  1290. int mmc_start_init(struct mmc *mmc)
  1291. {
  1292. int err;
  1293. /* we pretend there's no card when init is NULL */
  1294. if (mmc_getcd(mmc) == 0 || mmc->cfg->ops->init == NULL) {
  1295. mmc->has_init = 0;
  1296. #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
  1297. printf("MMC: no card present\n");
  1298. #endif
  1299. return NO_CARD_ERR;
  1300. }
  1301. if (mmc->has_init)
  1302. return 0;
  1303. board_mmc_power_init();
  1304. /* made sure it's not NULL earlier */
  1305. err = mmc->cfg->ops->init(mmc);
  1306. if (err)
  1307. return err;
  1308. mmc->ddr_mode = 0;
  1309. mmc_set_bus_width(mmc, 1);
  1310. mmc_set_clock(mmc, 1);
  1311. /* Reset the Card */
  1312. err = mmc_go_idle(mmc);
  1313. if (err)
  1314. return err;
  1315. /* The internal partition reset to user partition(0) at every CMD0*/
  1316. mmc->part_num = 0;
  1317. /* Test for SD version 2 */
  1318. err = mmc_send_if_cond(mmc);
  1319. /* Now try to get the SD card's operating condition */
  1320. err = sd_send_op_cond(mmc);
  1321. /* If the command timed out, we check for an MMC card */
  1322. if (err == TIMEOUT) {
  1323. err = mmc_send_op_cond(mmc);
  1324. if (err && err != IN_PROGRESS) {
  1325. #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
  1326. printf("Card did not respond to voltage select!\n");
  1327. #endif
  1328. return UNUSABLE_ERR;
  1329. }
  1330. }
  1331. if (err == IN_PROGRESS)
  1332. mmc->init_in_progress = 1;
  1333. return err;
  1334. }
  1335. static int mmc_complete_init(struct mmc *mmc)
  1336. {
  1337. int err = 0;
  1338. if (mmc->op_cond_pending)
  1339. err = mmc_complete_op_cond(mmc);
  1340. if (!err)
  1341. err = mmc_startup(mmc);
  1342. if (err)
  1343. mmc->has_init = 0;
  1344. else
  1345. mmc->has_init = 1;
  1346. mmc->init_in_progress = 0;
  1347. return err;
  1348. }
  1349. int mmc_init(struct mmc *mmc)
  1350. {
  1351. int err = IN_PROGRESS;
  1352. unsigned start;
  1353. if (mmc->has_init)
  1354. return 0;
  1355. start = get_timer(0);
  1356. if (!mmc->init_in_progress)
  1357. err = mmc_start_init(mmc);
  1358. if (!err || err == IN_PROGRESS)
  1359. err = mmc_complete_init(mmc);
  1360. debug("%s: %d, time %lu\n", __func__, err, get_timer(start));
  1361. return err;
  1362. }
  1363. int mmc_set_dsr(struct mmc *mmc, u16 val)
  1364. {
  1365. mmc->dsr = val;
  1366. return 0;
  1367. }
  1368. /* CPU-specific MMC initializations */
  1369. __weak int cpu_mmc_init(bd_t *bis)
  1370. {
  1371. return -1;
  1372. }
  1373. /* board-specific MMC initializations. */
  1374. __weak int board_mmc_init(bd_t *bis)
  1375. {
  1376. return -1;
  1377. }
  1378. #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
  1379. void print_mmc_devices(char separator)
  1380. {
  1381. struct mmc *m;
  1382. struct list_head *entry;
  1383. char *mmc_type;
  1384. list_for_each(entry, &mmc_devices) {
  1385. m = list_entry(entry, struct mmc, link);
  1386. if (m->has_init)
  1387. mmc_type = IS_SD(m) ? "SD" : "eMMC";
  1388. else
  1389. mmc_type = NULL;
  1390. printf("%s: %d", m->cfg->name, m->block_dev.dev);
  1391. if (mmc_type)
  1392. printf(" (%s)", mmc_type);
  1393. if (entry->next != &mmc_devices) {
  1394. printf("%c", separator);
  1395. if (separator != '\n')
  1396. puts (" ");
  1397. }
  1398. }
  1399. printf("\n");
  1400. }
  1401. #else
  1402. void print_mmc_devices(char separator) { }
  1403. #endif
  1404. int get_mmc_num(void)
  1405. {
  1406. return cur_dev_num;
  1407. }
  1408. void mmc_set_preinit(struct mmc *mmc, int preinit)
  1409. {
  1410. mmc->preinit = preinit;
  1411. }
  1412. static void do_preinit(void)
  1413. {
  1414. struct mmc *m;
  1415. struct list_head *entry;
  1416. list_for_each(entry, &mmc_devices) {
  1417. m = list_entry(entry, struct mmc, link);
  1418. if (m->preinit)
  1419. mmc_start_init(m);
  1420. }
  1421. }
  1422. int mmc_initialize(bd_t *bis)
  1423. {
  1424. INIT_LIST_HEAD (&mmc_devices);
  1425. cur_dev_num = 0;
  1426. if (board_mmc_init(bis) < 0)
  1427. cpu_mmc_init(bis);
  1428. #ifndef CONFIG_SPL_BUILD
  1429. print_mmc_devices(',');
  1430. #endif
  1431. do_preinit();
  1432. return 0;
  1433. }
  1434. #ifdef CONFIG_SUPPORT_EMMC_BOOT
  1435. /*
  1436. * This function changes the size of boot partition and the size of rpmb
  1437. * partition present on EMMC devices.
  1438. *
  1439. * Input Parameters:
  1440. * struct *mmc: pointer for the mmc device strcuture
  1441. * bootsize: size of boot partition
  1442. * rpmbsize: size of rpmb partition
  1443. *
  1444. * Returns 0 on success.
  1445. */
  1446. int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize,
  1447. unsigned long rpmbsize)
  1448. {
  1449. int err;
  1450. struct mmc_cmd cmd;
  1451. /* Only use this command for raw EMMC moviNAND. Enter backdoor mode */
  1452. cmd.cmdidx = MMC_CMD_RES_MAN;
  1453. cmd.resp_type = MMC_RSP_R1b;
  1454. cmd.cmdarg = MMC_CMD62_ARG1;
  1455. err = mmc_send_cmd(mmc, &cmd, NULL);
  1456. if (err) {
  1457. debug("mmc_boot_partition_size_change: Error1 = %d\n", err);
  1458. return err;
  1459. }
  1460. /* Boot partition changing mode */
  1461. cmd.cmdidx = MMC_CMD_RES_MAN;
  1462. cmd.resp_type = MMC_RSP_R1b;
  1463. cmd.cmdarg = MMC_CMD62_ARG2;
  1464. err = mmc_send_cmd(mmc, &cmd, NULL);
  1465. if (err) {
  1466. debug("mmc_boot_partition_size_change: Error2 = %d\n", err);
  1467. return err;
  1468. }
  1469. /* boot partition size is multiple of 128KB */
  1470. bootsize = (bootsize * 1024) / 128;
  1471. /* Arg: boot partition size */
  1472. cmd.cmdidx = MMC_CMD_RES_MAN;
  1473. cmd.resp_type = MMC_RSP_R1b;
  1474. cmd.cmdarg = bootsize;
  1475. err = mmc_send_cmd(mmc, &cmd, NULL);
  1476. if (err) {
  1477. debug("mmc_boot_partition_size_change: Error3 = %d\n", err);
  1478. return err;
  1479. }
  1480. /* RPMB partition size is multiple of 128KB */
  1481. rpmbsize = (rpmbsize * 1024) / 128;
  1482. /* Arg: RPMB partition size */
  1483. cmd.cmdidx = MMC_CMD_RES_MAN;
  1484. cmd.resp_type = MMC_RSP_R1b;
  1485. cmd.cmdarg = rpmbsize;
  1486. err = mmc_send_cmd(mmc, &cmd, NULL);
  1487. if (err) {
  1488. debug("mmc_boot_partition_size_change: Error4 = %d\n", err);
  1489. return err;
  1490. }
  1491. return 0;
  1492. }
  1493. /*
  1494. * Modify EXT_CSD[177] which is BOOT_BUS_WIDTH
  1495. * based on the passed in values for BOOT_BUS_WIDTH, RESET_BOOT_BUS_WIDTH
  1496. * and BOOT_MODE.
  1497. *
  1498. * Returns 0 on success.
  1499. */
  1500. int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode)
  1501. {
  1502. int err;
  1503. err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BOOT_BUS_WIDTH,
  1504. EXT_CSD_BOOT_BUS_WIDTH_MODE(mode) |
  1505. EXT_CSD_BOOT_BUS_WIDTH_RESET(reset) |
  1506. EXT_CSD_BOOT_BUS_WIDTH_WIDTH(width));
  1507. if (err)
  1508. return err;
  1509. return 0;
  1510. }
  1511. /*
  1512. * Modify EXT_CSD[179] which is PARTITION_CONFIG (formerly BOOT_CONFIG)
  1513. * based on the passed in values for BOOT_ACK, BOOT_PARTITION_ENABLE and
  1514. * PARTITION_ACCESS.
  1515. *
  1516. * Returns 0 on success.
  1517. */
  1518. int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access)
  1519. {
  1520. int err;
  1521. err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF,
  1522. EXT_CSD_BOOT_ACK(ack) |
  1523. EXT_CSD_BOOT_PART_NUM(part_num) |
  1524. EXT_CSD_PARTITION_ACCESS(access));
  1525. if (err)
  1526. return err;
  1527. return 0;
  1528. }
  1529. /*
  1530. * Modify EXT_CSD[162] which is RST_n_FUNCTION based on the given value
  1531. * for enable. Note that this is a write-once field for non-zero values.
  1532. *
  1533. * Returns 0 on success.
  1534. */
  1535. int mmc_set_rst_n_function(struct mmc *mmc, u8 enable)
  1536. {
  1537. return mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_RST_N_FUNCTION,
  1538. enable);
  1539. }
  1540. #endif