i2c-uniphier-f.c 8.6 KB

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  1. /*
  2. * Copyright (C) 2014 Panasonic Corporation
  3. * Copyright (C) 2015 Socionext Inc.
  4. * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  5. *
  6. * SPDX-License-Identifier: GPL-2.0+
  7. */
  8. #include <common.h>
  9. #include <linux/types.h>
  10. #include <asm/io.h>
  11. #include <asm/errno.h>
  12. #include <dm/device.h>
  13. #include <dm/root.h>
  14. #include <i2c.h>
  15. #include <fdtdec.h>
  16. #include <mapmem.h>
  17. DECLARE_GLOBAL_DATA_PTR;
  18. struct uniphier_fi2c_regs {
  19. u32 cr; /* control register */
  20. #define I2C_CR_MST (1 << 3) /* master mode */
  21. #define I2C_CR_STA (1 << 2) /* start condition */
  22. #define I2C_CR_STO (1 << 1) /* stop condition */
  23. #define I2C_CR_NACK (1 << 0) /* not ACK */
  24. u32 dttx; /* send FIFO (write-only) */
  25. #define dtrx dttx /* receive FIFO (read-only) */
  26. #define I2C_DTTX_CMD (1 << 8) /* send command (slave addr) */
  27. #define I2C_DTTX_RD (1 << 0) /* read */
  28. u32 __reserved; /* no register at offset 0x08 */
  29. u32 slad; /* slave address */
  30. u32 cyc; /* clock cycle control */
  31. u32 lctl; /* clock low period control */
  32. u32 ssut; /* restart/stop setup time control */
  33. u32 dsut; /* data setup time control */
  34. u32 intr; /* interrupt status */
  35. u32 ie; /* interrupt enable */
  36. u32 ic; /* interrupt clear */
  37. #define I2C_INT_TE (1 << 9) /* TX FIFO empty */
  38. #define I2C_INT_RB (1 << 4) /* received specified bytes */
  39. #define I2C_INT_NA (1 << 2) /* no answer */
  40. #define I2C_INT_AL (1 << 1) /* arbitration lost */
  41. u32 sr; /* status register */
  42. #define I2C_SR_DB (1 << 12) /* device busy */
  43. #define I2C_SR_BB (1 << 8) /* bus busy */
  44. #define I2C_SR_RFF (1 << 3) /* Rx FIFO full */
  45. #define I2C_SR_RNE (1 << 2) /* Rx FIFO not empty */
  46. #define I2C_SR_TNF (1 << 1) /* Tx FIFO not full */
  47. #define I2C_SR_TFE (1 << 0) /* Tx FIFO empty */
  48. u32 __reserved2; /* no register at offset 0x30 */
  49. u32 rst; /* reset control */
  50. #define I2C_RST_TBRST (1 << 2) /* clear Tx FIFO */
  51. #define I2C_RST_RBRST (1 << 1) /* clear Rx FIFO */
  52. #define I2C_RST_RST (1 << 0) /* forcible bus reset */
  53. u32 bm; /* bus monitor */
  54. u32 noise; /* noise filter control */
  55. u32 tbc; /* Tx byte count setting */
  56. u32 rbc; /* Rx byte count setting */
  57. u32 tbcm; /* Tx byte count monitor */
  58. u32 rbcm; /* Rx byte count monitor */
  59. u32 brst; /* bus reset */
  60. #define I2C_BRST_FOEN (1 << 1) /* normal operation */
  61. #define I2C_BRST_RSCLO (1 << 0) /* release SCL low fixing */
  62. };
  63. #define FIOCLK 50000000
  64. struct uniphier_fi2c_dev {
  65. struct uniphier_fi2c_regs __iomem *regs; /* register base */
  66. unsigned long fioclk; /* internal operation clock */
  67. unsigned long timeout; /* time out (us) */
  68. };
  69. static int poll_status(u32 __iomem *reg, u32 flag)
  70. {
  71. int wait = 1000000; /* 1 sec is long enough */
  72. while (readl(reg) & flag) {
  73. if (wait-- < 0)
  74. return -EREMOTEIO;
  75. udelay(1);
  76. }
  77. return 0;
  78. }
  79. static int reset_bus(struct uniphier_fi2c_regs __iomem *regs)
  80. {
  81. int ret;
  82. /* bus forcible reset */
  83. writel(I2C_RST_RST, &regs->rst);
  84. ret = poll_status(&regs->rst, I2C_RST_RST);
  85. if (ret < 0)
  86. debug("error: fail to reset I2C controller\n");
  87. return ret;
  88. }
  89. static int check_device_busy(struct uniphier_fi2c_regs __iomem *regs)
  90. {
  91. int ret;
  92. ret = poll_status(&regs->sr, I2C_SR_DB);
  93. if (ret < 0) {
  94. debug("error: device busy too long. reset...\n");
  95. ret = reset_bus(regs);
  96. }
  97. return ret;
  98. }
  99. static int uniphier_fi2c_probe(struct udevice *dev)
  100. {
  101. fdt_addr_t addr;
  102. fdt_size_t size;
  103. struct uniphier_fi2c_dev *priv = dev_get_priv(dev);
  104. int ret;
  105. addr = fdtdec_get_addr_size(gd->fdt_blob, dev->of_offset, "reg",
  106. &size);
  107. priv->regs = map_sysmem(addr, size);
  108. if (!priv->regs)
  109. return -ENOMEM;
  110. priv->fioclk = FIOCLK;
  111. /* bus forcible reset */
  112. ret = reset_bus(priv->regs);
  113. if (ret < 0)
  114. return ret;
  115. writel(I2C_BRST_FOEN | I2C_BRST_RSCLO, &priv->regs->brst);
  116. return 0;
  117. }
  118. static int uniphier_fi2c_remove(struct udevice *dev)
  119. {
  120. struct uniphier_fi2c_dev *priv = dev_get_priv(dev);
  121. unmap_sysmem(priv->regs);
  122. return 0;
  123. }
  124. static int wait_for_irq(struct uniphier_fi2c_dev *dev, u32 flags,
  125. bool *stop)
  126. {
  127. u32 irq;
  128. unsigned long wait = dev->timeout;
  129. int ret = -EREMOTEIO;
  130. do {
  131. udelay(1);
  132. irq = readl(&dev->regs->intr);
  133. } while (!(irq & flags) && wait--);
  134. if (wait < 0) {
  135. debug("error: time out\n");
  136. return ret;
  137. }
  138. if (irq & I2C_INT_AL) {
  139. debug("error: arbitration lost\n");
  140. *stop = false;
  141. return ret;
  142. }
  143. if (irq & I2C_INT_NA) {
  144. debug("error: no answer\n");
  145. return ret;
  146. }
  147. return 0;
  148. }
  149. static int issue_stop(struct uniphier_fi2c_dev *dev, int old_ret)
  150. {
  151. int ret;
  152. debug("stop condition\n");
  153. writel(I2C_CR_MST | I2C_CR_STO, &dev->regs->cr);
  154. ret = poll_status(&dev->regs->sr, I2C_SR_DB);
  155. if (ret < 0)
  156. debug("error: device busy after operation\n");
  157. return old_ret ? old_ret : ret;
  158. }
  159. static int uniphier_fi2c_transmit(struct uniphier_fi2c_dev *dev, uint addr,
  160. uint len, const u8 *buf, bool *stop)
  161. {
  162. int ret;
  163. const u32 irq_flags = I2C_INT_TE | I2C_INT_NA | I2C_INT_AL;
  164. struct uniphier_fi2c_regs __iomem *regs = dev->regs;
  165. debug("%s: addr = %x, len = %d\n", __func__, addr, len);
  166. writel(I2C_DTTX_CMD | addr << 1, &regs->dttx);
  167. writel(irq_flags, &regs->ie);
  168. writel(irq_flags, &regs->ic);
  169. debug("start condition\n");
  170. writel(I2C_CR_MST | I2C_CR_STA, &regs->cr);
  171. ret = wait_for_irq(dev, irq_flags, stop);
  172. if (ret < 0)
  173. goto error;
  174. while (len--) {
  175. debug("sending %x\n", *buf);
  176. writel(*buf++, &regs->dttx);
  177. writel(irq_flags, &regs->ic);
  178. ret = wait_for_irq(dev, irq_flags, stop);
  179. if (ret < 0)
  180. goto error;
  181. }
  182. error:
  183. writel(irq_flags, &regs->ic);
  184. if (*stop)
  185. ret = issue_stop(dev, ret);
  186. return ret;
  187. }
  188. static int uniphier_fi2c_receive(struct uniphier_fi2c_dev *dev, uint addr,
  189. uint len, u8 *buf, bool *stop)
  190. {
  191. int ret = 0;
  192. const u32 irq_flags = I2C_INT_RB | I2C_INT_NA | I2C_INT_AL;
  193. struct uniphier_fi2c_regs __iomem *regs = dev->regs;
  194. debug("%s: addr = %x, len = %d\n", __func__, addr, len);
  195. /*
  196. * In case 'len == 0', only the slave address should be sent
  197. * for probing, which is covered by the transmit function.
  198. */
  199. if (len == 0)
  200. return uniphier_fi2c_transmit(dev, addr, len, buf, stop);
  201. writel(I2C_DTTX_CMD | I2C_DTTX_RD | addr << 1, &regs->dttx);
  202. writel(0, &regs->rbc);
  203. writel(irq_flags, &regs->ie);
  204. writel(irq_flags, &regs->ic);
  205. debug("start condition\n");
  206. writel(I2C_CR_MST | I2C_CR_STA | (len == 1 ? I2C_CR_NACK : 0),
  207. &regs->cr);
  208. while (len--) {
  209. ret = wait_for_irq(dev, irq_flags, stop);
  210. if (ret < 0)
  211. goto error;
  212. *buf++ = readl(&regs->dtrx);
  213. debug("received %x\n", *(buf - 1));
  214. if (len == 1)
  215. writel(I2C_CR_MST | I2C_CR_NACK, &regs->cr);
  216. writel(irq_flags, &regs->ic);
  217. }
  218. error:
  219. writel(irq_flags, &regs->ic);
  220. if (*stop)
  221. ret = issue_stop(dev, ret);
  222. return ret;
  223. }
  224. static int uniphier_fi2c_xfer(struct udevice *bus, struct i2c_msg *msg,
  225. int nmsgs)
  226. {
  227. int ret;
  228. struct uniphier_fi2c_dev *dev = dev_get_priv(bus);
  229. bool stop;
  230. ret = check_device_busy(dev->regs);
  231. if (ret < 0)
  232. return ret;
  233. for (; nmsgs > 0; nmsgs--, msg++) {
  234. /* If next message is read, skip the stop condition */
  235. stop = nmsgs > 1 && msg[1].flags & I2C_M_RD ? false : true;
  236. if (msg->flags & I2C_M_RD)
  237. ret = uniphier_fi2c_receive(dev, msg->addr, msg->len,
  238. msg->buf, &stop);
  239. else
  240. ret = uniphier_fi2c_transmit(dev, msg->addr, msg->len,
  241. msg->buf, &stop);
  242. if (ret < 0)
  243. break;
  244. }
  245. return ret;
  246. }
  247. static int uniphier_fi2c_set_bus_speed(struct udevice *bus, unsigned int speed)
  248. {
  249. int ret;
  250. unsigned int clk_count;
  251. struct uniphier_fi2c_dev *dev = dev_get_priv(bus);
  252. struct uniphier_fi2c_regs __iomem *regs = dev->regs;
  253. /* max supported frequency is 400 kHz */
  254. if (speed > 400000)
  255. return -EINVAL;
  256. ret = check_device_busy(dev->regs);
  257. if (ret < 0)
  258. return ret;
  259. /* make sure the bus is idle when changing the frequency */
  260. writel(I2C_BRST_RSCLO, &regs->brst);
  261. clk_count = dev->fioclk / speed;
  262. writel(clk_count, &regs->cyc);
  263. writel(clk_count / 2, &regs->lctl);
  264. writel(clk_count / 2, &regs->ssut);
  265. writel(clk_count / 16, &regs->dsut);
  266. writel(I2C_BRST_FOEN | I2C_BRST_RSCLO, &regs->brst);
  267. /*
  268. * Theoretically, each byte can be transferred in
  269. * 1000000 * 9 / speed usec.
  270. * This time out value is long enough.
  271. */
  272. dev->timeout = 100000000L / speed;
  273. return 0;
  274. }
  275. static const struct dm_i2c_ops uniphier_fi2c_ops = {
  276. .xfer = uniphier_fi2c_xfer,
  277. .set_bus_speed = uniphier_fi2c_set_bus_speed,
  278. };
  279. static const struct udevice_id uniphier_fi2c_of_match[] = {
  280. { .compatible = "socionext,uniphier-fi2c" },
  281. { /* sentinel */ }
  282. };
  283. U_BOOT_DRIVER(uniphier_fi2c) = {
  284. .name = "uniphier-fi2c",
  285. .id = UCLASS_I2C,
  286. .of_match = uniphier_fi2c_of_match,
  287. .probe = uniphier_fi2c_probe,
  288. .remove = uniphier_fi2c_remove,
  289. .priv_auto_alloc_size = sizeof(struct uniphier_fi2c_dev),
  290. .ops = &uniphier_fi2c_ops,
  291. };