init.S 9.8 KB

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  1. /*
  2. * SPDX-License-Identifier: GPL-2.0 IBM-pibs
  3. */
  4. #include <config.h>
  5. #include <asm/ppc4xx.h>
  6. #include <ppc_asm.tmpl>
  7. #include <ppc_defs.h>
  8. #include <asm/cache.h>
  9. #include <asm/mmu.h>
  10. /**
  11. * ext_bus_cntlr_init - Initializes the External Bus Controller for the external peripherals
  12. *
  13. * IMPORTANT: For pass1 this code must run from cache since you can not
  14. * reliably change a peripheral banks timing register (pbxap) while running
  15. * code from that bank. For ex., since we are running from ROM on bank 0, we
  16. * can NOT execute the code that modifies bank 0 timings from ROM, so
  17. * we run it from cache.
  18. *
  19. * Bank 0 - Boot-Flash
  20. * Bank 1 - NAND-Flash
  21. * Bank 2 - ISA bus
  22. * Bank 3 - Second Flash
  23. * Bank 4 - USB controller
  24. */
  25. .globl ext_bus_cntlr_init
  26. ext_bus_cntlr_init:
  27. /*
  28. * We need the current boot up configuration to set correct
  29. * timings into internal flash and external flash
  30. */
  31. mfdcr r24,CPC0_PSR /* xxxx xxxx xxxx xxx? ?xxx xxxx xxxx xxxx
  32. 0 0 -> 8 bit external ROM
  33. 0 1 -> 16 bit internal ROM */
  34. addi r4,0,2
  35. srw r24,r24,r4 /* shift right r24 two positions */
  36. andi. r24,r24,0x06000
  37. /*
  38. * All calculations are based on 33MHz EBC clock.
  39. *
  40. * First, create a "very slow" timing (~250ns) with burst mode enabled
  41. * This is need for the external flash access
  42. */
  43. lis r25,0x0800
  44. /* 0000 1000 0xxx 0000 0000 0010 100x xxxx = 0x03800280 */
  45. ori r25,r25,0x0280
  46. /*
  47. * Second, create a fast timing:
  48. * 90ns first cycle - 3 clock access
  49. * and 90ns burst cycle, plus 1 clock after the last access
  50. * This is used for the internal access
  51. */
  52. lis r26,0x8900
  53. /* 1000 1001 0xxx 0000 0000 0010 100x xxxx */
  54. ori r26,r26,0x0280
  55. /*
  56. * We can't change settings on CS# if we currently use them.
  57. * -> load a few instructions into cache and run this code from cache
  58. */
  59. mflr r4 /* save link register */
  60. bl ..getAddr
  61. ..getAddr:
  62. mflr r3 /* get address of ..getAddr */
  63. mtlr r4 /* restore link register */
  64. addi r4,0,14 /* set ctr to 10; used to prefetch */
  65. mtctr r4 /* 10 cache lines to fit this function
  66. in cache (gives us 8x10=80 instructions) */
  67. ..ebcloop:
  68. icbt r0,r3 /* prefetch cache line for addr in r3 */
  69. addi r3,r3,32 /* move to next cache line */
  70. bdnz ..ebcloop /* continue for 10 cache lines */
  71. /*
  72. * Delay to ensure all accesses to ROM are complete before changing
  73. * bank 0 timings. 200usec should be enough.
  74. * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles
  75. */
  76. lis r3,0x0
  77. ori r3,r3,0xA000 /* ensure 200usec have passed since reset */
  78. mtctr r3
  79. ..spinlp:
  80. bdnz ..spinlp /* spin loop */
  81. /*-----------------------------------------------------------------------
  82. * Memory Bank 0 (BOOT-ROM) initialization
  83. * 0xFFEF00000....0xFFFFFFF
  84. * We only have to change the timing. Mapping is ok by boot-strapping
  85. *----------------------------------------------------------------------- */
  86. li r4,PB1AP /* PB0AP=Peripheral Bank 0 Access Parameters */
  87. mtdcr EBC0_CFGADDR,r4
  88. mr r4,r26 /* assume internal fast flash is boot flash */
  89. cmpwi r24,0x2000 /* assumption true? ... */
  90. beq 1f /* ...yes! */
  91. mr r4,r25 /* ...no, use the slow variant */
  92. mr r25,r26 /* use this for the other flash */
  93. 1:
  94. mtdcr EBC0_CFGDATA,r4 /* change timing now */
  95. li r4,PB0CR /* PB0CR=Peripheral Bank 0 Control Register */
  96. mtdcr EBC0_CFGADDR,r4
  97. mfdcr r4,EBC0_CFGDATA
  98. lis r3,0x0001
  99. ori r3,r3,0x8000 /* allow reads and writes */
  100. or r4,r4,r3
  101. mtdcr EBC0_CFGDATA,r4
  102. /*-----------------------------------------------------------------------
  103. * Memory Bank 3 (Second-Flash) initialization
  104. * 0xF0000000...0xF01FFFFF -> 2MB
  105. *----------------------------------------------------------------------- */
  106. li r4,PB3AP /* Peripheral Bank 1 Access Parameter */
  107. mtdcr EBC0_CFGADDR,r4
  108. mtdcr EBC0_CFGDATA,r2 /* change timing */
  109. li r4,PB3CR /* Peripheral Bank 1 Configuration Registers */
  110. mtdcr EBC0_CFGADDR,r4
  111. lis r4,0xF003
  112. ori r4,r4,0x8000
  113. /*
  114. * Consider boot configuration
  115. */
  116. xori r24,r24,0x2000 /* invert current bus width */
  117. or r4,r4,r24
  118. mtdcr EBC0_CFGDATA,r4
  119. /*-----------------------------------------------------------------------
  120. * Memory Bank 1 (NAND-Flash) initialization
  121. * 0x77D00000...0x77DFFFFF -> 1MB
  122. * - the write/read pulse to the NAND can be as short as 25ns, bus the cycle time is always 50ns
  123. * - the setup time is 0ns
  124. * - the hold time is 15ns
  125. * ->
  126. * - TWT = 0
  127. * - CSN = 0
  128. * - OEN = 0
  129. * - WBN = 0
  130. * - WBF = 0
  131. * - TH = 1
  132. * ----> 2 clocks per cycle = 60ns cycle (30ns active, 30ns hold)
  133. *----------------------------------------------------------------------- */
  134. li r4,PB1AP /* Peripheral Bank 1 Access Parameter */
  135. mtdcr EBC0_CFGADDR,r4
  136. lis r4,0x0000
  137. ori r4,r4,0x0200
  138. mtdcr EBC0_CFGDATA,r4
  139. li r4,PB1CR /* Peripheral Bank 1 Configuration Registers */
  140. mtdcr EBC0_CFGADDR,r4
  141. lis r4,0x77D1
  142. ori r4,r4,0x8000
  143. mtdcr EBC0_CFGDATA,r4
  144. /* USB init (without acceleration) */
  145. #ifndef CONFIG_ISP1161_PRESENT
  146. li r4,PB4AP /* PB4AP=Peripheral Bank 4 Access Parameters */
  147. mtdcr EBC0_CFGADDR,r4
  148. lis r4,0x0180
  149. ori r4,r4,0x5940
  150. mtdcr EBC0_CFGDATA,r4
  151. #endif
  152. /*-----------------------------------------------------------------------
  153. * Memory Bank 2 (ISA Access) initialization (plus memory bank 6 and 7)
  154. * 0x78000000...0x7BFFFFFF -> 64 MB
  155. * Wir arbeiten bei 33 MHz -> 30ns
  156. *-----------------------------------------------------------------------
  157. A7 (ppc notation) or A24 (standard notation) decides about
  158. the type of access:
  159. A7/A24=0 -> memory cycle
  160. A7/ /A24=1 -> I/O cycle
  161. */
  162. li r4,PB2AP /* PB2AP=Peripheral Bank 2 Access Parameters */
  163. mtdcr EBC0_CFGADDR,r4
  164. /*
  165. We emulate an ISA access
  166. 1. Address active
  167. 2. wait 0 EBC clocks -> CSN=0
  168. 3. set CS#
  169. 4. wait 0 EBC clock -> OEN/WBN=0
  170. 5. set OE#/WE#
  171. 6. wait 4 clocks (ca. 90ns) and for Ready signal
  172. 7. hold for 4 clocks -> TH=4
  173. */
  174. #if 1
  175. /* faster access to isa-bus */
  176. lis r4,0x0180
  177. ori r4,r4,0x5940
  178. #else
  179. lis r4,0x0100
  180. ori r4,r4,0x0340
  181. #endif
  182. mtdcr EBC0_CFGDATA,r4
  183. #ifdef IDE_USES_ISA_EMULATION
  184. li r25,PB5AP /* PB5AP=Peripheral Bank 5 Access Parameters */
  185. mtdcr EBC0_CFGADDR,r25
  186. mtdcr EBC0_CFGDATA,r4
  187. #endif
  188. li r25,PB6AP /* PB6AP=Peripheral Bank 6 Access Parameters */
  189. mtdcr EBC0_CFGADDR,r25
  190. mtdcr EBC0_CFGDATA,r4
  191. li r25,PB7AP /* PB7AP=Peripheral Bank 7 Access Parameters */
  192. mtdcr EBC0_CFGADDR,r25
  193. mtdcr EBC0_CFGDATA,r4
  194. li r25,PB2CR /* PB2CR=Peripheral Bank 2 Configuration Register */
  195. mtdcr EBC0_CFGADDR,r25
  196. lis r4,0x780B
  197. ori r4,r4,0xA000
  198. mtdcr EBC0_CFGDATA,r4
  199. /*
  200. * the other areas are only 1MiB in size
  201. */
  202. lis r4,0x7401
  203. ori r4,r4,0xA000
  204. li r25,PB6CR /* PB6CR=Peripheral Bank 6 Configuration Register */
  205. mtdcr EBC0_CFGADDR,r25
  206. lis r4,0x7401
  207. ori r4,r4,0xA000
  208. mtdcr EBC0_CFGDATA,r4
  209. li r25,PB7CR /* PB7CR=Peripheral Bank 7 Configuration Register */
  210. mtdcr EBC0_CFGADDR,r25
  211. lis r4,0x7411
  212. ori r4,r4,0xA000
  213. mtdcr EBC0_CFGDATA,r4
  214. #ifndef CONFIG_ISP1161_PRESENT
  215. li r25,PB4CR /* PB4CR=Peripheral Bank 4 Configuration Register */
  216. mtdcr EBC0_CFGADDR,r25
  217. lis r4,0x7421
  218. ori r4,r4,0xA000
  219. mtdcr EBC0_CFGDATA,r4
  220. #endif
  221. #ifdef IDE_USES_ISA_EMULATION
  222. li r25,PB5CR /* PB5CR=Peripheral Bank 5 Configuration Register */
  223. mtdcr EBC0_CFGADDR,r25
  224. lis r4,0x0000
  225. ori r4,r4,0x0000
  226. mtdcr EBC0_CFGDATA,r4
  227. #endif
  228. /*-----------------------------------------------------------------------
  229. * Memory bank 4: USB controller Philips ISP6111
  230. * 0x77C00000 ... 0x77CFFFFF
  231. *
  232. * The chip is connected to:
  233. * - CPU CS#4
  234. * - CPU IRQ#2
  235. * - CPU DMA 3
  236. *
  237. * Timing:
  238. * - command to first data: 300ns. Software must ensure this timing!
  239. * - Write pulse: 26ns
  240. * - Read pulse: 33ns
  241. * - read cycle time: 150ns
  242. * - write cycle time: 140ns
  243. *
  244. * Note: All calculations are based on 33MHz EBC clock. One '#' or '_' is 30ns
  245. *
  246. * |- 300ns --|
  247. * |---- 420ns ---|---- 420ns ---| cycle
  248. * CS ############:###____#######:###____#######
  249. * OE ############:####___#######:####___#######
  250. * WE ############:####__########:####__########
  251. *
  252. * ----> 2 clocks RD/WR pulses: 60ns
  253. * ----> CSN: 3 clock, 90ns
  254. * ----> OEN: 1 clocks (read cycle)
  255. * ----> WBN: 1 clocks (write cycle)
  256. * ----> WBE: 2 clocks
  257. * ----> TH: 7 clock, 210ns
  258. * ----> TWT: 7 clocks
  259. *----------------------------------------------------------------------- */
  260. #ifdef CONFIG_ISP1161_PRESENT
  261. li r4,PB4AP /* PB4AP=Peripheral Bank 4 Access Parameters */
  262. mtdcr EBC0_CFGADDR,r4
  263. lis r4,0x030D
  264. ori r4,r4,0x5E80
  265. mtdcr EBC0_CFGDATA,r4
  266. li r4,PB4CR /* PB2CR=Peripheral Bank 4 Configuration Register */
  267. mtdcr EBC0_CFGADDR,r4
  268. lis r4,0x77C1
  269. ori r4,r4,0xA000
  270. mtdcr EBC0_CFGDATA,r4
  271. #endif
  272. #ifndef IDE_USES_ISA_EMULATION
  273. /*-----------------------------------------------------------------------
  274. * Memory Bank 5 used for IDE access
  275. *
  276. * Timings for IDE Interface
  277. *
  278. * SETUP / LENGTH / HOLD - cycles valid for 33.3 MHz clk -> 30ns cycle time
  279. * 70 165 30 PIO-Mode 0, [ns]
  280. * 3 6 1 [Cycles] ----> AP=0x040C0200
  281. * 50 125 20 PIO-Mode 1, [ns]
  282. * 2 5 1 [Cycles] ----> AP=0x03080200
  283. * 30 100 15 PIO-Mode 2, [ns]
  284. * 1 4 1 [Cycles] ----> AP=0x02040200
  285. * 30 80 10 PIO-Mode 3, [ns]
  286. * 1 3 1 [Cycles] ----> AP=0x01840200
  287. * 25 70 10 PIO-Mode 4, [ns]
  288. * 1 3 1 [Cycles] ----> AP=0x01840200
  289. *
  290. *----------------------------------------------------------------------- */
  291. li r4,PB5AP
  292. mtdcr EBC0_CFGADDR,r4
  293. lis r4,0x040C
  294. ori r4,r4,0x0200
  295. mtdcr EBC0_CFGDATA,r4
  296. li r4,PB5CR /* PB2CR=Peripheral Bank 2 Configuration Register */
  297. mtdcr EBC0_CFGADDR,r4
  298. lis r4,0x7A01
  299. ori r4,r4,0xA000
  300. mtdcr EBC0_CFGDATA,r4
  301. #endif
  302. /*
  303. * External Peripheral Control Register
  304. */
  305. li r4,EBC0_CFG
  306. mtdcr EBC0_CFGADDR,r4
  307. lis r4,0xB84E
  308. ori r4,r4,0xF000
  309. mtdcr EBC0_CFGDATA,r4
  310. /*
  311. * drive POST code
  312. */
  313. lis r4,0x7900
  314. ori r4,r4,0x0080
  315. li r3,0x0001
  316. stb r3,0(r4) /* 01 -> external bus controller is initialized */
  317. nop /* pass2 DCR errata #8 */
  318. blr