exynos5800-peach-pi.dts 3.3 KB

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  1. /*
  2. * SAMSUNG/GOOGLE Peach-Pit board device tree source
  3. *
  4. * Copyright (c) 2013 Samsung Electronics Co., Ltd.
  5. * http://www.samsung.com
  6. *
  7. * SPDX-License-Identifier: GPL-2.0+
  8. */
  9. /dts-v1/;
  10. #include "exynos54xx.dtsi"
  11. / {
  12. model = "Samsung/Google Peach Pi board based on Exynos5800";
  13. compatible = "google,pit-rev#", "google,pit",
  14. "google,peach", "samsung,exynos5800", "samsung,exynos5";
  15. config {
  16. google,bad-wake-gpios = <&gpx0 6 GPIO_ACTIVE_HIGH>;
  17. hwid = "PIT TEST A-A 7848";
  18. lazy-init = <1>;
  19. };
  20. aliases {
  21. serial0 = "/serial@12C30000";
  22. console = "/serial@12C30000";
  23. pmic = "/i2c@12ca0000";
  24. };
  25. dmc {
  26. mem-manuf = "samsung";
  27. mem-type = "ddr3";
  28. clock-frequency = <800000000>;
  29. arm-frequency = <900000000>;
  30. };
  31. tmu@10060000 {
  32. samsung,min-temp = <25>;
  33. samsung,max-temp = <125>;
  34. samsung,start-warning = <95>;
  35. samsung,start-tripping = <105>;
  36. samsung,hw-tripping = <110>;
  37. samsung,efuse-min-value = <40>;
  38. samsung,efuse-value = <55>;
  39. samsung,efuse-max-value = <100>;
  40. samsung,slope = <274761730>;
  41. samsung,dc-value = <25>;
  42. };
  43. /* MAX77802 is on i2c bus 4 */
  44. i2c@12ca0000 {
  45. clock-frequency = <400000>;
  46. power-regulator@9 {
  47. compatible = "maxim,max77802-pmic";
  48. reg = <0x9>;
  49. };
  50. };
  51. i2c@12cd0000 { /* i2c7 */
  52. clock-frequency = <100000>;
  53. soundcodec@20 {
  54. reg = <0x20>;
  55. compatible = "maxim,max98090-codec";
  56. };
  57. };
  58. sound@3830000 {
  59. samsung,codec-type = "max98090";
  60. };
  61. i2c@12e10000 { /* i2c9 */
  62. clock-frequency = <400000>;
  63. tpm@20 {
  64. compatible = "infineon,slb9645-tpm";
  65. reg = <0x20>;
  66. };
  67. };
  68. spi@12d30000 { /* spi1 */
  69. spi-max-frequency = <50000000>;
  70. firmware_storage_spi: flash@0 {
  71. reg = <0>;
  72. /*
  73. * A region for the kernel to store a panic event
  74. * which the firmware will add to the log.
  75. */
  76. elog-panic-event-offset = <0x01e00000 0x100000>;
  77. elog-shrink-size = <0x400>;
  78. elog-full-threshold = <0xc00>;
  79. };
  80. };
  81. spi@12d40000 { /* spi2 */
  82. spi-max-frequency = <4000000>;
  83. spi-deactivate-delay = <200>;
  84. cros_ec: cros-ec@0 {
  85. compatible = "google,cros-ec-spi";
  86. reg = <0>;
  87. spi-half-duplex;
  88. spi-max-timeout-ms = <1100>;
  89. ec-interrupt = <&gpx1 5 GPIO_ACTIVE_LOW>;
  90. /*
  91. * This describes the flash memory within the EC. Note
  92. * that the STM32L flash erases to 0, not 0xff.
  93. */
  94. #address-cells = <1>;
  95. #size-cells = <1>;
  96. flash@8000000 {
  97. reg = <0x08000000 0x20000>;
  98. erase-value = <0>;
  99. };
  100. };
  101. };
  102. xhci@12000000 {
  103. samsung,vbus-gpio = <&gph0 0 GPIO_ACTIVE_HIGH>;
  104. };
  105. xhci@12400000 {
  106. samsung,vbus-gpio = <&gph0 1 GPIO_ACTIVE_HIGH>;
  107. };
  108. fimd@14400000 {
  109. samsung,vl-freq = <60>;
  110. samsung,vl-col = <1920>;
  111. samsung,vl-row = <1080>;
  112. samsung,vl-width = <1920>;
  113. samsung,vl-height = <1080>;
  114. samsung,vl-clkp;
  115. samsung,vl-dp;
  116. samsung,vl-bpix = <4>;
  117. samsung,vl-hspw = <80>;
  118. samsung,vl-hbpd = <172>;
  119. samsung,vl-hfpd = <60>;
  120. samsung,vl-vspw = <10>;
  121. samsung,vl-vbpd = <25>;
  122. samsung,vl-vfpd = <10>;
  123. samsung,vl-cmd-allow-len = <0xf>;
  124. samsung,power-on-delay = <30000>;
  125. samsung,winid = <3>;
  126. samsung,interface-mode = <1>;
  127. samsung,dp-enabled = <1>;
  128. samsung,dual-lcd-enabled = <0>;
  129. samsung,bl-en-gpio = <&gpx2 2 GPIO_ACTIVE_HIGH>;
  130. };
  131. };
  132. #include "cros-ec-keyboard.dtsi"