stm32_sdmmc2.c 17 KB

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  1. /*
  2. * Copyright (C) STMicroelectronics SA 2017
  3. * Author(s): Patrice CHOTARD, <patrice.chotard@st.com> for STMicroelectronics.
  4. *
  5. * SPDX-License-Identifier: GPL-2.0+
  6. */
  7. #include <common.h>
  8. #include <clk.h>
  9. #include <dm.h>
  10. #include <fdtdec.h>
  11. #include <libfdt.h>
  12. #include <mmc.h>
  13. #include <reset.h>
  14. #include <asm/io.h>
  15. #include <asm/gpio.h>
  16. #include <linux/iopoll.h>
  17. struct stm32_sdmmc2_plat {
  18. struct mmc_config cfg;
  19. struct mmc mmc;
  20. };
  21. struct stm32_sdmmc2_priv {
  22. fdt_addr_t base;
  23. struct clk clk;
  24. struct reset_ctl reset_ctl;
  25. struct gpio_desc cd_gpio;
  26. u32 clk_reg_msk;
  27. u32 pwr_reg_msk;
  28. };
  29. struct stm32_sdmmc2_ctx {
  30. u32 cache_start;
  31. u32 cache_end;
  32. u32 data_length;
  33. bool dpsm_abort;
  34. };
  35. /* SDMMC REGISTERS OFFSET */
  36. #define SDMMC_POWER 0x00 /* SDMMC power control */
  37. #define SDMMC_CLKCR 0x04 /* SDMMC clock control */
  38. #define SDMMC_ARG 0x08 /* SDMMC argument */
  39. #define SDMMC_CMD 0x0C /* SDMMC command */
  40. #define SDMMC_RESP1 0x14 /* SDMMC response 1 */
  41. #define SDMMC_RESP2 0x18 /* SDMMC response 2 */
  42. #define SDMMC_RESP3 0x1C /* SDMMC response 3 */
  43. #define SDMMC_RESP4 0x20 /* SDMMC response 4 */
  44. #define SDMMC_DTIMER 0x24 /* SDMMC data timer */
  45. #define SDMMC_DLEN 0x28 /* SDMMC data length */
  46. #define SDMMC_DCTRL 0x2C /* SDMMC data control */
  47. #define SDMMC_DCOUNT 0x30 /* SDMMC data counter */
  48. #define SDMMC_STA 0x34 /* SDMMC status */
  49. #define SDMMC_ICR 0x38 /* SDMMC interrupt clear */
  50. #define SDMMC_MASK 0x3C /* SDMMC mask */
  51. #define SDMMC_IDMACTRL 0x50 /* SDMMC DMA control */
  52. #define SDMMC_IDMABASE0 0x58 /* SDMMC DMA buffer 0 base address */
  53. /* SDMMC_POWER register */
  54. #define SDMMC_POWER_PWRCTRL GENMASK(1, 0)
  55. #define SDMMC_POWER_VSWITCH BIT(2)
  56. #define SDMMC_POWER_VSWITCHEN BIT(3)
  57. #define SDMMC_POWER_DIRPOL BIT(4)
  58. /* SDMMC_CLKCR register */
  59. #define SDMMC_CLKCR_CLKDIV GENMASK(9, 0)
  60. #define SDMMC_CLKCR_CLKDIV_MAX SDMMC_CLKCR_CLKDIV
  61. #define SDMMC_CLKCR_PWRSAV BIT(12)
  62. #define SDMMC_CLKCR_WIDBUS_4 BIT(14)
  63. #define SDMMC_CLKCR_WIDBUS_8 BIT(15)
  64. #define SDMMC_CLKCR_NEGEDGE BIT(16)
  65. #define SDMMC_CLKCR_HWFC_EN BIT(17)
  66. #define SDMMC_CLKCR_DDR BIT(18)
  67. #define SDMMC_CLKCR_BUSSPEED BIT(19)
  68. #define SDMMC_CLKCR_SELCLKRX GENMASK(21, 20)
  69. /* SDMMC_CMD register */
  70. #define SDMMC_CMD_CMDINDEX GENMASK(5, 0)
  71. #define SDMMC_CMD_CMDTRANS BIT(6)
  72. #define SDMMC_CMD_CMDSTOP BIT(7)
  73. #define SDMMC_CMD_WAITRESP GENMASK(9, 8)
  74. #define SDMMC_CMD_WAITRESP_0 BIT(8)
  75. #define SDMMC_CMD_WAITRESP_1 BIT(9)
  76. #define SDMMC_CMD_WAITINT BIT(10)
  77. #define SDMMC_CMD_WAITPEND BIT(11)
  78. #define SDMMC_CMD_CPSMEN BIT(12)
  79. #define SDMMC_CMD_DTHOLD BIT(13)
  80. #define SDMMC_CMD_BOOTMODE BIT(14)
  81. #define SDMMC_CMD_BOOTEN BIT(15)
  82. #define SDMMC_CMD_CMDSUSPEND BIT(16)
  83. /* SDMMC_DCTRL register */
  84. #define SDMMC_DCTRL_DTEN BIT(0)
  85. #define SDMMC_DCTRL_DTDIR BIT(1)
  86. #define SDMMC_DCTRL_DTMODE GENMASK(3, 2)
  87. #define SDMMC_DCTRL_DBLOCKSIZE GENMASK(7, 4)
  88. #define SDMMC_DCTRL_DBLOCKSIZE_SHIFT 4
  89. #define SDMMC_DCTRL_RWSTART BIT(8)
  90. #define SDMMC_DCTRL_RWSTOP BIT(9)
  91. #define SDMMC_DCTRL_RWMOD BIT(10)
  92. #define SDMMC_DCTRL_SDMMCEN BIT(11)
  93. #define SDMMC_DCTRL_BOOTACKEN BIT(12)
  94. #define SDMMC_DCTRL_FIFORST BIT(13)
  95. /* SDMMC_STA register */
  96. #define SDMMC_STA_CCRCFAIL BIT(0)
  97. #define SDMMC_STA_DCRCFAIL BIT(1)
  98. #define SDMMC_STA_CTIMEOUT BIT(2)
  99. #define SDMMC_STA_DTIMEOUT BIT(3)
  100. #define SDMMC_STA_TXUNDERR BIT(4)
  101. #define SDMMC_STA_RXOVERR BIT(5)
  102. #define SDMMC_STA_CMDREND BIT(6)
  103. #define SDMMC_STA_CMDSENT BIT(7)
  104. #define SDMMC_STA_DATAEND BIT(8)
  105. #define SDMMC_STA_DHOLD BIT(9)
  106. #define SDMMC_STA_DBCKEND BIT(10)
  107. #define SDMMC_STA_DABORT BIT(11)
  108. #define SDMMC_STA_DPSMACT BIT(12)
  109. #define SDMMC_STA_CPSMACT BIT(13)
  110. #define SDMMC_STA_TXFIFOHE BIT(14)
  111. #define SDMMC_STA_RXFIFOHF BIT(15)
  112. #define SDMMC_STA_TXFIFOF BIT(16)
  113. #define SDMMC_STA_RXFIFOF BIT(17)
  114. #define SDMMC_STA_TXFIFOE BIT(18)
  115. #define SDMMC_STA_RXFIFOE BIT(19)
  116. #define SDMMC_STA_BUSYD0 BIT(20)
  117. #define SDMMC_STA_BUSYD0END BIT(21)
  118. #define SDMMC_STA_SDMMCIT BIT(22)
  119. #define SDMMC_STA_ACKFAIL BIT(23)
  120. #define SDMMC_STA_ACKTIMEOUT BIT(24)
  121. #define SDMMC_STA_VSWEND BIT(25)
  122. #define SDMMC_STA_CKSTOP BIT(26)
  123. #define SDMMC_STA_IDMATE BIT(27)
  124. #define SDMMC_STA_IDMABTC BIT(28)
  125. /* SDMMC_ICR register */
  126. #define SDMMC_ICR_CCRCFAILC BIT(0)
  127. #define SDMMC_ICR_DCRCFAILC BIT(1)
  128. #define SDMMC_ICR_CTIMEOUTC BIT(2)
  129. #define SDMMC_ICR_DTIMEOUTC BIT(3)
  130. #define SDMMC_ICR_TXUNDERRC BIT(4)
  131. #define SDMMC_ICR_RXOVERRC BIT(5)
  132. #define SDMMC_ICR_CMDRENDC BIT(6)
  133. #define SDMMC_ICR_CMDSENTC BIT(7)
  134. #define SDMMC_ICR_DATAENDC BIT(8)
  135. #define SDMMC_ICR_DHOLDC BIT(9)
  136. #define SDMMC_ICR_DBCKENDC BIT(10)
  137. #define SDMMC_ICR_DABORTC BIT(11)
  138. #define SDMMC_ICR_BUSYD0ENDC BIT(21)
  139. #define SDMMC_ICR_SDMMCITC BIT(22)
  140. #define SDMMC_ICR_ACKFAILC BIT(23)
  141. #define SDMMC_ICR_ACKTIMEOUTC BIT(24)
  142. #define SDMMC_ICR_VSWENDC BIT(25)
  143. #define SDMMC_ICR_CKSTOPC BIT(26)
  144. #define SDMMC_ICR_IDMATEC BIT(27)
  145. #define SDMMC_ICR_IDMABTCC BIT(28)
  146. #define SDMMC_ICR_STATIC_FLAGS ((GENMASK(28, 21)) | (GENMASK(11, 0)))
  147. /* SDMMC_MASK register */
  148. #define SDMMC_MASK_CCRCFAILIE BIT(0)
  149. #define SDMMC_MASK_DCRCFAILIE BIT(1)
  150. #define SDMMC_MASK_CTIMEOUTIE BIT(2)
  151. #define SDMMC_MASK_DTIMEOUTIE BIT(3)
  152. #define SDMMC_MASK_TXUNDERRIE BIT(4)
  153. #define SDMMC_MASK_RXOVERRIE BIT(5)
  154. #define SDMMC_MASK_CMDRENDIE BIT(6)
  155. #define SDMMC_MASK_CMDSENTIE BIT(7)
  156. #define SDMMC_MASK_DATAENDIE BIT(8)
  157. #define SDMMC_MASK_DHOLDIE BIT(9)
  158. #define SDMMC_MASK_DBCKENDIE BIT(10)
  159. #define SDMMC_MASK_DABORTIE BIT(11)
  160. #define SDMMC_MASK_TXFIFOHEIE BIT(14)
  161. #define SDMMC_MASK_RXFIFOHFIE BIT(15)
  162. #define SDMMC_MASK_RXFIFOFIE BIT(17)
  163. #define SDMMC_MASK_TXFIFOEIE BIT(18)
  164. #define SDMMC_MASK_BUSYD0ENDIE BIT(21)
  165. #define SDMMC_MASK_SDMMCITIE BIT(22)
  166. #define SDMMC_MASK_ACKFAILIE BIT(23)
  167. #define SDMMC_MASK_ACKTIMEOUTIE BIT(24)
  168. #define SDMMC_MASK_VSWENDIE BIT(25)
  169. #define SDMMC_MASK_CKSTOPIE BIT(26)
  170. #define SDMMC_MASK_IDMABTCIE BIT(28)
  171. /* SDMMC_IDMACTRL register */
  172. #define SDMMC_IDMACTRL_IDMAEN BIT(0)
  173. #define SDMMC_CMD_TIMEOUT 0xFFFFFFFF
  174. DECLARE_GLOBAL_DATA_PTR;
  175. static void stm32_sdmmc2_start_data(struct stm32_sdmmc2_priv *priv,
  176. struct mmc_data *data,
  177. struct stm32_sdmmc2_ctx *ctx)
  178. {
  179. u32 data_ctrl, idmabase0;
  180. /* Configure the SDMMC DPSM (Data Path State Machine) */
  181. data_ctrl = (__ilog2(data->blocksize) <<
  182. SDMMC_DCTRL_DBLOCKSIZE_SHIFT) &
  183. SDMMC_DCTRL_DBLOCKSIZE;
  184. if (data->flags & MMC_DATA_READ) {
  185. data_ctrl |= SDMMC_DCTRL_DTDIR;
  186. idmabase0 = (u32)data->dest;
  187. } else {
  188. idmabase0 = (u32)data->src;
  189. }
  190. /* Set the SDMMC Data TimeOut value */
  191. writel(SDMMC_CMD_TIMEOUT, priv->base + SDMMC_DTIMER);
  192. /* Set the SDMMC DataLength value */
  193. writel(ctx->data_length, priv->base + SDMMC_DLEN);
  194. /* Write to SDMMC DCTRL */
  195. writel(data_ctrl, priv->base + SDMMC_DCTRL);
  196. /* Cache align */
  197. ctx->cache_start = rounddown(idmabase0, ARCH_DMA_MINALIGN);
  198. ctx->cache_end = roundup(idmabase0 + ctx->data_length,
  199. ARCH_DMA_MINALIGN);
  200. /*
  201. * Flush data cache before DMA start (clean and invalidate)
  202. * Clean also needed for read
  203. * Avoid issue on buffer not cached-aligned
  204. */
  205. flush_dcache_range(ctx->cache_start, ctx->cache_end);
  206. /* Enable internal DMA */
  207. writel(idmabase0, priv->base + SDMMC_IDMABASE0);
  208. writel(SDMMC_IDMACTRL_IDMAEN, priv->base + SDMMC_IDMACTRL);
  209. }
  210. static void stm32_sdmmc2_start_cmd(struct stm32_sdmmc2_priv *priv,
  211. struct mmc_cmd *cmd, u32 cmd_param)
  212. {
  213. if (readl(priv->base + SDMMC_ARG) & SDMMC_CMD_CPSMEN)
  214. writel(0, priv->base + SDMMC_ARG);
  215. cmd_param |= cmd->cmdidx | SDMMC_CMD_CPSMEN;
  216. if (cmd->resp_type & MMC_RSP_PRESENT) {
  217. if (cmd->resp_type & MMC_RSP_136)
  218. cmd_param |= SDMMC_CMD_WAITRESP;
  219. else if (cmd->resp_type & MMC_RSP_CRC)
  220. cmd_param |= SDMMC_CMD_WAITRESP_0;
  221. else
  222. cmd_param |= SDMMC_CMD_WAITRESP_1;
  223. }
  224. /* Clear flags */
  225. writel(SDMMC_ICR_STATIC_FLAGS, priv->base + SDMMC_ICR);
  226. /* Set SDMMC argument value */
  227. writel(cmd->cmdarg, priv->base + SDMMC_ARG);
  228. /* Set SDMMC command parameters */
  229. writel(cmd_param, priv->base + SDMMC_CMD);
  230. }
  231. static int stm32_sdmmc2_end_cmd(struct stm32_sdmmc2_priv *priv,
  232. struct mmc_cmd *cmd,
  233. struct stm32_sdmmc2_ctx *ctx)
  234. {
  235. u32 mask = SDMMC_STA_CTIMEOUT;
  236. u32 status;
  237. int ret;
  238. if (cmd->resp_type & MMC_RSP_PRESENT) {
  239. mask |= SDMMC_STA_CMDREND;
  240. if (cmd->resp_type & MMC_RSP_CRC)
  241. mask |= SDMMC_STA_CCRCFAIL;
  242. } else {
  243. mask |= SDMMC_STA_CMDSENT;
  244. }
  245. /* Polling status register */
  246. ret = readl_poll_timeout(priv->base + SDMMC_STA, status, status & mask,
  247. 10000);
  248. if (ret < 0) {
  249. debug("%s: timeout reading SDMMC_STA register\n", __func__);
  250. ctx->dpsm_abort = true;
  251. return ret;
  252. }
  253. /* Check status */
  254. if (status & SDMMC_STA_CTIMEOUT) {
  255. debug("%s: error SDMMC_STA_CTIMEOUT (0x%x) for cmd %d\n",
  256. __func__, status, cmd->cmdidx);
  257. ctx->dpsm_abort = true;
  258. return -ETIMEDOUT;
  259. }
  260. if (status & SDMMC_STA_CCRCFAIL && cmd->resp_type & MMC_RSP_CRC) {
  261. debug("%s: error SDMMC_STA_CCRCFAIL (0x%x) for cmd %d\n",
  262. __func__, status, cmd->cmdidx);
  263. ctx->dpsm_abort = true;
  264. return -EILSEQ;
  265. }
  266. if (status & SDMMC_STA_CMDREND && cmd->resp_type & MMC_RSP_PRESENT) {
  267. cmd->response[0] = readl(priv->base + SDMMC_RESP1);
  268. if (cmd->resp_type & MMC_RSP_136) {
  269. cmd->response[1] = readl(priv->base + SDMMC_RESP2);
  270. cmd->response[2] = readl(priv->base + SDMMC_RESP3);
  271. cmd->response[3] = readl(priv->base + SDMMC_RESP4);
  272. }
  273. }
  274. return 0;
  275. }
  276. static int stm32_sdmmc2_end_data(struct stm32_sdmmc2_priv *priv,
  277. struct mmc_cmd *cmd,
  278. struct mmc_data *data,
  279. struct stm32_sdmmc2_ctx *ctx)
  280. {
  281. u32 mask = SDMMC_STA_DCRCFAIL | SDMMC_STA_DTIMEOUT |
  282. SDMMC_STA_IDMATE | SDMMC_STA_DATAEND;
  283. u32 status;
  284. if (data->flags & MMC_DATA_READ)
  285. mask |= SDMMC_STA_RXOVERR;
  286. else
  287. mask |= SDMMC_STA_TXUNDERR;
  288. status = readl(priv->base + SDMMC_STA);
  289. while (!(status & mask))
  290. status = readl(priv->base + SDMMC_STA);
  291. /*
  292. * Need invalidate the dcache again to avoid any
  293. * cache-refill during the DMA operations (pre-fetching)
  294. */
  295. if (data->flags & MMC_DATA_READ)
  296. invalidate_dcache_range(ctx->cache_start, ctx->cache_end);
  297. if (status & SDMMC_STA_DCRCFAIL) {
  298. debug("%s: error SDMMC_STA_DCRCFAIL (0x%x) for cmd %d\n",
  299. __func__, status, cmd->cmdidx);
  300. if (readl(priv->base + SDMMC_DCOUNT))
  301. ctx->dpsm_abort = true;
  302. return -EILSEQ;
  303. }
  304. if (status & SDMMC_STA_DTIMEOUT) {
  305. debug("%s: error SDMMC_STA_DTIMEOUT (0x%x) for cmd %d\n",
  306. __func__, status, cmd->cmdidx);
  307. ctx->dpsm_abort = true;
  308. return -ETIMEDOUT;
  309. }
  310. if (status & SDMMC_STA_TXUNDERR) {
  311. debug("%s: error SDMMC_STA_TXUNDERR (0x%x) for cmd %d\n",
  312. __func__, status, cmd->cmdidx);
  313. ctx->dpsm_abort = true;
  314. return -EIO;
  315. }
  316. if (status & SDMMC_STA_RXOVERR) {
  317. debug("%s: error SDMMC_STA_RXOVERR (0x%x) for cmd %d\n",
  318. __func__, status, cmd->cmdidx);
  319. ctx->dpsm_abort = true;
  320. return -EIO;
  321. }
  322. if (status & SDMMC_STA_IDMATE) {
  323. debug("%s: error SDMMC_STA_IDMATE (0x%x) for cmd %d\n",
  324. __func__, status, cmd->cmdidx);
  325. ctx->dpsm_abort = true;
  326. return -EIO;
  327. }
  328. return 0;
  329. }
  330. static int stm32_sdmmc2_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
  331. struct mmc_data *data)
  332. {
  333. struct stm32_sdmmc2_priv *priv = dev_get_priv(dev);
  334. struct stm32_sdmmc2_ctx ctx;
  335. u32 cmdat = data ? SDMMC_CMD_CMDTRANS : 0;
  336. int ret, retry = 3;
  337. retry_cmd:
  338. ctx.data_length = 0;
  339. ctx.dpsm_abort = false;
  340. if (data) {
  341. ctx.data_length = data->blocks * data->blocksize;
  342. stm32_sdmmc2_start_data(priv, data, &ctx);
  343. }
  344. stm32_sdmmc2_start_cmd(priv, cmd, cmdat);
  345. debug("%s: send cmd %d data: 0x%x @ 0x%x\n",
  346. __func__, cmd->cmdidx,
  347. data ? ctx.data_length : 0, (unsigned int)data);
  348. ret = stm32_sdmmc2_end_cmd(priv, cmd, &ctx);
  349. if (data && !ret)
  350. ret = stm32_sdmmc2_end_data(priv, cmd, data, &ctx);
  351. /* Clear flags */
  352. writel(SDMMC_ICR_STATIC_FLAGS, priv->base + SDMMC_ICR);
  353. if (data)
  354. writel(0x0, priv->base + SDMMC_IDMACTRL);
  355. /*
  356. * To stop Data Path State Machine, a stop_transmission command
  357. * shall be send on cmd or data errors.
  358. */
  359. if (ctx.dpsm_abort && (cmd->cmdidx != MMC_CMD_STOP_TRANSMISSION)) {
  360. struct mmc_cmd stop_cmd;
  361. stop_cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
  362. stop_cmd.cmdarg = 0;
  363. stop_cmd.resp_type = MMC_RSP_R1b;
  364. debug("%s: send STOP command to abort dpsm treatments\n",
  365. __func__);
  366. stm32_sdmmc2_start_cmd(priv, &stop_cmd, SDMMC_CMD_CMDSTOP);
  367. stm32_sdmmc2_end_cmd(priv, &stop_cmd, &ctx);
  368. writel(SDMMC_ICR_STATIC_FLAGS, priv->base + SDMMC_ICR);
  369. }
  370. if ((ret != -ETIMEDOUT) && (ret != 0) && retry) {
  371. printf("%s: cmd %d failed, retrying ...\n",
  372. __func__, cmd->cmdidx);
  373. retry--;
  374. goto retry_cmd;
  375. }
  376. debug("%s: end for CMD %d, ret = %d\n", __func__, cmd->cmdidx, ret);
  377. return ret;
  378. }
  379. static void stm32_sdmmc2_pwron(struct stm32_sdmmc2_priv *priv)
  380. {
  381. /* Reset */
  382. reset_assert(&priv->reset_ctl);
  383. udelay(2);
  384. reset_deassert(&priv->reset_ctl);
  385. udelay(1000);
  386. /* Set Power State to ON */
  387. writel(SDMMC_POWER_PWRCTRL | priv->pwr_reg_msk, priv->base + SDMMC_POWER);
  388. /*
  389. * 1ms: required power up waiting time before starting the
  390. * SD initialization sequence
  391. */
  392. udelay(1000);
  393. }
  394. #define IS_RISING_EDGE(reg) (reg & SDMMC_CLKCR_NEGEDGE ? 0 : 1)
  395. static int stm32_sdmmc2_set_ios(struct udevice *dev)
  396. {
  397. struct mmc *mmc = mmc_get_mmc_dev(dev);
  398. struct stm32_sdmmc2_priv *priv = dev_get_priv(dev);
  399. struct stm32_sdmmc2_plat *plat = dev_get_platdata(dev);
  400. struct mmc_config *cfg = &plat->cfg;
  401. u32 desired = mmc->clock;
  402. u32 sys_clock = clk_get_rate(&priv->clk);
  403. u32 clk = 0;
  404. debug("%s: bus_with = %d, clock = %d\n", __func__,
  405. mmc->bus_width, mmc->clock);
  406. if ((mmc->bus_width == 1) && (desired == cfg->f_min))
  407. stm32_sdmmc2_pwron(priv);
  408. /*
  409. * clk_div = 0 => command and data generated on SDMMCCLK falling edge
  410. * clk_div > 0 and NEGEDGE = 0 => command and data generated on
  411. * SDMMCCLK rising edge
  412. * clk_div > 0 and NEGEDGE = 1 => command and data generated on
  413. * SDMMCCLK falling edge
  414. */
  415. if (desired && ((sys_clock > desired) ||
  416. IS_RISING_EDGE(priv->clk_reg_msk))) {
  417. clk = DIV_ROUND_UP(sys_clock, 2 * desired);
  418. if (clk > SDMMC_CLKCR_CLKDIV_MAX)
  419. clk = SDMMC_CLKCR_CLKDIV_MAX;
  420. }
  421. if (mmc->bus_width == 4)
  422. clk |= SDMMC_CLKCR_WIDBUS_4;
  423. if (mmc->bus_width == 8)
  424. clk |= SDMMC_CLKCR_WIDBUS_8;
  425. writel(clk | priv->clk_reg_msk, priv->base + SDMMC_CLKCR);
  426. return 0;
  427. }
  428. static int stm32_sdmmc2_getcd(struct udevice *dev)
  429. {
  430. struct stm32_sdmmc2_priv *priv = dev_get_priv(dev);
  431. debug("stm32_sdmmc2_getcd called\n");
  432. if (dm_gpio_is_valid(&priv->cd_gpio))
  433. return dm_gpio_get_value(&priv->cd_gpio);
  434. return 1;
  435. }
  436. static const struct dm_mmc_ops stm32_sdmmc2_ops = {
  437. .send_cmd = stm32_sdmmc2_send_cmd,
  438. .set_ios = stm32_sdmmc2_set_ios,
  439. .get_cd = stm32_sdmmc2_getcd,
  440. };
  441. static int stm32_sdmmc2_probe(struct udevice *dev)
  442. {
  443. struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
  444. struct stm32_sdmmc2_plat *plat = dev_get_platdata(dev);
  445. struct stm32_sdmmc2_priv *priv = dev_get_priv(dev);
  446. struct mmc_config *cfg = &plat->cfg;
  447. int ret;
  448. priv->base = dev_read_addr(dev);
  449. if (priv->base == FDT_ADDR_T_NONE)
  450. return -EINVAL;
  451. if (dev_read_bool(dev, "st,negedge"))
  452. priv->clk_reg_msk |= SDMMC_CLKCR_NEGEDGE;
  453. if (dev_read_bool(dev, "st,dirpol"))
  454. priv->pwr_reg_msk |= SDMMC_POWER_DIRPOL;
  455. ret = clk_get_by_index(dev, 0, &priv->clk);
  456. if (ret)
  457. return ret;
  458. ret = clk_enable(&priv->clk);
  459. if (ret)
  460. goto clk_free;
  461. ret = reset_get_by_index(dev, 0, &priv->reset_ctl);
  462. if (ret)
  463. goto clk_disable;
  464. gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio,
  465. GPIOD_IS_IN);
  466. cfg->f_min = 400000;
  467. cfg->f_max = dev_read_u32_default(dev, "max-frequency", 52000000);
  468. cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
  469. cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
  470. cfg->name = "STM32 SDMMC2";
  471. cfg->host_caps = 0;
  472. if (cfg->f_max > 25000000)
  473. cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
  474. switch (dev_read_u32_default(dev, "bus-width", 1)) {
  475. case 8:
  476. cfg->host_caps |= MMC_MODE_8BIT;
  477. case 4:
  478. cfg->host_caps |= MMC_MODE_4BIT;
  479. break;
  480. case 1:
  481. break;
  482. default:
  483. pr_err("invalid \"bus-width\" property, force to 1\n");
  484. }
  485. upriv->mmc = &plat->mmc;
  486. return 0;
  487. clk_disable:
  488. clk_disable(&priv->clk);
  489. clk_free:
  490. clk_free(&priv->clk);
  491. return ret;
  492. }
  493. int stm32_sdmmc_bind(struct udevice *dev)
  494. {
  495. struct stm32_sdmmc2_plat *plat = dev_get_platdata(dev);
  496. return mmc_bind(dev, &plat->mmc, &plat->cfg);
  497. }
  498. static const struct udevice_id stm32_sdmmc2_ids[] = {
  499. { .compatible = "st,stm32-sdmmc2" },
  500. { }
  501. };
  502. U_BOOT_DRIVER(stm32_sdmmc2) = {
  503. .name = "stm32_sdmmc2",
  504. .id = UCLASS_MMC,
  505. .of_match = stm32_sdmmc2_ids,
  506. .ops = &stm32_sdmmc2_ops,
  507. .probe = stm32_sdmmc2_probe,
  508. .bind = stm32_sdmmc_bind,
  509. .priv_auto_alloc_size = sizeof(struct stm32_sdmmc2_priv),
  510. .platdata_auto_alloc_size = sizeof(struct stm32_sdmmc2_plat),
  511. };