ddr.c 7.2 KB

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  1. /*
  2. * Copyright 2010-2011 Freescale Semiconductor, Inc.
  3. *
  4. * SPDX-License-Identifier: GPL-2.0
  5. */
  6. #include <common.h>
  7. #include <asm/mmu.h>
  8. #include <asm/immap_85xx.h>
  9. #include <asm/processor.h>
  10. #include <fsl_ddr_sdram.h>
  11. #include <fsl_ddr_dimm_params.h>
  12. #include <asm/io.h>
  13. #include <asm/fsl_law.h>
  14. #ifdef CONFIG_SYS_DDR_RAW_TIMING
  15. #if defined(CONFIG_P1020RDB_PROTO) || \
  16. defined(CONFIG_TARGET_P1021RDB) || \
  17. defined(CONFIG_TARGET_P1020UTM)
  18. /* Micron MT41J256M8_187E */
  19. dimm_params_t ddr_raw_timing = {
  20. .n_ranks = 1,
  21. .rank_density = 1073741824u,
  22. .capacity = 1073741824u,
  23. .primary_sdram_width = 32,
  24. .ec_sdram_width = 0,
  25. .registered_dimm = 0,
  26. .mirrored_dimm = 0,
  27. .n_row_addr = 15,
  28. .n_col_addr = 10,
  29. .n_banks_per_sdram_device = 8,
  30. .edc_config = 0,
  31. .burst_lengths_bitmask = 0x0c,
  32. .tckmin_x_ps = 1870,
  33. .caslat_x = 0x1e << 4, /* 5,6,7,8 */
  34. .taa_ps = 13125,
  35. .twr_ps = 15000,
  36. .trcd_ps = 13125,
  37. .trrd_ps = 7500,
  38. .trp_ps = 13125,
  39. .tras_ps = 37500,
  40. .trc_ps = 50625,
  41. .trfc_ps = 160000,
  42. .twtr_ps = 7500,
  43. .trtp_ps = 7500,
  44. .refresh_rate_ps = 7800000,
  45. .tfaw_ps = 37500,
  46. };
  47. #elif defined(CONFIG_TARGET_P2020RDB)
  48. /* Micron MT41J128M16_15E */
  49. dimm_params_t ddr_raw_timing = {
  50. .n_ranks = 1,
  51. .rank_density = 1073741824u,
  52. .capacity = 1073741824u,
  53. .primary_sdram_width = 64,
  54. .ec_sdram_width = 0,
  55. .registered_dimm = 0,
  56. .mirrored_dimm = 0,
  57. .n_row_addr = 14,
  58. .n_col_addr = 10,
  59. .n_banks_per_sdram_device = 8,
  60. .edc_config = 0,
  61. .burst_lengths_bitmask = 0x0c,
  62. .tckmin_x_ps = 1500,
  63. .caslat_x = 0x7e << 4, /* 5,6,7,8,9,10 */
  64. .taa_ps = 13500,
  65. .twr_ps = 15000,
  66. .trcd_ps = 13500,
  67. .trrd_ps = 6000,
  68. .trp_ps = 13500,
  69. .tras_ps = 36000,
  70. .trc_ps = 49500,
  71. .trfc_ps = 160000,
  72. .twtr_ps = 7500,
  73. .trtp_ps = 7500,
  74. .refresh_rate_ps = 7800000,
  75. .tfaw_ps = 30000,
  76. };
  77. #elif (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD))
  78. /* Micron MT41J512M8_187E */
  79. dimm_params_t ddr_raw_timing = {
  80. .n_ranks = 2,
  81. .rank_density = 1073741824u,
  82. .capacity = 2147483648u,
  83. .primary_sdram_width = 32,
  84. .ec_sdram_width = 0,
  85. .registered_dimm = 0,
  86. .mirrored_dimm = 0,
  87. .n_row_addr = 15,
  88. .n_col_addr = 10,
  89. .n_banks_per_sdram_device = 8,
  90. .edc_config = 0,
  91. .burst_lengths_bitmask = 0x0c,
  92. .tckmin_x_ps = 1870,
  93. .caslat_x = 0x1e << 4, /* 5,6,7,8 */
  94. .taa_ps = 13125,
  95. .twr_ps = 15000,
  96. .trcd_ps = 13125,
  97. .trrd_ps = 7500,
  98. .trp_ps = 13125,
  99. .tras_ps = 37500,
  100. .trc_ps = 50625,
  101. .trfc_ps = 160000,
  102. .twtr_ps = 7500,
  103. .trtp_ps = 7500,
  104. .refresh_rate_ps = 7800000,
  105. .tfaw_ps = 37500,
  106. };
  107. #elif defined(CONFIG_TARGET_P1020RDB_PC)
  108. /*
  109. * Samsung K4B2G0846C-HCF8
  110. * The following timing are for "downshift"
  111. * i.e. to use CL9 part as CL7
  112. * otherwise, tAA, tRCD, tRP will be 13500ps
  113. * and tRC will be 49500ps
  114. */
  115. dimm_params_t ddr_raw_timing = {
  116. .n_ranks = 1,
  117. .rank_density = 1073741824u,
  118. .capacity = 1073741824u,
  119. .primary_sdram_width = 32,
  120. .ec_sdram_width = 0,
  121. .registered_dimm = 0,
  122. .mirrored_dimm = 0,
  123. .n_row_addr = 15,
  124. .n_col_addr = 10,
  125. .n_banks_per_sdram_device = 8,
  126. .edc_config = 0,
  127. .burst_lengths_bitmask = 0x0c,
  128. .tckmin_x_ps = 1875,
  129. .caslat_x = 0x1e << 4, /* 5,6,7,8 */
  130. .taa_ps = 13125,
  131. .twr_ps = 15000,
  132. .trcd_ps = 13125,
  133. .trrd_ps = 7500,
  134. .trp_ps = 13125,
  135. .tras_ps = 37500,
  136. .trc_ps = 50625,
  137. .trfc_ps = 160000,
  138. .twtr_ps = 7500,
  139. .trtp_ps = 7500,
  140. .refresh_rate_ps = 7800000,
  141. .tfaw_ps = 37500,
  142. };
  143. #elif defined(CONFIG_TARGET_P1024RDB) || \
  144. defined(CONFIG_TARGET_P1025RDB)
  145. /*
  146. * Samsung K4B2G0846C-HCH9
  147. * The following timing are for "downshift"
  148. * i.e. to use CL9 part as CL7
  149. * otherwise, tAA, tRCD, tRP will be 13500ps
  150. * and tRC will be 49500ps
  151. */
  152. dimm_params_t ddr_raw_timing = {
  153. .n_ranks = 1,
  154. .rank_density = 1073741824u,
  155. .capacity = 1073741824u,
  156. .primary_sdram_width = 32,
  157. .ec_sdram_width = 0,
  158. .registered_dimm = 0,
  159. .mirrored_dimm = 0,
  160. .n_row_addr = 15,
  161. .n_col_addr = 10,
  162. .n_banks_per_sdram_device = 8,
  163. .edc_config = 0,
  164. .burst_lengths_bitmask = 0x0c,
  165. .tckmin_x_ps = 1500,
  166. .caslat_x = 0x3e << 4, /* 5,6,7,8,9 */
  167. .taa_ps = 13125,
  168. .twr_ps = 15000,
  169. .trcd_ps = 13125,
  170. .trrd_ps = 6000,
  171. .trp_ps = 13125,
  172. .tras_ps = 36000,
  173. .trc_ps = 49125,
  174. .trfc_ps = 160000,
  175. .twtr_ps = 7500,
  176. .trtp_ps = 7500,
  177. .refresh_rate_ps = 7800000,
  178. .tfaw_ps = 30000,
  179. };
  180. #else
  181. #error Missing raw timing data for this board
  182. #endif
  183. int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
  184. unsigned int controller_number,
  185. unsigned int dimm_number)
  186. {
  187. const char dimm_model[] = "Fixed DDR on board";
  188. if ((controller_number == 0) && (dimm_number == 0)) {
  189. memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
  190. memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
  191. memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
  192. }
  193. return 0;
  194. }
  195. #endif /* CONFIG_SYS_DDR_RAW_TIMING */
  196. #ifdef CONFIG_SYS_DDR_CS0_BNDS
  197. /* Fixed sdram init -- doesn't use serial presence detect. */
  198. phys_size_t fixed_sdram(void)
  199. {
  200. sys_info_t sysinfo;
  201. char buf[32];
  202. size_t ddr_size;
  203. fsl_ddr_cfg_regs_t ddr_cfg_regs = {
  204. .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
  205. .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
  206. .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
  207. #if CONFIG_CHIP_SELECTS_PER_CTRL > 1
  208. .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
  209. .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
  210. .cs[1].config_2 = CONFIG_SYS_DDR_CS1_CONFIG_2,
  211. #endif
  212. .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3,
  213. .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0,
  214. .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1,
  215. .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2,
  216. .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
  217. .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
  218. .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1,
  219. .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2,
  220. .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
  221. .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL,
  222. .ddr_data_init = CONFIG_SYS_DDR_DATA_INIT,
  223. .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL,
  224. .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
  225. .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
  226. .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
  227. .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
  228. .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
  229. .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
  230. .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
  231. .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
  232. .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
  233. };
  234. get_sys_info(&sysinfo);
  235. printf("Configuring DDR for %s MT/s data rate\n",
  236. strmhz(buf, sysinfo.freq_ddrbus));
  237. ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
  238. fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
  239. if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
  240. ddr_size, LAW_TRGT_IF_DDR_1) < 0) {
  241. printf("ERROR setting Local Access Windows for DDR\n");
  242. return 0;
  243. };
  244. return ddr_size;
  245. }
  246. #endif
  247. void fsl_ddr_board_options(memctl_options_t *popts,
  248. dimm_params_t *pdimm,
  249. unsigned int ctrl_num)
  250. {
  251. int i;
  252. popts->clk_adjust = 6;
  253. popts->cpo_override = 0x1f;
  254. popts->write_data_delay = 2;
  255. popts->half_strength_driver_enable = 1;
  256. /* Write leveling override */
  257. popts->wrlvl_en = 1;
  258. popts->wrlvl_override = 1;
  259. popts->wrlvl_sample = 0xf;
  260. popts->wrlvl_start = 0x8;
  261. popts->trwt_override = 1;
  262. popts->trwt = 0;
  263. if (pdimm->primary_sdram_width == 64)
  264. popts->data_bus_width = 0;
  265. else if (pdimm->primary_sdram_width == 32)
  266. popts->data_bus_width = 1;
  267. else
  268. printf("Error in DDR bus width configuration!\n");
  269. for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
  270. popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
  271. popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
  272. }
  273. }