mvpp2.c 117 KB

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  1. /*
  2. * Driver for Marvell PPv2 network controller for Armada 375 SoC.
  3. *
  4. * Copyright (C) 2014 Marvell
  5. *
  6. * Marcin Wojtas <mw@semihalf.com>
  7. *
  8. * U-Boot version:
  9. * Copyright (C) 2016 Stefan Roese <sr@denx.de>
  10. *
  11. * This file is licensed under the terms of the GNU General Public
  12. * License version 2. This program is licensed "as is" without any
  13. * warranty of any kind, whether express or implied.
  14. */
  15. #include <common.h>
  16. #include <dm.h>
  17. #include <dm/device-internal.h>
  18. #include <dm/lists.h>
  19. #include <net.h>
  20. #include <netdev.h>
  21. #include <config.h>
  22. #include <malloc.h>
  23. #include <asm/io.h>
  24. #include <linux/errno.h>
  25. #include <phy.h>
  26. #include <miiphy.h>
  27. #include <watchdog.h>
  28. #include <asm/arch/cpu.h>
  29. #include <asm/arch/soc.h>
  30. #include <linux/compat.h>
  31. #include <linux/mbus.h>
  32. DECLARE_GLOBAL_DATA_PTR;
  33. /* Some linux -> U-Boot compatibility stuff */
  34. #define netdev_err(dev, fmt, args...) \
  35. printf(fmt, ##args)
  36. #define netdev_warn(dev, fmt, args...) \
  37. printf(fmt, ##args)
  38. #define netdev_info(dev, fmt, args...) \
  39. printf(fmt, ##args)
  40. #define netdev_dbg(dev, fmt, args...) \
  41. printf(fmt, ##args)
  42. #define ETH_ALEN 6 /* Octets in one ethernet addr */
  43. #define __verify_pcpu_ptr(ptr) \
  44. do { \
  45. const void __percpu *__vpp_verify = (typeof((ptr) + 0))NULL; \
  46. (void)__vpp_verify; \
  47. } while (0)
  48. #define VERIFY_PERCPU_PTR(__p) \
  49. ({ \
  50. __verify_pcpu_ptr(__p); \
  51. (typeof(*(__p)) __kernel __force *)(__p); \
  52. })
  53. #define per_cpu_ptr(ptr, cpu) ({ (void)(cpu); VERIFY_PERCPU_PTR(ptr); })
  54. #define smp_processor_id() 0
  55. #define num_present_cpus() 1
  56. #define for_each_present_cpu(cpu) \
  57. for ((cpu) = 0; (cpu) < 1; (cpu)++)
  58. #define NET_SKB_PAD max(32, MVPP2_CPU_D_CACHE_LINE_SIZE)
  59. #define CONFIG_NR_CPUS 1
  60. #define ETH_HLEN ETHER_HDR_SIZE /* Total octets in header */
  61. /* 2(HW hdr) 14(MAC hdr) 4(CRC) 32(extra for cache prefetch) */
  62. #define WRAP (2 + ETH_HLEN + 4 + 32)
  63. #define MTU 1500
  64. #define RX_BUFFER_SIZE (ALIGN(MTU + WRAP, ARCH_DMA_MINALIGN))
  65. #define MVPP2_SMI_TIMEOUT 10000
  66. /* RX Fifo Registers */
  67. #define MVPP2_RX_DATA_FIFO_SIZE_REG(port) (0x00 + 4 * (port))
  68. #define MVPP2_RX_ATTR_FIFO_SIZE_REG(port) (0x20 + 4 * (port))
  69. #define MVPP2_RX_MIN_PKT_SIZE_REG 0x60
  70. #define MVPP2_RX_FIFO_INIT_REG 0x64
  71. /* RX DMA Top Registers */
  72. #define MVPP2_RX_CTRL_REG(port) (0x140 + 4 * (port))
  73. #define MVPP2_RX_LOW_LATENCY_PKT_SIZE(s) (((s) & 0xfff) << 16)
  74. #define MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK BIT(31)
  75. #define MVPP2_POOL_BUF_SIZE_REG(pool) (0x180 + 4 * (pool))
  76. #define MVPP2_POOL_BUF_SIZE_OFFSET 5
  77. #define MVPP2_RXQ_CONFIG_REG(rxq) (0x800 + 4 * (rxq))
  78. #define MVPP2_SNOOP_PKT_SIZE_MASK 0x1ff
  79. #define MVPP2_SNOOP_BUF_HDR_MASK BIT(9)
  80. #define MVPP2_RXQ_POOL_SHORT_OFFS 20
  81. #define MVPP2_RXQ_POOL_SHORT_MASK 0x700000
  82. #define MVPP2_RXQ_POOL_LONG_OFFS 24
  83. #define MVPP2_RXQ_POOL_LONG_MASK 0x7000000
  84. #define MVPP2_RXQ_PACKET_OFFSET_OFFS 28
  85. #define MVPP2_RXQ_PACKET_OFFSET_MASK 0x70000000
  86. #define MVPP2_RXQ_DISABLE_MASK BIT(31)
  87. /* Parser Registers */
  88. #define MVPP2_PRS_INIT_LOOKUP_REG 0x1000
  89. #define MVPP2_PRS_PORT_LU_MAX 0xf
  90. #define MVPP2_PRS_PORT_LU_MASK(port) (0xff << ((port) * 4))
  91. #define MVPP2_PRS_PORT_LU_VAL(port, val) ((val) << ((port) * 4))
  92. #define MVPP2_PRS_INIT_OFFS_REG(port) (0x1004 + ((port) & 4))
  93. #define MVPP2_PRS_INIT_OFF_MASK(port) (0x3f << (((port) % 4) * 8))
  94. #define MVPP2_PRS_INIT_OFF_VAL(port, val) ((val) << (((port) % 4) * 8))
  95. #define MVPP2_PRS_MAX_LOOP_REG(port) (0x100c + ((port) & 4))
  96. #define MVPP2_PRS_MAX_LOOP_MASK(port) (0xff << (((port) % 4) * 8))
  97. #define MVPP2_PRS_MAX_LOOP_VAL(port, val) ((val) << (((port) % 4) * 8))
  98. #define MVPP2_PRS_TCAM_IDX_REG 0x1100
  99. #define MVPP2_PRS_TCAM_DATA_REG(idx) (0x1104 + (idx) * 4)
  100. #define MVPP2_PRS_TCAM_INV_MASK BIT(31)
  101. #define MVPP2_PRS_SRAM_IDX_REG 0x1200
  102. #define MVPP2_PRS_SRAM_DATA_REG(idx) (0x1204 + (idx) * 4)
  103. #define MVPP2_PRS_TCAM_CTRL_REG 0x1230
  104. #define MVPP2_PRS_TCAM_EN_MASK BIT(0)
  105. /* Classifier Registers */
  106. #define MVPP2_CLS_MODE_REG 0x1800
  107. #define MVPP2_CLS_MODE_ACTIVE_MASK BIT(0)
  108. #define MVPP2_CLS_PORT_WAY_REG 0x1810
  109. #define MVPP2_CLS_PORT_WAY_MASK(port) (1 << (port))
  110. #define MVPP2_CLS_LKP_INDEX_REG 0x1814
  111. #define MVPP2_CLS_LKP_INDEX_WAY_OFFS 6
  112. #define MVPP2_CLS_LKP_TBL_REG 0x1818
  113. #define MVPP2_CLS_LKP_TBL_RXQ_MASK 0xff
  114. #define MVPP2_CLS_LKP_TBL_LOOKUP_EN_MASK BIT(25)
  115. #define MVPP2_CLS_FLOW_INDEX_REG 0x1820
  116. #define MVPP2_CLS_FLOW_TBL0_REG 0x1824
  117. #define MVPP2_CLS_FLOW_TBL1_REG 0x1828
  118. #define MVPP2_CLS_FLOW_TBL2_REG 0x182c
  119. #define MVPP2_CLS_OVERSIZE_RXQ_LOW_REG(port) (0x1980 + ((port) * 4))
  120. #define MVPP2_CLS_OVERSIZE_RXQ_LOW_BITS 3
  121. #define MVPP2_CLS_OVERSIZE_RXQ_LOW_MASK 0x7
  122. #define MVPP2_CLS_SWFWD_P2HQ_REG(port) (0x19b0 + ((port) * 4))
  123. #define MVPP2_CLS_SWFWD_PCTRL_REG 0x19d0
  124. #define MVPP2_CLS_SWFWD_PCTRL_MASK(port) (1 << (port))
  125. /* Descriptor Manager Top Registers */
  126. #define MVPP2_RXQ_NUM_REG 0x2040
  127. #define MVPP2_RXQ_DESC_ADDR_REG 0x2044
  128. #define MVPP2_RXQ_DESC_SIZE_REG 0x2048
  129. #define MVPP2_RXQ_DESC_SIZE_MASK 0x3ff0
  130. #define MVPP2_RXQ_STATUS_UPDATE_REG(rxq) (0x3000 + 4 * (rxq))
  131. #define MVPP2_RXQ_NUM_PROCESSED_OFFSET 0
  132. #define MVPP2_RXQ_NUM_NEW_OFFSET 16
  133. #define MVPP2_RXQ_STATUS_REG(rxq) (0x3400 + 4 * (rxq))
  134. #define MVPP2_RXQ_OCCUPIED_MASK 0x3fff
  135. #define MVPP2_RXQ_NON_OCCUPIED_OFFSET 16
  136. #define MVPP2_RXQ_NON_OCCUPIED_MASK 0x3fff0000
  137. #define MVPP2_RXQ_THRESH_REG 0x204c
  138. #define MVPP2_OCCUPIED_THRESH_OFFSET 0
  139. #define MVPP2_OCCUPIED_THRESH_MASK 0x3fff
  140. #define MVPP2_RXQ_INDEX_REG 0x2050
  141. #define MVPP2_TXQ_NUM_REG 0x2080
  142. #define MVPP2_TXQ_DESC_ADDR_REG 0x2084
  143. #define MVPP2_TXQ_DESC_SIZE_REG 0x2088
  144. #define MVPP2_TXQ_DESC_SIZE_MASK 0x3ff0
  145. #define MVPP2_AGGR_TXQ_UPDATE_REG 0x2090
  146. #define MVPP2_TXQ_THRESH_REG 0x2094
  147. #define MVPP2_TRANSMITTED_THRESH_OFFSET 16
  148. #define MVPP2_TRANSMITTED_THRESH_MASK 0x3fff0000
  149. #define MVPP2_TXQ_INDEX_REG 0x2098
  150. #define MVPP2_TXQ_PREF_BUF_REG 0x209c
  151. #define MVPP2_PREF_BUF_PTR(desc) ((desc) & 0xfff)
  152. #define MVPP2_PREF_BUF_SIZE_4 (BIT(12) | BIT(13))
  153. #define MVPP2_PREF_BUF_SIZE_16 (BIT(12) | BIT(14))
  154. #define MVPP2_PREF_BUF_THRESH(val) ((val) << 17)
  155. #define MVPP2_TXQ_DRAIN_EN_MASK BIT(31)
  156. #define MVPP2_TXQ_PENDING_REG 0x20a0
  157. #define MVPP2_TXQ_PENDING_MASK 0x3fff
  158. #define MVPP2_TXQ_INT_STATUS_REG 0x20a4
  159. #define MVPP2_TXQ_SENT_REG(txq) (0x3c00 + 4 * (txq))
  160. #define MVPP2_TRANSMITTED_COUNT_OFFSET 16
  161. #define MVPP2_TRANSMITTED_COUNT_MASK 0x3fff0000
  162. #define MVPP2_TXQ_RSVD_REQ_REG 0x20b0
  163. #define MVPP2_TXQ_RSVD_REQ_Q_OFFSET 16
  164. #define MVPP2_TXQ_RSVD_RSLT_REG 0x20b4
  165. #define MVPP2_TXQ_RSVD_RSLT_MASK 0x3fff
  166. #define MVPP2_TXQ_RSVD_CLR_REG 0x20b8
  167. #define MVPP2_TXQ_RSVD_CLR_OFFSET 16
  168. #define MVPP2_AGGR_TXQ_DESC_ADDR_REG(cpu) (0x2100 + 4 * (cpu))
  169. #define MVPP2_AGGR_TXQ_DESC_SIZE_REG(cpu) (0x2140 + 4 * (cpu))
  170. #define MVPP2_AGGR_TXQ_DESC_SIZE_MASK 0x3ff0
  171. #define MVPP2_AGGR_TXQ_STATUS_REG(cpu) (0x2180 + 4 * (cpu))
  172. #define MVPP2_AGGR_TXQ_PENDING_MASK 0x3fff
  173. #define MVPP2_AGGR_TXQ_INDEX_REG(cpu) (0x21c0 + 4 * (cpu))
  174. /* MBUS bridge registers */
  175. #define MVPP2_WIN_BASE(w) (0x4000 + ((w) << 2))
  176. #define MVPP2_WIN_SIZE(w) (0x4020 + ((w) << 2))
  177. #define MVPP2_WIN_REMAP(w) (0x4040 + ((w) << 2))
  178. #define MVPP2_BASE_ADDR_ENABLE 0x4060
  179. /* Interrupt Cause and Mask registers */
  180. #define MVPP2_ISR_RX_THRESHOLD_REG(rxq) (0x5200 + 4 * (rxq))
  181. #define MVPP2_ISR_RXQ_GROUP_REG(rxq) (0x5400 + 4 * (rxq))
  182. #define MVPP2_ISR_ENABLE_REG(port) (0x5420 + 4 * (port))
  183. #define MVPP2_ISR_ENABLE_INTERRUPT(mask) ((mask) & 0xffff)
  184. #define MVPP2_ISR_DISABLE_INTERRUPT(mask) (((mask) << 16) & 0xffff0000)
  185. #define MVPP2_ISR_RX_TX_CAUSE_REG(port) (0x5480 + 4 * (port))
  186. #define MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK 0xffff
  187. #define MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK 0xff0000
  188. #define MVPP2_CAUSE_RX_FIFO_OVERRUN_MASK BIT(24)
  189. #define MVPP2_CAUSE_FCS_ERR_MASK BIT(25)
  190. #define MVPP2_CAUSE_TX_FIFO_UNDERRUN_MASK BIT(26)
  191. #define MVPP2_CAUSE_TX_EXCEPTION_SUM_MASK BIT(29)
  192. #define MVPP2_CAUSE_RX_EXCEPTION_SUM_MASK BIT(30)
  193. #define MVPP2_CAUSE_MISC_SUM_MASK BIT(31)
  194. #define MVPP2_ISR_RX_TX_MASK_REG(port) (0x54a0 + 4 * (port))
  195. #define MVPP2_ISR_PON_RX_TX_MASK_REG 0x54bc
  196. #define MVPP2_PON_CAUSE_RXQ_OCCUP_DESC_ALL_MASK 0xffff
  197. #define MVPP2_PON_CAUSE_TXP_OCCUP_DESC_ALL_MASK 0x3fc00000
  198. #define MVPP2_PON_CAUSE_MISC_SUM_MASK BIT(31)
  199. #define MVPP2_ISR_MISC_CAUSE_REG 0x55b0
  200. /* Buffer Manager registers */
  201. #define MVPP2_BM_POOL_BASE_REG(pool) (0x6000 + ((pool) * 4))
  202. #define MVPP2_BM_POOL_BASE_ADDR_MASK 0xfffff80
  203. #define MVPP2_BM_POOL_SIZE_REG(pool) (0x6040 + ((pool) * 4))
  204. #define MVPP2_BM_POOL_SIZE_MASK 0xfff0
  205. #define MVPP2_BM_POOL_READ_PTR_REG(pool) (0x6080 + ((pool) * 4))
  206. #define MVPP2_BM_POOL_GET_READ_PTR_MASK 0xfff0
  207. #define MVPP2_BM_POOL_PTRS_NUM_REG(pool) (0x60c0 + ((pool) * 4))
  208. #define MVPP2_BM_POOL_PTRS_NUM_MASK 0xfff0
  209. #define MVPP2_BM_BPPI_READ_PTR_REG(pool) (0x6100 + ((pool) * 4))
  210. #define MVPP2_BM_BPPI_PTRS_NUM_REG(pool) (0x6140 + ((pool) * 4))
  211. #define MVPP2_BM_BPPI_PTR_NUM_MASK 0x7ff
  212. #define MVPP2_BM_BPPI_PREFETCH_FULL_MASK BIT(16)
  213. #define MVPP2_BM_POOL_CTRL_REG(pool) (0x6200 + ((pool) * 4))
  214. #define MVPP2_BM_START_MASK BIT(0)
  215. #define MVPP2_BM_STOP_MASK BIT(1)
  216. #define MVPP2_BM_STATE_MASK BIT(4)
  217. #define MVPP2_BM_LOW_THRESH_OFFS 8
  218. #define MVPP2_BM_LOW_THRESH_MASK 0x7f00
  219. #define MVPP2_BM_LOW_THRESH_VALUE(val) ((val) << \
  220. MVPP2_BM_LOW_THRESH_OFFS)
  221. #define MVPP2_BM_HIGH_THRESH_OFFS 16
  222. #define MVPP2_BM_HIGH_THRESH_MASK 0x7f0000
  223. #define MVPP2_BM_HIGH_THRESH_VALUE(val) ((val) << \
  224. MVPP2_BM_HIGH_THRESH_OFFS)
  225. #define MVPP2_BM_INTR_CAUSE_REG(pool) (0x6240 + ((pool) * 4))
  226. #define MVPP2_BM_RELEASED_DELAY_MASK BIT(0)
  227. #define MVPP2_BM_ALLOC_FAILED_MASK BIT(1)
  228. #define MVPP2_BM_BPPE_EMPTY_MASK BIT(2)
  229. #define MVPP2_BM_BPPE_FULL_MASK BIT(3)
  230. #define MVPP2_BM_AVAILABLE_BP_LOW_MASK BIT(4)
  231. #define MVPP2_BM_INTR_MASK_REG(pool) (0x6280 + ((pool) * 4))
  232. #define MVPP2_BM_PHY_ALLOC_REG(pool) (0x6400 + ((pool) * 4))
  233. #define MVPP2_BM_PHY_ALLOC_GRNTD_MASK BIT(0)
  234. #define MVPP2_BM_VIRT_ALLOC_REG 0x6440
  235. #define MVPP2_BM_PHY_RLS_REG(pool) (0x6480 + ((pool) * 4))
  236. #define MVPP2_BM_PHY_RLS_MC_BUFF_MASK BIT(0)
  237. #define MVPP2_BM_PHY_RLS_PRIO_EN_MASK BIT(1)
  238. #define MVPP2_BM_PHY_RLS_GRNTD_MASK BIT(2)
  239. #define MVPP2_BM_VIRT_RLS_REG 0x64c0
  240. #define MVPP2_BM_MC_RLS_REG 0x64c4
  241. #define MVPP2_BM_MC_ID_MASK 0xfff
  242. #define MVPP2_BM_FORCE_RELEASE_MASK BIT(12)
  243. /* TX Scheduler registers */
  244. #define MVPP2_TXP_SCHED_PORT_INDEX_REG 0x8000
  245. #define MVPP2_TXP_SCHED_Q_CMD_REG 0x8004
  246. #define MVPP2_TXP_SCHED_ENQ_MASK 0xff
  247. #define MVPP2_TXP_SCHED_DISQ_OFFSET 8
  248. #define MVPP2_TXP_SCHED_CMD_1_REG 0x8010
  249. #define MVPP2_TXP_SCHED_PERIOD_REG 0x8018
  250. #define MVPP2_TXP_SCHED_MTU_REG 0x801c
  251. #define MVPP2_TXP_MTU_MAX 0x7FFFF
  252. #define MVPP2_TXP_SCHED_REFILL_REG 0x8020
  253. #define MVPP2_TXP_REFILL_TOKENS_ALL_MASK 0x7ffff
  254. #define MVPP2_TXP_REFILL_PERIOD_ALL_MASK 0x3ff00000
  255. #define MVPP2_TXP_REFILL_PERIOD_MASK(v) ((v) << 20)
  256. #define MVPP2_TXP_SCHED_TOKEN_SIZE_REG 0x8024
  257. #define MVPP2_TXP_TOKEN_SIZE_MAX 0xffffffff
  258. #define MVPP2_TXQ_SCHED_REFILL_REG(q) (0x8040 + ((q) << 2))
  259. #define MVPP2_TXQ_REFILL_TOKENS_ALL_MASK 0x7ffff
  260. #define MVPP2_TXQ_REFILL_PERIOD_ALL_MASK 0x3ff00000
  261. #define MVPP2_TXQ_REFILL_PERIOD_MASK(v) ((v) << 20)
  262. #define MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(q) (0x8060 + ((q) << 2))
  263. #define MVPP2_TXQ_TOKEN_SIZE_MAX 0x7fffffff
  264. #define MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(q) (0x8080 + ((q) << 2))
  265. #define MVPP2_TXQ_TOKEN_CNTR_MAX 0xffffffff
  266. /* TX general registers */
  267. #define MVPP2_TX_SNOOP_REG 0x8800
  268. #define MVPP2_TX_PORT_FLUSH_REG 0x8810
  269. #define MVPP2_TX_PORT_FLUSH_MASK(port) (1 << (port))
  270. /* LMS registers */
  271. #define MVPP2_SRC_ADDR_MIDDLE 0x24
  272. #define MVPP2_SRC_ADDR_HIGH 0x28
  273. #define MVPP2_PHY_AN_CFG0_REG 0x34
  274. #define MVPP2_PHY_AN_STOP_SMI0_MASK BIT(7)
  275. #define MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG 0x305c
  276. #define MVPP2_EXT_GLOBAL_CTRL_DEFAULT 0x27
  277. /* Per-port registers */
  278. #define MVPP2_GMAC_CTRL_0_REG 0x0
  279. #define MVPP2_GMAC_PORT_EN_MASK BIT(0)
  280. #define MVPP2_GMAC_MAX_RX_SIZE_OFFS 2
  281. #define MVPP2_GMAC_MAX_RX_SIZE_MASK 0x7ffc
  282. #define MVPP2_GMAC_MIB_CNTR_EN_MASK BIT(15)
  283. #define MVPP2_GMAC_CTRL_1_REG 0x4
  284. #define MVPP2_GMAC_PERIODIC_XON_EN_MASK BIT(1)
  285. #define MVPP2_GMAC_GMII_LB_EN_MASK BIT(5)
  286. #define MVPP2_GMAC_PCS_LB_EN_BIT 6
  287. #define MVPP2_GMAC_PCS_LB_EN_MASK BIT(6)
  288. #define MVPP2_GMAC_SA_LOW_OFFS 7
  289. #define MVPP2_GMAC_CTRL_2_REG 0x8
  290. #define MVPP2_GMAC_INBAND_AN_MASK BIT(0)
  291. #define MVPP2_GMAC_PCS_ENABLE_MASK BIT(3)
  292. #define MVPP2_GMAC_PORT_RGMII_MASK BIT(4)
  293. #define MVPP2_GMAC_PORT_RESET_MASK BIT(6)
  294. #define MVPP2_GMAC_AUTONEG_CONFIG 0xc
  295. #define MVPP2_GMAC_FORCE_LINK_DOWN BIT(0)
  296. #define MVPP2_GMAC_FORCE_LINK_PASS BIT(1)
  297. #define MVPP2_GMAC_CONFIG_MII_SPEED BIT(5)
  298. #define MVPP2_GMAC_CONFIG_GMII_SPEED BIT(6)
  299. #define MVPP2_GMAC_AN_SPEED_EN BIT(7)
  300. #define MVPP2_GMAC_FC_ADV_EN BIT(9)
  301. #define MVPP2_GMAC_CONFIG_FULL_DUPLEX BIT(12)
  302. #define MVPP2_GMAC_AN_DUPLEX_EN BIT(13)
  303. #define MVPP2_GMAC_PORT_FIFO_CFG_1_REG 0x1c
  304. #define MVPP2_GMAC_TX_FIFO_MIN_TH_OFFS 6
  305. #define MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK 0x1fc0
  306. #define MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(v) (((v) << 6) & \
  307. MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK)
  308. #define MVPP2_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff
  309. /* Descriptor ring Macros */
  310. #define MVPP2_QUEUE_NEXT_DESC(q, index) \
  311. (((index) < (q)->last_desc) ? ((index) + 1) : 0)
  312. /* SMI: 0xc0054 -> offset 0x54 to lms_base */
  313. #define MVPP2_SMI 0x0054
  314. #define MVPP2_PHY_REG_MASK 0x1f
  315. /* SMI register fields */
  316. #define MVPP2_SMI_DATA_OFFS 0 /* Data */
  317. #define MVPP2_SMI_DATA_MASK (0xffff << MVPP2_SMI_DATA_OFFS)
  318. #define MVPP2_SMI_DEV_ADDR_OFFS 16 /* PHY device address */
  319. #define MVPP2_SMI_REG_ADDR_OFFS 21 /* PHY device reg addr*/
  320. #define MVPP2_SMI_OPCODE_OFFS 26 /* Write/Read opcode */
  321. #define MVPP2_SMI_OPCODE_READ (1 << MVPP2_SMI_OPCODE_OFFS)
  322. #define MVPP2_SMI_READ_VALID (1 << 27) /* Read Valid */
  323. #define MVPP2_SMI_BUSY (1 << 28) /* Busy */
  324. #define MVPP2_PHY_ADDR_MASK 0x1f
  325. #define MVPP2_PHY_REG_MASK 0x1f
  326. /* Various constants */
  327. /* Coalescing */
  328. #define MVPP2_TXDONE_COAL_PKTS_THRESH 15
  329. #define MVPP2_TXDONE_HRTIMER_PERIOD_NS 1000000UL
  330. #define MVPP2_RX_COAL_PKTS 32
  331. #define MVPP2_RX_COAL_USEC 100
  332. /* The two bytes Marvell header. Either contains a special value used
  333. * by Marvell switches when a specific hardware mode is enabled (not
  334. * supported by this driver) or is filled automatically by zeroes on
  335. * the RX side. Those two bytes being at the front of the Ethernet
  336. * header, they allow to have the IP header aligned on a 4 bytes
  337. * boundary automatically: the hardware skips those two bytes on its
  338. * own.
  339. */
  340. #define MVPP2_MH_SIZE 2
  341. #define MVPP2_ETH_TYPE_LEN 2
  342. #define MVPP2_PPPOE_HDR_SIZE 8
  343. #define MVPP2_VLAN_TAG_LEN 4
  344. /* Lbtd 802.3 type */
  345. #define MVPP2_IP_LBDT_TYPE 0xfffa
  346. #define MVPP2_CPU_D_CACHE_LINE_SIZE 32
  347. #define MVPP2_TX_CSUM_MAX_SIZE 9800
  348. /* Timeout constants */
  349. #define MVPP2_TX_DISABLE_TIMEOUT_MSEC 1000
  350. #define MVPP2_TX_PENDING_TIMEOUT_MSEC 1000
  351. #define MVPP2_TX_MTU_MAX 0x7ffff
  352. /* Maximum number of T-CONTs of PON port */
  353. #define MVPP2_MAX_TCONT 16
  354. /* Maximum number of supported ports */
  355. #define MVPP2_MAX_PORTS 4
  356. /* Maximum number of TXQs used by single port */
  357. #define MVPP2_MAX_TXQ 8
  358. /* Maximum number of RXQs used by single port */
  359. #define MVPP2_MAX_RXQ 8
  360. /* Default number of TXQs in use */
  361. #define MVPP2_DEFAULT_TXQ 1
  362. /* Dfault number of RXQs in use */
  363. #define MVPP2_DEFAULT_RXQ 1
  364. #define CONFIG_MV_ETH_RXQ 8 /* increment by 8 */
  365. /* Total number of RXQs available to all ports */
  366. #define MVPP2_RXQ_TOTAL_NUM (MVPP2_MAX_PORTS * MVPP2_MAX_RXQ)
  367. /* Max number of Rx descriptors */
  368. #define MVPP2_MAX_RXD 16
  369. /* Max number of Tx descriptors */
  370. #define MVPP2_MAX_TXD 16
  371. /* Amount of Tx descriptors that can be reserved at once by CPU */
  372. #define MVPP2_CPU_DESC_CHUNK 64
  373. /* Max number of Tx descriptors in each aggregated queue */
  374. #define MVPP2_AGGR_TXQ_SIZE 256
  375. /* Descriptor aligned size */
  376. #define MVPP2_DESC_ALIGNED_SIZE 32
  377. /* Descriptor alignment mask */
  378. #define MVPP2_TX_DESC_ALIGN (MVPP2_DESC_ALIGNED_SIZE - 1)
  379. /* RX FIFO constants */
  380. #define MVPP2_RX_FIFO_PORT_DATA_SIZE 0x2000
  381. #define MVPP2_RX_FIFO_PORT_ATTR_SIZE 0x80
  382. #define MVPP2_RX_FIFO_PORT_MIN_PKT 0x80
  383. /* RX buffer constants */
  384. #define MVPP2_SKB_SHINFO_SIZE \
  385. 0
  386. #define MVPP2_RX_PKT_SIZE(mtu) \
  387. ALIGN((mtu) + MVPP2_MH_SIZE + MVPP2_VLAN_TAG_LEN + \
  388. ETH_HLEN + ETH_FCS_LEN, MVPP2_CPU_D_CACHE_LINE_SIZE)
  389. #define MVPP2_RX_BUF_SIZE(pkt_size) ((pkt_size) + NET_SKB_PAD)
  390. #define MVPP2_RX_TOTAL_SIZE(buf_size) ((buf_size) + MVPP2_SKB_SHINFO_SIZE)
  391. #define MVPP2_RX_MAX_PKT_SIZE(total_size) \
  392. ((total_size) - NET_SKB_PAD - MVPP2_SKB_SHINFO_SIZE)
  393. #define MVPP2_BIT_TO_BYTE(bit) ((bit) / 8)
  394. /* IPv6 max L3 address size */
  395. #define MVPP2_MAX_L3_ADDR_SIZE 16
  396. /* Port flags */
  397. #define MVPP2_F_LOOPBACK BIT(0)
  398. /* Marvell tag types */
  399. enum mvpp2_tag_type {
  400. MVPP2_TAG_TYPE_NONE = 0,
  401. MVPP2_TAG_TYPE_MH = 1,
  402. MVPP2_TAG_TYPE_DSA = 2,
  403. MVPP2_TAG_TYPE_EDSA = 3,
  404. MVPP2_TAG_TYPE_VLAN = 4,
  405. MVPP2_TAG_TYPE_LAST = 5
  406. };
  407. /* Parser constants */
  408. #define MVPP2_PRS_TCAM_SRAM_SIZE 256
  409. #define MVPP2_PRS_TCAM_WORDS 6
  410. #define MVPP2_PRS_SRAM_WORDS 4
  411. #define MVPP2_PRS_FLOW_ID_SIZE 64
  412. #define MVPP2_PRS_FLOW_ID_MASK 0x3f
  413. #define MVPP2_PRS_TCAM_ENTRY_INVALID 1
  414. #define MVPP2_PRS_TCAM_DSA_TAGGED_BIT BIT(5)
  415. #define MVPP2_PRS_IPV4_HEAD 0x40
  416. #define MVPP2_PRS_IPV4_HEAD_MASK 0xf0
  417. #define MVPP2_PRS_IPV4_MC 0xe0
  418. #define MVPP2_PRS_IPV4_MC_MASK 0xf0
  419. #define MVPP2_PRS_IPV4_BC_MASK 0xff
  420. #define MVPP2_PRS_IPV4_IHL 0x5
  421. #define MVPP2_PRS_IPV4_IHL_MASK 0xf
  422. #define MVPP2_PRS_IPV6_MC 0xff
  423. #define MVPP2_PRS_IPV6_MC_MASK 0xff
  424. #define MVPP2_PRS_IPV6_HOP_MASK 0xff
  425. #define MVPP2_PRS_TCAM_PROTO_MASK 0xff
  426. #define MVPP2_PRS_TCAM_PROTO_MASK_L 0x3f
  427. #define MVPP2_PRS_DBL_VLANS_MAX 100
  428. /* Tcam structure:
  429. * - lookup ID - 4 bits
  430. * - port ID - 1 byte
  431. * - additional information - 1 byte
  432. * - header data - 8 bytes
  433. * The fields are represented by MVPP2_PRS_TCAM_DATA_REG(5)->(0).
  434. */
  435. #define MVPP2_PRS_AI_BITS 8
  436. #define MVPP2_PRS_PORT_MASK 0xff
  437. #define MVPP2_PRS_LU_MASK 0xf
  438. #define MVPP2_PRS_TCAM_DATA_BYTE(offs) \
  439. (((offs) - ((offs) % 2)) * 2 + ((offs) % 2))
  440. #define MVPP2_PRS_TCAM_DATA_BYTE_EN(offs) \
  441. (((offs) * 2) - ((offs) % 2) + 2)
  442. #define MVPP2_PRS_TCAM_AI_BYTE 16
  443. #define MVPP2_PRS_TCAM_PORT_BYTE 17
  444. #define MVPP2_PRS_TCAM_LU_BYTE 20
  445. #define MVPP2_PRS_TCAM_EN_OFFS(offs) ((offs) + 2)
  446. #define MVPP2_PRS_TCAM_INV_WORD 5
  447. /* Tcam entries ID */
  448. #define MVPP2_PE_DROP_ALL 0
  449. #define MVPP2_PE_FIRST_FREE_TID 1
  450. #define MVPP2_PE_LAST_FREE_TID (MVPP2_PRS_TCAM_SRAM_SIZE - 31)
  451. #define MVPP2_PE_IP6_EXT_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 30)
  452. #define MVPP2_PE_MAC_MC_IP6 (MVPP2_PRS_TCAM_SRAM_SIZE - 29)
  453. #define MVPP2_PE_IP6_ADDR_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 28)
  454. #define MVPP2_PE_IP4_ADDR_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 27)
  455. #define MVPP2_PE_LAST_DEFAULT_FLOW (MVPP2_PRS_TCAM_SRAM_SIZE - 26)
  456. #define MVPP2_PE_FIRST_DEFAULT_FLOW (MVPP2_PRS_TCAM_SRAM_SIZE - 19)
  457. #define MVPP2_PE_EDSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 18)
  458. #define MVPP2_PE_EDSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 17)
  459. #define MVPP2_PE_DSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 16)
  460. #define MVPP2_PE_DSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 15)
  461. #define MVPP2_PE_ETYPE_EDSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 14)
  462. #define MVPP2_PE_ETYPE_EDSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 13)
  463. #define MVPP2_PE_ETYPE_DSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 12)
  464. #define MVPP2_PE_ETYPE_DSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 11)
  465. #define MVPP2_PE_MH_DEFAULT (MVPP2_PRS_TCAM_SRAM_SIZE - 10)
  466. #define MVPP2_PE_DSA_DEFAULT (MVPP2_PRS_TCAM_SRAM_SIZE - 9)
  467. #define MVPP2_PE_IP6_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 8)
  468. #define MVPP2_PE_IP4_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 7)
  469. #define MVPP2_PE_ETH_TYPE_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 6)
  470. #define MVPP2_PE_VLAN_DBL (MVPP2_PRS_TCAM_SRAM_SIZE - 5)
  471. #define MVPP2_PE_VLAN_NONE (MVPP2_PRS_TCAM_SRAM_SIZE - 4)
  472. #define MVPP2_PE_MAC_MC_ALL (MVPP2_PRS_TCAM_SRAM_SIZE - 3)
  473. #define MVPP2_PE_MAC_PROMISCUOUS (MVPP2_PRS_TCAM_SRAM_SIZE - 2)
  474. #define MVPP2_PE_MAC_NON_PROMISCUOUS (MVPP2_PRS_TCAM_SRAM_SIZE - 1)
  475. /* Sram structure
  476. * The fields are represented by MVPP2_PRS_TCAM_DATA_REG(3)->(0).
  477. */
  478. #define MVPP2_PRS_SRAM_RI_OFFS 0
  479. #define MVPP2_PRS_SRAM_RI_WORD 0
  480. #define MVPP2_PRS_SRAM_RI_CTRL_OFFS 32
  481. #define MVPP2_PRS_SRAM_RI_CTRL_WORD 1
  482. #define MVPP2_PRS_SRAM_RI_CTRL_BITS 32
  483. #define MVPP2_PRS_SRAM_SHIFT_OFFS 64
  484. #define MVPP2_PRS_SRAM_SHIFT_SIGN_BIT 72
  485. #define MVPP2_PRS_SRAM_UDF_OFFS 73
  486. #define MVPP2_PRS_SRAM_UDF_BITS 8
  487. #define MVPP2_PRS_SRAM_UDF_MASK 0xff
  488. #define MVPP2_PRS_SRAM_UDF_SIGN_BIT 81
  489. #define MVPP2_PRS_SRAM_UDF_TYPE_OFFS 82
  490. #define MVPP2_PRS_SRAM_UDF_TYPE_MASK 0x7
  491. #define MVPP2_PRS_SRAM_UDF_TYPE_L3 1
  492. #define MVPP2_PRS_SRAM_UDF_TYPE_L4 4
  493. #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS 85
  494. #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_MASK 0x3
  495. #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD 1
  496. #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_IP4_ADD 2
  497. #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_IP6_ADD 3
  498. #define MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS 87
  499. #define MVPP2_PRS_SRAM_OP_SEL_UDF_BITS 2
  500. #define MVPP2_PRS_SRAM_OP_SEL_UDF_MASK 0x3
  501. #define MVPP2_PRS_SRAM_OP_SEL_UDF_ADD 0
  502. #define MVPP2_PRS_SRAM_OP_SEL_UDF_IP4_ADD 2
  503. #define MVPP2_PRS_SRAM_OP_SEL_UDF_IP6_ADD 3
  504. #define MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS 89
  505. #define MVPP2_PRS_SRAM_AI_OFFS 90
  506. #define MVPP2_PRS_SRAM_AI_CTRL_OFFS 98
  507. #define MVPP2_PRS_SRAM_AI_CTRL_BITS 8
  508. #define MVPP2_PRS_SRAM_AI_MASK 0xff
  509. #define MVPP2_PRS_SRAM_NEXT_LU_OFFS 106
  510. #define MVPP2_PRS_SRAM_NEXT_LU_MASK 0xf
  511. #define MVPP2_PRS_SRAM_LU_DONE_BIT 110
  512. #define MVPP2_PRS_SRAM_LU_GEN_BIT 111
  513. /* Sram result info bits assignment */
  514. #define MVPP2_PRS_RI_MAC_ME_MASK 0x1
  515. #define MVPP2_PRS_RI_DSA_MASK 0x2
  516. #define MVPP2_PRS_RI_VLAN_MASK 0xc
  517. #define MVPP2_PRS_RI_VLAN_NONE ~(BIT(2) | BIT(3))
  518. #define MVPP2_PRS_RI_VLAN_SINGLE BIT(2)
  519. #define MVPP2_PRS_RI_VLAN_DOUBLE BIT(3)
  520. #define MVPP2_PRS_RI_VLAN_TRIPLE (BIT(2) | BIT(3))
  521. #define MVPP2_PRS_RI_CPU_CODE_MASK 0x70
  522. #define MVPP2_PRS_RI_CPU_CODE_RX_SPEC BIT(4)
  523. #define MVPP2_PRS_RI_L2_CAST_MASK 0x600
  524. #define MVPP2_PRS_RI_L2_UCAST ~(BIT(9) | BIT(10))
  525. #define MVPP2_PRS_RI_L2_MCAST BIT(9)
  526. #define MVPP2_PRS_RI_L2_BCAST BIT(10)
  527. #define MVPP2_PRS_RI_PPPOE_MASK 0x800
  528. #define MVPP2_PRS_RI_L3_PROTO_MASK 0x7000
  529. #define MVPP2_PRS_RI_L3_UN ~(BIT(12) | BIT(13) | BIT(14))
  530. #define MVPP2_PRS_RI_L3_IP4 BIT(12)
  531. #define MVPP2_PRS_RI_L3_IP4_OPT BIT(13)
  532. #define MVPP2_PRS_RI_L3_IP4_OTHER (BIT(12) | BIT(13))
  533. #define MVPP2_PRS_RI_L3_IP6 BIT(14)
  534. #define MVPP2_PRS_RI_L3_IP6_EXT (BIT(12) | BIT(14))
  535. #define MVPP2_PRS_RI_L3_ARP (BIT(13) | BIT(14))
  536. #define MVPP2_PRS_RI_L3_ADDR_MASK 0x18000
  537. #define MVPP2_PRS_RI_L3_UCAST ~(BIT(15) | BIT(16))
  538. #define MVPP2_PRS_RI_L3_MCAST BIT(15)
  539. #define MVPP2_PRS_RI_L3_BCAST (BIT(15) | BIT(16))
  540. #define MVPP2_PRS_RI_IP_FRAG_MASK 0x20000
  541. #define MVPP2_PRS_RI_UDF3_MASK 0x300000
  542. #define MVPP2_PRS_RI_UDF3_RX_SPECIAL BIT(21)
  543. #define MVPP2_PRS_RI_L4_PROTO_MASK 0x1c00000
  544. #define MVPP2_PRS_RI_L4_TCP BIT(22)
  545. #define MVPP2_PRS_RI_L4_UDP BIT(23)
  546. #define MVPP2_PRS_RI_L4_OTHER (BIT(22) | BIT(23))
  547. #define MVPP2_PRS_RI_UDF7_MASK 0x60000000
  548. #define MVPP2_PRS_RI_UDF7_IP6_LITE BIT(29)
  549. #define MVPP2_PRS_RI_DROP_MASK 0x80000000
  550. /* Sram additional info bits assignment */
  551. #define MVPP2_PRS_IPV4_DIP_AI_BIT BIT(0)
  552. #define MVPP2_PRS_IPV6_NO_EXT_AI_BIT BIT(0)
  553. #define MVPP2_PRS_IPV6_EXT_AI_BIT BIT(1)
  554. #define MVPP2_PRS_IPV6_EXT_AH_AI_BIT BIT(2)
  555. #define MVPP2_PRS_IPV6_EXT_AH_LEN_AI_BIT BIT(3)
  556. #define MVPP2_PRS_IPV6_EXT_AH_L4_AI_BIT BIT(4)
  557. #define MVPP2_PRS_SINGLE_VLAN_AI 0
  558. #define MVPP2_PRS_DBL_VLAN_AI_BIT BIT(7)
  559. /* DSA/EDSA type */
  560. #define MVPP2_PRS_TAGGED true
  561. #define MVPP2_PRS_UNTAGGED false
  562. #define MVPP2_PRS_EDSA true
  563. #define MVPP2_PRS_DSA false
  564. /* MAC entries, shadow udf */
  565. enum mvpp2_prs_udf {
  566. MVPP2_PRS_UDF_MAC_DEF,
  567. MVPP2_PRS_UDF_MAC_RANGE,
  568. MVPP2_PRS_UDF_L2_DEF,
  569. MVPP2_PRS_UDF_L2_DEF_COPY,
  570. MVPP2_PRS_UDF_L2_USER,
  571. };
  572. /* Lookup ID */
  573. enum mvpp2_prs_lookup {
  574. MVPP2_PRS_LU_MH,
  575. MVPP2_PRS_LU_MAC,
  576. MVPP2_PRS_LU_DSA,
  577. MVPP2_PRS_LU_VLAN,
  578. MVPP2_PRS_LU_L2,
  579. MVPP2_PRS_LU_PPPOE,
  580. MVPP2_PRS_LU_IP4,
  581. MVPP2_PRS_LU_IP6,
  582. MVPP2_PRS_LU_FLOWS,
  583. MVPP2_PRS_LU_LAST,
  584. };
  585. /* L3 cast enum */
  586. enum mvpp2_prs_l3_cast {
  587. MVPP2_PRS_L3_UNI_CAST,
  588. MVPP2_PRS_L3_MULTI_CAST,
  589. MVPP2_PRS_L3_BROAD_CAST
  590. };
  591. /* Classifier constants */
  592. #define MVPP2_CLS_FLOWS_TBL_SIZE 512
  593. #define MVPP2_CLS_FLOWS_TBL_DATA_WORDS 3
  594. #define MVPP2_CLS_LKP_TBL_SIZE 64
  595. /* BM constants */
  596. #define MVPP2_BM_POOLS_NUM 1
  597. #define MVPP2_BM_LONG_BUF_NUM 16
  598. #define MVPP2_BM_SHORT_BUF_NUM 16
  599. #define MVPP2_BM_POOL_SIZE_MAX (16*1024 - MVPP2_BM_POOL_PTR_ALIGN/4)
  600. #define MVPP2_BM_POOL_PTR_ALIGN 128
  601. #define MVPP2_BM_SWF_LONG_POOL(port) 0
  602. /* BM cookie (32 bits) definition */
  603. #define MVPP2_BM_COOKIE_POOL_OFFS 8
  604. #define MVPP2_BM_COOKIE_CPU_OFFS 24
  605. /* BM short pool packet size
  606. * These value assure that for SWF the total number
  607. * of bytes allocated for each buffer will be 512
  608. */
  609. #define MVPP2_BM_SHORT_PKT_SIZE MVPP2_RX_MAX_PKT_SIZE(512)
  610. enum mvpp2_bm_type {
  611. MVPP2_BM_FREE,
  612. MVPP2_BM_SWF_LONG,
  613. MVPP2_BM_SWF_SHORT
  614. };
  615. /* Definitions */
  616. /* Shared Packet Processor resources */
  617. struct mvpp2 {
  618. /* Shared registers' base addresses */
  619. void __iomem *base;
  620. void __iomem *lms_base;
  621. /* List of pointers to port structures */
  622. struct mvpp2_port **port_list;
  623. /* Aggregated TXQs */
  624. struct mvpp2_tx_queue *aggr_txqs;
  625. /* BM pools */
  626. struct mvpp2_bm_pool *bm_pools;
  627. /* PRS shadow table */
  628. struct mvpp2_prs_shadow *prs_shadow;
  629. /* PRS auxiliary table for double vlan entries control */
  630. bool *prs_double_vlans;
  631. /* Tclk value */
  632. u32 tclk;
  633. struct mii_dev *bus;
  634. };
  635. struct mvpp2_pcpu_stats {
  636. u64 rx_packets;
  637. u64 rx_bytes;
  638. u64 tx_packets;
  639. u64 tx_bytes;
  640. };
  641. struct mvpp2_port {
  642. u8 id;
  643. int irq;
  644. struct mvpp2 *priv;
  645. /* Per-port registers' base address */
  646. void __iomem *base;
  647. struct mvpp2_rx_queue **rxqs;
  648. struct mvpp2_tx_queue **txqs;
  649. int pkt_size;
  650. u32 pending_cause_rx;
  651. /* Per-CPU port control */
  652. struct mvpp2_port_pcpu __percpu *pcpu;
  653. /* Flags */
  654. unsigned long flags;
  655. u16 tx_ring_size;
  656. u16 rx_ring_size;
  657. struct mvpp2_pcpu_stats __percpu *stats;
  658. struct phy_device *phy_dev;
  659. phy_interface_t phy_interface;
  660. int phy_node;
  661. int phyaddr;
  662. int init;
  663. unsigned int link;
  664. unsigned int duplex;
  665. unsigned int speed;
  666. struct mvpp2_bm_pool *pool_long;
  667. struct mvpp2_bm_pool *pool_short;
  668. /* Index of first port's physical RXQ */
  669. u8 first_rxq;
  670. u8 dev_addr[ETH_ALEN];
  671. };
  672. /* The mvpp2_tx_desc and mvpp2_rx_desc structures describe the
  673. * layout of the transmit and reception DMA descriptors, and their
  674. * layout is therefore defined by the hardware design
  675. */
  676. #define MVPP2_TXD_L3_OFF_SHIFT 0
  677. #define MVPP2_TXD_IP_HLEN_SHIFT 8
  678. #define MVPP2_TXD_L4_CSUM_FRAG BIT(13)
  679. #define MVPP2_TXD_L4_CSUM_NOT BIT(14)
  680. #define MVPP2_TXD_IP_CSUM_DISABLE BIT(15)
  681. #define MVPP2_TXD_PADDING_DISABLE BIT(23)
  682. #define MVPP2_TXD_L4_UDP BIT(24)
  683. #define MVPP2_TXD_L3_IP6 BIT(26)
  684. #define MVPP2_TXD_L_DESC BIT(28)
  685. #define MVPP2_TXD_F_DESC BIT(29)
  686. #define MVPP2_RXD_ERR_SUMMARY BIT(15)
  687. #define MVPP2_RXD_ERR_CODE_MASK (BIT(13) | BIT(14))
  688. #define MVPP2_RXD_ERR_CRC 0x0
  689. #define MVPP2_RXD_ERR_OVERRUN BIT(13)
  690. #define MVPP2_RXD_ERR_RESOURCE (BIT(13) | BIT(14))
  691. #define MVPP2_RXD_BM_POOL_ID_OFFS 16
  692. #define MVPP2_RXD_BM_POOL_ID_MASK (BIT(16) | BIT(17) | BIT(18))
  693. #define MVPP2_RXD_HWF_SYNC BIT(21)
  694. #define MVPP2_RXD_L4_CSUM_OK BIT(22)
  695. #define MVPP2_RXD_IP4_HEADER_ERR BIT(24)
  696. #define MVPP2_RXD_L4_TCP BIT(25)
  697. #define MVPP2_RXD_L4_UDP BIT(26)
  698. #define MVPP2_RXD_L3_IP4 BIT(28)
  699. #define MVPP2_RXD_L3_IP6 BIT(30)
  700. #define MVPP2_RXD_BUF_HDR BIT(31)
  701. struct mvpp2_tx_desc {
  702. u32 command; /* Options used by HW for packet transmitting.*/
  703. u8 packet_offset; /* the offset from the buffer beginning */
  704. u8 phys_txq; /* destination queue ID */
  705. u16 data_size; /* data size of transmitted packet in bytes */
  706. u32 buf_phys_addr; /* physical addr of transmitted buffer */
  707. u32 buf_cookie; /* cookie for access to TX buffer in tx path */
  708. u32 reserved1[3]; /* hw_cmd (for future use, BM, PON, PNC) */
  709. u32 reserved2; /* reserved (for future use) */
  710. };
  711. struct mvpp2_rx_desc {
  712. u32 status; /* info about received packet */
  713. u16 reserved1; /* parser_info (for future use, PnC) */
  714. u16 data_size; /* size of received packet in bytes */
  715. u32 buf_phys_addr; /* physical address of the buffer */
  716. u32 buf_cookie; /* cookie for access to RX buffer in rx path */
  717. u16 reserved2; /* gem_port_id (for future use, PON) */
  718. u16 reserved3; /* csum_l4 (for future use, PnC) */
  719. u8 reserved4; /* bm_qset (for future use, BM) */
  720. u8 reserved5;
  721. u16 reserved6; /* classify_info (for future use, PnC) */
  722. u32 reserved7; /* flow_id (for future use, PnC) */
  723. u32 reserved8;
  724. };
  725. /* Per-CPU Tx queue control */
  726. struct mvpp2_txq_pcpu {
  727. int cpu;
  728. /* Number of Tx DMA descriptors in the descriptor ring */
  729. int size;
  730. /* Number of currently used Tx DMA descriptor in the
  731. * descriptor ring
  732. */
  733. int count;
  734. /* Number of Tx DMA descriptors reserved for each CPU */
  735. int reserved_num;
  736. /* Index of last TX DMA descriptor that was inserted */
  737. int txq_put_index;
  738. /* Index of the TX DMA descriptor to be cleaned up */
  739. int txq_get_index;
  740. };
  741. struct mvpp2_tx_queue {
  742. /* Physical number of this Tx queue */
  743. u8 id;
  744. /* Logical number of this Tx queue */
  745. u8 log_id;
  746. /* Number of Tx DMA descriptors in the descriptor ring */
  747. int size;
  748. /* Number of currently used Tx DMA descriptor in the descriptor ring */
  749. int count;
  750. /* Per-CPU control of physical Tx queues */
  751. struct mvpp2_txq_pcpu __percpu *pcpu;
  752. u32 done_pkts_coal;
  753. /* Virtual address of thex Tx DMA descriptors array */
  754. struct mvpp2_tx_desc *descs;
  755. /* DMA address of the Tx DMA descriptors array */
  756. dma_addr_t descs_phys;
  757. /* Index of the last Tx DMA descriptor */
  758. int last_desc;
  759. /* Index of the next Tx DMA descriptor to process */
  760. int next_desc_to_proc;
  761. };
  762. struct mvpp2_rx_queue {
  763. /* RX queue number, in the range 0-31 for physical RXQs */
  764. u8 id;
  765. /* Num of rx descriptors in the rx descriptor ring */
  766. int size;
  767. u32 pkts_coal;
  768. u32 time_coal;
  769. /* Virtual address of the RX DMA descriptors array */
  770. struct mvpp2_rx_desc *descs;
  771. /* DMA address of the RX DMA descriptors array */
  772. dma_addr_t descs_phys;
  773. /* Index of the last RX DMA descriptor */
  774. int last_desc;
  775. /* Index of the next RX DMA descriptor to process */
  776. int next_desc_to_proc;
  777. /* ID of port to which physical RXQ is mapped */
  778. int port;
  779. /* Port's logic RXQ number to which physical RXQ is mapped */
  780. int logic_rxq;
  781. };
  782. union mvpp2_prs_tcam_entry {
  783. u32 word[MVPP2_PRS_TCAM_WORDS];
  784. u8 byte[MVPP2_PRS_TCAM_WORDS * 4];
  785. };
  786. union mvpp2_prs_sram_entry {
  787. u32 word[MVPP2_PRS_SRAM_WORDS];
  788. u8 byte[MVPP2_PRS_SRAM_WORDS * 4];
  789. };
  790. struct mvpp2_prs_entry {
  791. u32 index;
  792. union mvpp2_prs_tcam_entry tcam;
  793. union mvpp2_prs_sram_entry sram;
  794. };
  795. struct mvpp2_prs_shadow {
  796. bool valid;
  797. bool finish;
  798. /* Lookup ID */
  799. int lu;
  800. /* User defined offset */
  801. int udf;
  802. /* Result info */
  803. u32 ri;
  804. u32 ri_mask;
  805. };
  806. struct mvpp2_cls_flow_entry {
  807. u32 index;
  808. u32 data[MVPP2_CLS_FLOWS_TBL_DATA_WORDS];
  809. };
  810. struct mvpp2_cls_lookup_entry {
  811. u32 lkpid;
  812. u32 way;
  813. u32 data;
  814. };
  815. struct mvpp2_bm_pool {
  816. /* Pool number in the range 0-7 */
  817. int id;
  818. enum mvpp2_bm_type type;
  819. /* Buffer Pointers Pool External (BPPE) size */
  820. int size;
  821. /* Number of buffers for this pool */
  822. int buf_num;
  823. /* Pool buffer size */
  824. int buf_size;
  825. /* Packet size */
  826. int pkt_size;
  827. /* BPPE virtual base address */
  828. u32 *virt_addr;
  829. /* BPPE physical base address */
  830. dma_addr_t phys_addr;
  831. /* Ports using BM pool */
  832. u32 port_map;
  833. /* Occupied buffers indicator */
  834. int in_use_thresh;
  835. };
  836. struct mvpp2_buff_hdr {
  837. u32 next_buff_phys_addr;
  838. u32 next_buff_virt_addr;
  839. u16 byte_count;
  840. u16 info;
  841. u8 reserved1; /* bm_qset (for future use, BM) */
  842. };
  843. /* Buffer header info bits */
  844. #define MVPP2_B_HDR_INFO_MC_ID_MASK 0xfff
  845. #define MVPP2_B_HDR_INFO_MC_ID(info) ((info) & MVPP2_B_HDR_INFO_MC_ID_MASK)
  846. #define MVPP2_B_HDR_INFO_LAST_OFFS 12
  847. #define MVPP2_B_HDR_INFO_LAST_MASK BIT(12)
  848. #define MVPP2_B_HDR_INFO_IS_LAST(info) \
  849. ((info & MVPP2_B_HDR_INFO_LAST_MASK) >> MVPP2_B_HDR_INFO_LAST_OFFS)
  850. /* Static declaractions */
  851. /* Number of RXQs used by single port */
  852. static int rxq_number = MVPP2_DEFAULT_RXQ;
  853. /* Number of TXQs used by single port */
  854. static int txq_number = MVPP2_DEFAULT_TXQ;
  855. #define MVPP2_DRIVER_NAME "mvpp2"
  856. #define MVPP2_DRIVER_VERSION "1.0"
  857. /*
  858. * U-Boot internal data, mostly uncached buffers for descriptors and data
  859. */
  860. struct buffer_location {
  861. struct mvpp2_tx_desc *aggr_tx_descs;
  862. struct mvpp2_tx_desc *tx_descs;
  863. struct mvpp2_rx_desc *rx_descs;
  864. u32 *bm_pool[MVPP2_BM_POOLS_NUM];
  865. u32 *rx_buffer[MVPP2_BM_LONG_BUF_NUM];
  866. int first_rxq;
  867. };
  868. /*
  869. * All 4 interfaces use the same global buffer, since only one interface
  870. * can be enabled at once
  871. */
  872. static struct buffer_location buffer_loc;
  873. /*
  874. * Page table entries are set to 1MB, or multiples of 1MB
  875. * (not < 1MB). driver uses less bd's so use 1MB bdspace.
  876. */
  877. #define BD_SPACE (1 << 20)
  878. /* Utility/helper methods */
  879. static void mvpp2_write(struct mvpp2 *priv, u32 offset, u32 data)
  880. {
  881. writel(data, priv->base + offset);
  882. }
  883. static u32 mvpp2_read(struct mvpp2 *priv, u32 offset)
  884. {
  885. return readl(priv->base + offset);
  886. }
  887. static void mvpp2_txq_inc_get(struct mvpp2_txq_pcpu *txq_pcpu)
  888. {
  889. txq_pcpu->txq_get_index++;
  890. if (txq_pcpu->txq_get_index == txq_pcpu->size)
  891. txq_pcpu->txq_get_index = 0;
  892. }
  893. /* Get number of physical egress port */
  894. static inline int mvpp2_egress_port(struct mvpp2_port *port)
  895. {
  896. return MVPP2_MAX_TCONT + port->id;
  897. }
  898. /* Get number of physical TXQ */
  899. static inline int mvpp2_txq_phys(int port, int txq)
  900. {
  901. return (MVPP2_MAX_TCONT + port) * MVPP2_MAX_TXQ + txq;
  902. }
  903. /* Parser configuration routines */
  904. /* Update parser tcam and sram hw entries */
  905. static int mvpp2_prs_hw_write(struct mvpp2 *priv, struct mvpp2_prs_entry *pe)
  906. {
  907. int i;
  908. if (pe->index > MVPP2_PRS_TCAM_SRAM_SIZE - 1)
  909. return -EINVAL;
  910. /* Clear entry invalidation bit */
  911. pe->tcam.word[MVPP2_PRS_TCAM_INV_WORD] &= ~MVPP2_PRS_TCAM_INV_MASK;
  912. /* Write tcam index - indirect access */
  913. mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, pe->index);
  914. for (i = 0; i < MVPP2_PRS_TCAM_WORDS; i++)
  915. mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(i), pe->tcam.word[i]);
  916. /* Write sram index - indirect access */
  917. mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, pe->index);
  918. for (i = 0; i < MVPP2_PRS_SRAM_WORDS; i++)
  919. mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), pe->sram.word[i]);
  920. return 0;
  921. }
  922. /* Read tcam entry from hw */
  923. static int mvpp2_prs_hw_read(struct mvpp2 *priv, struct mvpp2_prs_entry *pe)
  924. {
  925. int i;
  926. if (pe->index > MVPP2_PRS_TCAM_SRAM_SIZE - 1)
  927. return -EINVAL;
  928. /* Write tcam index - indirect access */
  929. mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, pe->index);
  930. pe->tcam.word[MVPP2_PRS_TCAM_INV_WORD] = mvpp2_read(priv,
  931. MVPP2_PRS_TCAM_DATA_REG(MVPP2_PRS_TCAM_INV_WORD));
  932. if (pe->tcam.word[MVPP2_PRS_TCAM_INV_WORD] & MVPP2_PRS_TCAM_INV_MASK)
  933. return MVPP2_PRS_TCAM_ENTRY_INVALID;
  934. for (i = 0; i < MVPP2_PRS_TCAM_WORDS; i++)
  935. pe->tcam.word[i] = mvpp2_read(priv, MVPP2_PRS_TCAM_DATA_REG(i));
  936. /* Write sram index - indirect access */
  937. mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, pe->index);
  938. for (i = 0; i < MVPP2_PRS_SRAM_WORDS; i++)
  939. pe->sram.word[i] = mvpp2_read(priv, MVPP2_PRS_SRAM_DATA_REG(i));
  940. return 0;
  941. }
  942. /* Invalidate tcam hw entry */
  943. static void mvpp2_prs_hw_inv(struct mvpp2 *priv, int index)
  944. {
  945. /* Write index - indirect access */
  946. mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, index);
  947. mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(MVPP2_PRS_TCAM_INV_WORD),
  948. MVPP2_PRS_TCAM_INV_MASK);
  949. }
  950. /* Enable shadow table entry and set its lookup ID */
  951. static void mvpp2_prs_shadow_set(struct mvpp2 *priv, int index, int lu)
  952. {
  953. priv->prs_shadow[index].valid = true;
  954. priv->prs_shadow[index].lu = lu;
  955. }
  956. /* Update ri fields in shadow table entry */
  957. static void mvpp2_prs_shadow_ri_set(struct mvpp2 *priv, int index,
  958. unsigned int ri, unsigned int ri_mask)
  959. {
  960. priv->prs_shadow[index].ri_mask = ri_mask;
  961. priv->prs_shadow[index].ri = ri;
  962. }
  963. /* Update lookup field in tcam sw entry */
  964. static void mvpp2_prs_tcam_lu_set(struct mvpp2_prs_entry *pe, unsigned int lu)
  965. {
  966. int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_LU_BYTE);
  967. pe->tcam.byte[MVPP2_PRS_TCAM_LU_BYTE] = lu;
  968. pe->tcam.byte[enable_off] = MVPP2_PRS_LU_MASK;
  969. }
  970. /* Update mask for single port in tcam sw entry */
  971. static void mvpp2_prs_tcam_port_set(struct mvpp2_prs_entry *pe,
  972. unsigned int port, bool add)
  973. {
  974. int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_PORT_BYTE);
  975. if (add)
  976. pe->tcam.byte[enable_off] &= ~(1 << port);
  977. else
  978. pe->tcam.byte[enable_off] |= 1 << port;
  979. }
  980. /* Update port map in tcam sw entry */
  981. static void mvpp2_prs_tcam_port_map_set(struct mvpp2_prs_entry *pe,
  982. unsigned int ports)
  983. {
  984. unsigned char port_mask = MVPP2_PRS_PORT_MASK;
  985. int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_PORT_BYTE);
  986. pe->tcam.byte[MVPP2_PRS_TCAM_PORT_BYTE] = 0;
  987. pe->tcam.byte[enable_off] &= ~port_mask;
  988. pe->tcam.byte[enable_off] |= ~ports & MVPP2_PRS_PORT_MASK;
  989. }
  990. /* Obtain port map from tcam sw entry */
  991. static unsigned int mvpp2_prs_tcam_port_map_get(struct mvpp2_prs_entry *pe)
  992. {
  993. int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_PORT_BYTE);
  994. return ~(pe->tcam.byte[enable_off]) & MVPP2_PRS_PORT_MASK;
  995. }
  996. /* Set byte of data and its enable bits in tcam sw entry */
  997. static void mvpp2_prs_tcam_data_byte_set(struct mvpp2_prs_entry *pe,
  998. unsigned int offs, unsigned char byte,
  999. unsigned char enable)
  1000. {
  1001. pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE(offs)] = byte;
  1002. pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE_EN(offs)] = enable;
  1003. }
  1004. /* Get byte of data and its enable bits from tcam sw entry */
  1005. static void mvpp2_prs_tcam_data_byte_get(struct mvpp2_prs_entry *pe,
  1006. unsigned int offs, unsigned char *byte,
  1007. unsigned char *enable)
  1008. {
  1009. *byte = pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE(offs)];
  1010. *enable = pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE_EN(offs)];
  1011. }
  1012. /* Set ethertype in tcam sw entry */
  1013. static void mvpp2_prs_match_etype(struct mvpp2_prs_entry *pe, int offset,
  1014. unsigned short ethertype)
  1015. {
  1016. mvpp2_prs_tcam_data_byte_set(pe, offset + 0, ethertype >> 8, 0xff);
  1017. mvpp2_prs_tcam_data_byte_set(pe, offset + 1, ethertype & 0xff, 0xff);
  1018. }
  1019. /* Set bits in sram sw entry */
  1020. static void mvpp2_prs_sram_bits_set(struct mvpp2_prs_entry *pe, int bit_num,
  1021. int val)
  1022. {
  1023. pe->sram.byte[MVPP2_BIT_TO_BYTE(bit_num)] |= (val << (bit_num % 8));
  1024. }
  1025. /* Clear bits in sram sw entry */
  1026. static void mvpp2_prs_sram_bits_clear(struct mvpp2_prs_entry *pe, int bit_num,
  1027. int val)
  1028. {
  1029. pe->sram.byte[MVPP2_BIT_TO_BYTE(bit_num)] &= ~(val << (bit_num % 8));
  1030. }
  1031. /* Update ri bits in sram sw entry */
  1032. static void mvpp2_prs_sram_ri_update(struct mvpp2_prs_entry *pe,
  1033. unsigned int bits, unsigned int mask)
  1034. {
  1035. unsigned int i;
  1036. for (i = 0; i < MVPP2_PRS_SRAM_RI_CTRL_BITS; i++) {
  1037. int ri_off = MVPP2_PRS_SRAM_RI_OFFS;
  1038. if (!(mask & BIT(i)))
  1039. continue;
  1040. if (bits & BIT(i))
  1041. mvpp2_prs_sram_bits_set(pe, ri_off + i, 1);
  1042. else
  1043. mvpp2_prs_sram_bits_clear(pe, ri_off + i, 1);
  1044. mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_RI_CTRL_OFFS + i, 1);
  1045. }
  1046. }
  1047. /* Update ai bits in sram sw entry */
  1048. static void mvpp2_prs_sram_ai_update(struct mvpp2_prs_entry *pe,
  1049. unsigned int bits, unsigned int mask)
  1050. {
  1051. unsigned int i;
  1052. int ai_off = MVPP2_PRS_SRAM_AI_OFFS;
  1053. for (i = 0; i < MVPP2_PRS_SRAM_AI_CTRL_BITS; i++) {
  1054. if (!(mask & BIT(i)))
  1055. continue;
  1056. if (bits & BIT(i))
  1057. mvpp2_prs_sram_bits_set(pe, ai_off + i, 1);
  1058. else
  1059. mvpp2_prs_sram_bits_clear(pe, ai_off + i, 1);
  1060. mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_AI_CTRL_OFFS + i, 1);
  1061. }
  1062. }
  1063. /* Read ai bits from sram sw entry */
  1064. static int mvpp2_prs_sram_ai_get(struct mvpp2_prs_entry *pe)
  1065. {
  1066. u8 bits;
  1067. int ai_off = MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_AI_OFFS);
  1068. int ai_en_off = ai_off + 1;
  1069. int ai_shift = MVPP2_PRS_SRAM_AI_OFFS % 8;
  1070. bits = (pe->sram.byte[ai_off] >> ai_shift) |
  1071. (pe->sram.byte[ai_en_off] << (8 - ai_shift));
  1072. return bits;
  1073. }
  1074. /* In sram sw entry set lookup ID field of the tcam key to be used in the next
  1075. * lookup interation
  1076. */
  1077. static void mvpp2_prs_sram_next_lu_set(struct mvpp2_prs_entry *pe,
  1078. unsigned int lu)
  1079. {
  1080. int sram_next_off = MVPP2_PRS_SRAM_NEXT_LU_OFFS;
  1081. mvpp2_prs_sram_bits_clear(pe, sram_next_off,
  1082. MVPP2_PRS_SRAM_NEXT_LU_MASK);
  1083. mvpp2_prs_sram_bits_set(pe, sram_next_off, lu);
  1084. }
  1085. /* In the sram sw entry set sign and value of the next lookup offset
  1086. * and the offset value generated to the classifier
  1087. */
  1088. static void mvpp2_prs_sram_shift_set(struct mvpp2_prs_entry *pe, int shift,
  1089. unsigned int op)
  1090. {
  1091. /* Set sign */
  1092. if (shift < 0) {
  1093. mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_SHIFT_SIGN_BIT, 1);
  1094. shift = 0 - shift;
  1095. } else {
  1096. mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_SHIFT_SIGN_BIT, 1);
  1097. }
  1098. /* Set value */
  1099. pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_SHIFT_OFFS)] =
  1100. (unsigned char)shift;
  1101. /* Reset and set operation */
  1102. mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS,
  1103. MVPP2_PRS_SRAM_OP_SEL_SHIFT_MASK);
  1104. mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS, op);
  1105. /* Set base offset as current */
  1106. mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS, 1);
  1107. }
  1108. /* In the sram sw entry set sign and value of the user defined offset
  1109. * generated to the classifier
  1110. */
  1111. static void mvpp2_prs_sram_offset_set(struct mvpp2_prs_entry *pe,
  1112. unsigned int type, int offset,
  1113. unsigned int op)
  1114. {
  1115. /* Set sign */
  1116. if (offset < 0) {
  1117. mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_SIGN_BIT, 1);
  1118. offset = 0 - offset;
  1119. } else {
  1120. mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_SIGN_BIT, 1);
  1121. }
  1122. /* Set value */
  1123. mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_OFFS,
  1124. MVPP2_PRS_SRAM_UDF_MASK);
  1125. mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_OFFS, offset);
  1126. pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_UDF_OFFS +
  1127. MVPP2_PRS_SRAM_UDF_BITS)] &=
  1128. ~(MVPP2_PRS_SRAM_UDF_MASK >> (8 - (MVPP2_PRS_SRAM_UDF_OFFS % 8)));
  1129. pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_UDF_OFFS +
  1130. MVPP2_PRS_SRAM_UDF_BITS)] |=
  1131. (offset >> (8 - (MVPP2_PRS_SRAM_UDF_OFFS % 8)));
  1132. /* Set offset type */
  1133. mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_TYPE_OFFS,
  1134. MVPP2_PRS_SRAM_UDF_TYPE_MASK);
  1135. mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_TYPE_OFFS, type);
  1136. /* Set offset operation */
  1137. mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS,
  1138. MVPP2_PRS_SRAM_OP_SEL_UDF_MASK);
  1139. mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS, op);
  1140. pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS +
  1141. MVPP2_PRS_SRAM_OP_SEL_UDF_BITS)] &=
  1142. ~(MVPP2_PRS_SRAM_OP_SEL_UDF_MASK >>
  1143. (8 - (MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS % 8)));
  1144. pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS +
  1145. MVPP2_PRS_SRAM_OP_SEL_UDF_BITS)] |=
  1146. (op >> (8 - (MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS % 8)));
  1147. /* Set base offset as current */
  1148. mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS, 1);
  1149. }
  1150. /* Find parser flow entry */
  1151. static struct mvpp2_prs_entry *mvpp2_prs_flow_find(struct mvpp2 *priv, int flow)
  1152. {
  1153. struct mvpp2_prs_entry *pe;
  1154. int tid;
  1155. pe = kzalloc(sizeof(*pe), GFP_KERNEL);
  1156. if (!pe)
  1157. return NULL;
  1158. mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_FLOWS);
  1159. /* Go through the all entires with MVPP2_PRS_LU_FLOWS */
  1160. for (tid = MVPP2_PRS_TCAM_SRAM_SIZE - 1; tid >= 0; tid--) {
  1161. u8 bits;
  1162. if (!priv->prs_shadow[tid].valid ||
  1163. priv->prs_shadow[tid].lu != MVPP2_PRS_LU_FLOWS)
  1164. continue;
  1165. pe->index = tid;
  1166. mvpp2_prs_hw_read(priv, pe);
  1167. bits = mvpp2_prs_sram_ai_get(pe);
  1168. /* Sram store classification lookup ID in AI bits [5:0] */
  1169. if ((bits & MVPP2_PRS_FLOW_ID_MASK) == flow)
  1170. return pe;
  1171. }
  1172. kfree(pe);
  1173. return NULL;
  1174. }
  1175. /* Return first free tcam index, seeking from start to end */
  1176. static int mvpp2_prs_tcam_first_free(struct mvpp2 *priv, unsigned char start,
  1177. unsigned char end)
  1178. {
  1179. int tid;
  1180. if (start > end)
  1181. swap(start, end);
  1182. if (end >= MVPP2_PRS_TCAM_SRAM_SIZE)
  1183. end = MVPP2_PRS_TCAM_SRAM_SIZE - 1;
  1184. for (tid = start; tid <= end; tid++) {
  1185. if (!priv->prs_shadow[tid].valid)
  1186. return tid;
  1187. }
  1188. return -EINVAL;
  1189. }
  1190. /* Enable/disable dropping all mac da's */
  1191. static void mvpp2_prs_mac_drop_all_set(struct mvpp2 *priv, int port, bool add)
  1192. {
  1193. struct mvpp2_prs_entry pe;
  1194. if (priv->prs_shadow[MVPP2_PE_DROP_ALL].valid) {
  1195. /* Entry exist - update port only */
  1196. pe.index = MVPP2_PE_DROP_ALL;
  1197. mvpp2_prs_hw_read(priv, &pe);
  1198. } else {
  1199. /* Entry doesn't exist - create new */
  1200. memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
  1201. mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);
  1202. pe.index = MVPP2_PE_DROP_ALL;
  1203. /* Non-promiscuous mode for all ports - DROP unknown packets */
  1204. mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DROP_MASK,
  1205. MVPP2_PRS_RI_DROP_MASK);
  1206. mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
  1207. mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
  1208. /* Update shadow table */
  1209. mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
  1210. /* Mask all ports */
  1211. mvpp2_prs_tcam_port_map_set(&pe, 0);
  1212. }
  1213. /* Update port mask */
  1214. mvpp2_prs_tcam_port_set(&pe, port, add);
  1215. mvpp2_prs_hw_write(priv, &pe);
  1216. }
  1217. /* Set port to promiscuous mode */
  1218. static void mvpp2_prs_mac_promisc_set(struct mvpp2 *priv, int port, bool add)
  1219. {
  1220. struct mvpp2_prs_entry pe;
  1221. /* Promiscuous mode - Accept unknown packets */
  1222. if (priv->prs_shadow[MVPP2_PE_MAC_PROMISCUOUS].valid) {
  1223. /* Entry exist - update port only */
  1224. pe.index = MVPP2_PE_MAC_PROMISCUOUS;
  1225. mvpp2_prs_hw_read(priv, &pe);
  1226. } else {
  1227. /* Entry doesn't exist - create new */
  1228. memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
  1229. mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);
  1230. pe.index = MVPP2_PE_MAC_PROMISCUOUS;
  1231. /* Continue - set next lookup */
  1232. mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_DSA);
  1233. /* Set result info bits */
  1234. mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L2_UCAST,
  1235. MVPP2_PRS_RI_L2_CAST_MASK);
  1236. /* Shift to ethertype */
  1237. mvpp2_prs_sram_shift_set(&pe, 2 * ETH_ALEN,
  1238. MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
  1239. /* Mask all ports */
  1240. mvpp2_prs_tcam_port_map_set(&pe, 0);
  1241. /* Update shadow table */
  1242. mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
  1243. }
  1244. /* Update port mask */
  1245. mvpp2_prs_tcam_port_set(&pe, port, add);
  1246. mvpp2_prs_hw_write(priv, &pe);
  1247. }
  1248. /* Accept multicast */
  1249. static void mvpp2_prs_mac_multi_set(struct mvpp2 *priv, int port, int index,
  1250. bool add)
  1251. {
  1252. struct mvpp2_prs_entry pe;
  1253. unsigned char da_mc;
  1254. /* Ethernet multicast address first byte is
  1255. * 0x01 for IPv4 and 0x33 for IPv6
  1256. */
  1257. da_mc = (index == MVPP2_PE_MAC_MC_ALL) ? 0x01 : 0x33;
  1258. if (priv->prs_shadow[index].valid) {
  1259. /* Entry exist - update port only */
  1260. pe.index = index;
  1261. mvpp2_prs_hw_read(priv, &pe);
  1262. } else {
  1263. /* Entry doesn't exist - create new */
  1264. memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
  1265. mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);
  1266. pe.index = index;
  1267. /* Continue - set next lookup */
  1268. mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_DSA);
  1269. /* Set result info bits */
  1270. mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L2_MCAST,
  1271. MVPP2_PRS_RI_L2_CAST_MASK);
  1272. /* Update tcam entry data first byte */
  1273. mvpp2_prs_tcam_data_byte_set(&pe, 0, da_mc, 0xff);
  1274. /* Shift to ethertype */
  1275. mvpp2_prs_sram_shift_set(&pe, 2 * ETH_ALEN,
  1276. MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
  1277. /* Mask all ports */
  1278. mvpp2_prs_tcam_port_map_set(&pe, 0);
  1279. /* Update shadow table */
  1280. mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
  1281. }
  1282. /* Update port mask */
  1283. mvpp2_prs_tcam_port_set(&pe, port, add);
  1284. mvpp2_prs_hw_write(priv, &pe);
  1285. }
  1286. /* Parser per-port initialization */
  1287. static void mvpp2_prs_hw_port_init(struct mvpp2 *priv, int port, int lu_first,
  1288. int lu_max, int offset)
  1289. {
  1290. u32 val;
  1291. /* Set lookup ID */
  1292. val = mvpp2_read(priv, MVPP2_PRS_INIT_LOOKUP_REG);
  1293. val &= ~MVPP2_PRS_PORT_LU_MASK(port);
  1294. val |= MVPP2_PRS_PORT_LU_VAL(port, lu_first);
  1295. mvpp2_write(priv, MVPP2_PRS_INIT_LOOKUP_REG, val);
  1296. /* Set maximum number of loops for packet received from port */
  1297. val = mvpp2_read(priv, MVPP2_PRS_MAX_LOOP_REG(port));
  1298. val &= ~MVPP2_PRS_MAX_LOOP_MASK(port);
  1299. val |= MVPP2_PRS_MAX_LOOP_VAL(port, lu_max);
  1300. mvpp2_write(priv, MVPP2_PRS_MAX_LOOP_REG(port), val);
  1301. /* Set initial offset for packet header extraction for the first
  1302. * searching loop
  1303. */
  1304. val = mvpp2_read(priv, MVPP2_PRS_INIT_OFFS_REG(port));
  1305. val &= ~MVPP2_PRS_INIT_OFF_MASK(port);
  1306. val |= MVPP2_PRS_INIT_OFF_VAL(port, offset);
  1307. mvpp2_write(priv, MVPP2_PRS_INIT_OFFS_REG(port), val);
  1308. }
  1309. /* Default flow entries initialization for all ports */
  1310. static void mvpp2_prs_def_flow_init(struct mvpp2 *priv)
  1311. {
  1312. struct mvpp2_prs_entry pe;
  1313. int port;
  1314. for (port = 0; port < MVPP2_MAX_PORTS; port++) {
  1315. memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
  1316. mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
  1317. pe.index = MVPP2_PE_FIRST_DEFAULT_FLOW - port;
  1318. /* Mask all ports */
  1319. mvpp2_prs_tcam_port_map_set(&pe, 0);
  1320. /* Set flow ID*/
  1321. mvpp2_prs_sram_ai_update(&pe, port, MVPP2_PRS_FLOW_ID_MASK);
  1322. mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_DONE_BIT, 1);
  1323. /* Update shadow table and hw entry */
  1324. mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_FLOWS);
  1325. mvpp2_prs_hw_write(priv, &pe);
  1326. }
  1327. }
  1328. /* Set default entry for Marvell Header field */
  1329. static void mvpp2_prs_mh_init(struct mvpp2 *priv)
  1330. {
  1331. struct mvpp2_prs_entry pe;
  1332. memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
  1333. pe.index = MVPP2_PE_MH_DEFAULT;
  1334. mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MH);
  1335. mvpp2_prs_sram_shift_set(&pe, MVPP2_MH_SIZE,
  1336. MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
  1337. mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_MAC);
  1338. /* Unmask all ports */
  1339. mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
  1340. /* Update shadow table and hw entry */
  1341. mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MH);
  1342. mvpp2_prs_hw_write(priv, &pe);
  1343. }
  1344. /* Set default entires (place holder) for promiscuous, non-promiscuous and
  1345. * multicast MAC addresses
  1346. */
  1347. static void mvpp2_prs_mac_init(struct mvpp2 *priv)
  1348. {
  1349. struct mvpp2_prs_entry pe;
  1350. memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
  1351. /* Non-promiscuous mode for all ports - DROP unknown packets */
  1352. pe.index = MVPP2_PE_MAC_NON_PROMISCUOUS;
  1353. mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);
  1354. mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DROP_MASK,
  1355. MVPP2_PRS_RI_DROP_MASK);
  1356. mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
  1357. mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
  1358. /* Unmask all ports */
  1359. mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
  1360. /* Update shadow table and hw entry */
  1361. mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
  1362. mvpp2_prs_hw_write(priv, &pe);
  1363. /* place holders only - no ports */
  1364. mvpp2_prs_mac_drop_all_set(priv, 0, false);
  1365. mvpp2_prs_mac_promisc_set(priv, 0, false);
  1366. mvpp2_prs_mac_multi_set(priv, MVPP2_PE_MAC_MC_ALL, 0, false);
  1367. mvpp2_prs_mac_multi_set(priv, MVPP2_PE_MAC_MC_IP6, 0, false);
  1368. }
  1369. /* Match basic ethertypes */
  1370. static int mvpp2_prs_etype_init(struct mvpp2 *priv)
  1371. {
  1372. struct mvpp2_prs_entry pe;
  1373. int tid;
  1374. /* Ethertype: PPPoE */
  1375. tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
  1376. MVPP2_PE_LAST_FREE_TID);
  1377. if (tid < 0)
  1378. return tid;
  1379. memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
  1380. mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
  1381. pe.index = tid;
  1382. mvpp2_prs_match_etype(&pe, 0, PROT_PPP_SES);
  1383. mvpp2_prs_sram_shift_set(&pe, MVPP2_PPPOE_HDR_SIZE,
  1384. MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
  1385. mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_PPPOE);
  1386. mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_PPPOE_MASK,
  1387. MVPP2_PRS_RI_PPPOE_MASK);
  1388. /* Update shadow table and hw entry */
  1389. mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
  1390. priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
  1391. priv->prs_shadow[pe.index].finish = false;
  1392. mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_PPPOE_MASK,
  1393. MVPP2_PRS_RI_PPPOE_MASK);
  1394. mvpp2_prs_hw_write(priv, &pe);
  1395. /* Ethertype: ARP */
  1396. tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
  1397. MVPP2_PE_LAST_FREE_TID);
  1398. if (tid < 0)
  1399. return tid;
  1400. memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
  1401. mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
  1402. pe.index = tid;
  1403. mvpp2_prs_match_etype(&pe, 0, PROT_ARP);
  1404. /* Generate flow in the next iteration*/
  1405. mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
  1406. mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
  1407. mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_ARP,
  1408. MVPP2_PRS_RI_L3_PROTO_MASK);
  1409. /* Set L3 offset */
  1410. mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
  1411. MVPP2_ETH_TYPE_LEN,
  1412. MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
  1413. /* Update shadow table and hw entry */
  1414. mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
  1415. priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
  1416. priv->prs_shadow[pe.index].finish = true;
  1417. mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_ARP,
  1418. MVPP2_PRS_RI_L3_PROTO_MASK);
  1419. mvpp2_prs_hw_write(priv, &pe);
  1420. /* Ethertype: LBTD */
  1421. tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
  1422. MVPP2_PE_LAST_FREE_TID);
  1423. if (tid < 0)
  1424. return tid;
  1425. memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
  1426. mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
  1427. pe.index = tid;
  1428. mvpp2_prs_match_etype(&pe, 0, MVPP2_IP_LBDT_TYPE);
  1429. /* Generate flow in the next iteration*/
  1430. mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
  1431. mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
  1432. mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_CPU_CODE_RX_SPEC |
  1433. MVPP2_PRS_RI_UDF3_RX_SPECIAL,
  1434. MVPP2_PRS_RI_CPU_CODE_MASK |
  1435. MVPP2_PRS_RI_UDF3_MASK);
  1436. /* Set L3 offset */
  1437. mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
  1438. MVPP2_ETH_TYPE_LEN,
  1439. MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
  1440. /* Update shadow table and hw entry */
  1441. mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
  1442. priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
  1443. priv->prs_shadow[pe.index].finish = true;
  1444. mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_CPU_CODE_RX_SPEC |
  1445. MVPP2_PRS_RI_UDF3_RX_SPECIAL,
  1446. MVPP2_PRS_RI_CPU_CODE_MASK |
  1447. MVPP2_PRS_RI_UDF3_MASK);
  1448. mvpp2_prs_hw_write(priv, &pe);
  1449. /* Ethertype: IPv4 without options */
  1450. tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
  1451. MVPP2_PE_LAST_FREE_TID);
  1452. if (tid < 0)
  1453. return tid;
  1454. memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
  1455. mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
  1456. pe.index = tid;
  1457. mvpp2_prs_match_etype(&pe, 0, PROT_IP);
  1458. mvpp2_prs_tcam_data_byte_set(&pe, MVPP2_ETH_TYPE_LEN,
  1459. MVPP2_PRS_IPV4_HEAD | MVPP2_PRS_IPV4_IHL,
  1460. MVPP2_PRS_IPV4_HEAD_MASK |
  1461. MVPP2_PRS_IPV4_IHL_MASK);
  1462. mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP4);
  1463. mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4,
  1464. MVPP2_PRS_RI_L3_PROTO_MASK);
  1465. /* Skip eth_type + 4 bytes of IP header */
  1466. mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 4,
  1467. MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
  1468. /* Set L3 offset */
  1469. mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
  1470. MVPP2_ETH_TYPE_LEN,
  1471. MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
  1472. /* Update shadow table and hw entry */
  1473. mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
  1474. priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
  1475. priv->prs_shadow[pe.index].finish = false;
  1476. mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP4,
  1477. MVPP2_PRS_RI_L3_PROTO_MASK);
  1478. mvpp2_prs_hw_write(priv, &pe);
  1479. /* Ethertype: IPv4 with options */
  1480. tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
  1481. MVPP2_PE_LAST_FREE_TID);
  1482. if (tid < 0)
  1483. return tid;
  1484. pe.index = tid;
  1485. /* Clear tcam data before updating */
  1486. pe.tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE(MVPP2_ETH_TYPE_LEN)] = 0x0;
  1487. pe.tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE_EN(MVPP2_ETH_TYPE_LEN)] = 0x0;
  1488. mvpp2_prs_tcam_data_byte_set(&pe, MVPP2_ETH_TYPE_LEN,
  1489. MVPP2_PRS_IPV4_HEAD,
  1490. MVPP2_PRS_IPV4_HEAD_MASK);
  1491. /* Clear ri before updating */
  1492. pe.sram.word[MVPP2_PRS_SRAM_RI_WORD] = 0x0;
  1493. pe.sram.word[MVPP2_PRS_SRAM_RI_CTRL_WORD] = 0x0;
  1494. mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4_OPT,
  1495. MVPP2_PRS_RI_L3_PROTO_MASK);
  1496. /* Update shadow table and hw entry */
  1497. mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
  1498. priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
  1499. priv->prs_shadow[pe.index].finish = false;
  1500. mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP4_OPT,
  1501. MVPP2_PRS_RI_L3_PROTO_MASK);
  1502. mvpp2_prs_hw_write(priv, &pe);
  1503. /* Ethertype: IPv6 without options */
  1504. tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
  1505. MVPP2_PE_LAST_FREE_TID);
  1506. if (tid < 0)
  1507. return tid;
  1508. memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
  1509. mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
  1510. pe.index = tid;
  1511. mvpp2_prs_match_etype(&pe, 0, PROT_IPV6);
  1512. /* Skip DIP of IPV6 header */
  1513. mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 8 +
  1514. MVPP2_MAX_L3_ADDR_SIZE,
  1515. MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
  1516. mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP6);
  1517. mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP6,
  1518. MVPP2_PRS_RI_L3_PROTO_MASK);
  1519. /* Set L3 offset */
  1520. mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
  1521. MVPP2_ETH_TYPE_LEN,
  1522. MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
  1523. mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
  1524. priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
  1525. priv->prs_shadow[pe.index].finish = false;
  1526. mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP6,
  1527. MVPP2_PRS_RI_L3_PROTO_MASK);
  1528. mvpp2_prs_hw_write(priv, &pe);
  1529. /* Default entry for MVPP2_PRS_LU_L2 - Unknown ethtype */
  1530. memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
  1531. mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
  1532. pe.index = MVPP2_PE_ETH_TYPE_UN;
  1533. /* Unmask all ports */
  1534. mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
  1535. /* Generate flow in the next iteration*/
  1536. mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
  1537. mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
  1538. mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UN,
  1539. MVPP2_PRS_RI_L3_PROTO_MASK);
  1540. /* Set L3 offset even it's unknown L3 */
  1541. mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
  1542. MVPP2_ETH_TYPE_LEN,
  1543. MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
  1544. /* Update shadow table and hw entry */
  1545. mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
  1546. priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
  1547. priv->prs_shadow[pe.index].finish = true;
  1548. mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_UN,
  1549. MVPP2_PRS_RI_L3_PROTO_MASK);
  1550. mvpp2_prs_hw_write(priv, &pe);
  1551. return 0;
  1552. }
  1553. /* Parser default initialization */
  1554. static int mvpp2_prs_default_init(struct udevice *dev,
  1555. struct mvpp2 *priv)
  1556. {
  1557. int err, index, i;
  1558. /* Enable tcam table */
  1559. mvpp2_write(priv, MVPP2_PRS_TCAM_CTRL_REG, MVPP2_PRS_TCAM_EN_MASK);
  1560. /* Clear all tcam and sram entries */
  1561. for (index = 0; index < MVPP2_PRS_TCAM_SRAM_SIZE; index++) {
  1562. mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, index);
  1563. for (i = 0; i < MVPP2_PRS_TCAM_WORDS; i++)
  1564. mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(i), 0);
  1565. mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, index);
  1566. for (i = 0; i < MVPP2_PRS_SRAM_WORDS; i++)
  1567. mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), 0);
  1568. }
  1569. /* Invalidate all tcam entries */
  1570. for (index = 0; index < MVPP2_PRS_TCAM_SRAM_SIZE; index++)
  1571. mvpp2_prs_hw_inv(priv, index);
  1572. priv->prs_shadow = devm_kcalloc(dev, MVPP2_PRS_TCAM_SRAM_SIZE,
  1573. sizeof(struct mvpp2_prs_shadow),
  1574. GFP_KERNEL);
  1575. if (!priv->prs_shadow)
  1576. return -ENOMEM;
  1577. /* Always start from lookup = 0 */
  1578. for (index = 0; index < MVPP2_MAX_PORTS; index++)
  1579. mvpp2_prs_hw_port_init(priv, index, MVPP2_PRS_LU_MH,
  1580. MVPP2_PRS_PORT_LU_MAX, 0);
  1581. mvpp2_prs_def_flow_init(priv);
  1582. mvpp2_prs_mh_init(priv);
  1583. mvpp2_prs_mac_init(priv);
  1584. err = mvpp2_prs_etype_init(priv);
  1585. if (err)
  1586. return err;
  1587. return 0;
  1588. }
  1589. /* Compare MAC DA with tcam entry data */
  1590. static bool mvpp2_prs_mac_range_equals(struct mvpp2_prs_entry *pe,
  1591. const u8 *da, unsigned char *mask)
  1592. {
  1593. unsigned char tcam_byte, tcam_mask;
  1594. int index;
  1595. for (index = 0; index < ETH_ALEN; index++) {
  1596. mvpp2_prs_tcam_data_byte_get(pe, index, &tcam_byte, &tcam_mask);
  1597. if (tcam_mask != mask[index])
  1598. return false;
  1599. if ((tcam_mask & tcam_byte) != (da[index] & mask[index]))
  1600. return false;
  1601. }
  1602. return true;
  1603. }
  1604. /* Find tcam entry with matched pair <MAC DA, port> */
  1605. static struct mvpp2_prs_entry *
  1606. mvpp2_prs_mac_da_range_find(struct mvpp2 *priv, int pmap, const u8 *da,
  1607. unsigned char *mask, int udf_type)
  1608. {
  1609. struct mvpp2_prs_entry *pe;
  1610. int tid;
  1611. pe = kzalloc(sizeof(*pe), GFP_KERNEL);
  1612. if (!pe)
  1613. return NULL;
  1614. mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_MAC);
  1615. /* Go through the all entires with MVPP2_PRS_LU_MAC */
  1616. for (tid = MVPP2_PE_FIRST_FREE_TID;
  1617. tid <= MVPP2_PE_LAST_FREE_TID; tid++) {
  1618. unsigned int entry_pmap;
  1619. if (!priv->prs_shadow[tid].valid ||
  1620. (priv->prs_shadow[tid].lu != MVPP2_PRS_LU_MAC) ||
  1621. (priv->prs_shadow[tid].udf != udf_type))
  1622. continue;
  1623. pe->index = tid;
  1624. mvpp2_prs_hw_read(priv, pe);
  1625. entry_pmap = mvpp2_prs_tcam_port_map_get(pe);
  1626. if (mvpp2_prs_mac_range_equals(pe, da, mask) &&
  1627. entry_pmap == pmap)
  1628. return pe;
  1629. }
  1630. kfree(pe);
  1631. return NULL;
  1632. }
  1633. /* Update parser's mac da entry */
  1634. static int mvpp2_prs_mac_da_accept(struct mvpp2 *priv, int port,
  1635. const u8 *da, bool add)
  1636. {
  1637. struct mvpp2_prs_entry *pe;
  1638. unsigned int pmap, len, ri;
  1639. unsigned char mask[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
  1640. int tid;
  1641. /* Scan TCAM and see if entry with this <MAC DA, port> already exist */
  1642. pe = mvpp2_prs_mac_da_range_find(priv, (1 << port), da, mask,
  1643. MVPP2_PRS_UDF_MAC_DEF);
  1644. /* No such entry */
  1645. if (!pe) {
  1646. if (!add)
  1647. return 0;
  1648. /* Create new TCAM entry */
  1649. /* Find first range mac entry*/
  1650. for (tid = MVPP2_PE_FIRST_FREE_TID;
  1651. tid <= MVPP2_PE_LAST_FREE_TID; tid++)
  1652. if (priv->prs_shadow[tid].valid &&
  1653. (priv->prs_shadow[tid].lu == MVPP2_PRS_LU_MAC) &&
  1654. (priv->prs_shadow[tid].udf ==
  1655. MVPP2_PRS_UDF_MAC_RANGE))
  1656. break;
  1657. /* Go through the all entries from first to last */
  1658. tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
  1659. tid - 1);
  1660. if (tid < 0)
  1661. return tid;
  1662. pe = kzalloc(sizeof(*pe), GFP_KERNEL);
  1663. if (!pe)
  1664. return -1;
  1665. mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_MAC);
  1666. pe->index = tid;
  1667. /* Mask all ports */
  1668. mvpp2_prs_tcam_port_map_set(pe, 0);
  1669. }
  1670. /* Update port mask */
  1671. mvpp2_prs_tcam_port_set(pe, port, add);
  1672. /* Invalidate the entry if no ports are left enabled */
  1673. pmap = mvpp2_prs_tcam_port_map_get(pe);
  1674. if (pmap == 0) {
  1675. if (add) {
  1676. kfree(pe);
  1677. return -1;
  1678. }
  1679. mvpp2_prs_hw_inv(priv, pe->index);
  1680. priv->prs_shadow[pe->index].valid = false;
  1681. kfree(pe);
  1682. return 0;
  1683. }
  1684. /* Continue - set next lookup */
  1685. mvpp2_prs_sram_next_lu_set(pe, MVPP2_PRS_LU_DSA);
  1686. /* Set match on DA */
  1687. len = ETH_ALEN;
  1688. while (len--)
  1689. mvpp2_prs_tcam_data_byte_set(pe, len, da[len], 0xff);
  1690. /* Set result info bits */
  1691. ri = MVPP2_PRS_RI_L2_UCAST | MVPP2_PRS_RI_MAC_ME_MASK;
  1692. mvpp2_prs_sram_ri_update(pe, ri, MVPP2_PRS_RI_L2_CAST_MASK |
  1693. MVPP2_PRS_RI_MAC_ME_MASK);
  1694. mvpp2_prs_shadow_ri_set(priv, pe->index, ri, MVPP2_PRS_RI_L2_CAST_MASK |
  1695. MVPP2_PRS_RI_MAC_ME_MASK);
  1696. /* Shift to ethertype */
  1697. mvpp2_prs_sram_shift_set(pe, 2 * ETH_ALEN,
  1698. MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
  1699. /* Update shadow table and hw entry */
  1700. priv->prs_shadow[pe->index].udf = MVPP2_PRS_UDF_MAC_DEF;
  1701. mvpp2_prs_shadow_set(priv, pe->index, MVPP2_PRS_LU_MAC);
  1702. mvpp2_prs_hw_write(priv, pe);
  1703. kfree(pe);
  1704. return 0;
  1705. }
  1706. static int mvpp2_prs_update_mac_da(struct mvpp2_port *port, const u8 *da)
  1707. {
  1708. int err;
  1709. /* Remove old parser entry */
  1710. err = mvpp2_prs_mac_da_accept(port->priv, port->id, port->dev_addr,
  1711. false);
  1712. if (err)
  1713. return err;
  1714. /* Add new parser entry */
  1715. err = mvpp2_prs_mac_da_accept(port->priv, port->id, da, true);
  1716. if (err)
  1717. return err;
  1718. /* Set addr in the device */
  1719. memcpy(port->dev_addr, da, ETH_ALEN);
  1720. return 0;
  1721. }
  1722. /* Set prs flow for the port */
  1723. static int mvpp2_prs_def_flow(struct mvpp2_port *port)
  1724. {
  1725. struct mvpp2_prs_entry *pe;
  1726. int tid;
  1727. pe = mvpp2_prs_flow_find(port->priv, port->id);
  1728. /* Such entry not exist */
  1729. if (!pe) {
  1730. /* Go through the all entires from last to first */
  1731. tid = mvpp2_prs_tcam_first_free(port->priv,
  1732. MVPP2_PE_LAST_FREE_TID,
  1733. MVPP2_PE_FIRST_FREE_TID);
  1734. if (tid < 0)
  1735. return tid;
  1736. pe = kzalloc(sizeof(*pe), GFP_KERNEL);
  1737. if (!pe)
  1738. return -ENOMEM;
  1739. mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_FLOWS);
  1740. pe->index = tid;
  1741. /* Set flow ID*/
  1742. mvpp2_prs_sram_ai_update(pe, port->id, MVPP2_PRS_FLOW_ID_MASK);
  1743. mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_LU_DONE_BIT, 1);
  1744. /* Update shadow table */
  1745. mvpp2_prs_shadow_set(port->priv, pe->index, MVPP2_PRS_LU_FLOWS);
  1746. }
  1747. mvpp2_prs_tcam_port_map_set(pe, (1 << port->id));
  1748. mvpp2_prs_hw_write(port->priv, pe);
  1749. kfree(pe);
  1750. return 0;
  1751. }
  1752. /* Classifier configuration routines */
  1753. /* Update classification flow table registers */
  1754. static void mvpp2_cls_flow_write(struct mvpp2 *priv,
  1755. struct mvpp2_cls_flow_entry *fe)
  1756. {
  1757. mvpp2_write(priv, MVPP2_CLS_FLOW_INDEX_REG, fe->index);
  1758. mvpp2_write(priv, MVPP2_CLS_FLOW_TBL0_REG, fe->data[0]);
  1759. mvpp2_write(priv, MVPP2_CLS_FLOW_TBL1_REG, fe->data[1]);
  1760. mvpp2_write(priv, MVPP2_CLS_FLOW_TBL2_REG, fe->data[2]);
  1761. }
  1762. /* Update classification lookup table register */
  1763. static void mvpp2_cls_lookup_write(struct mvpp2 *priv,
  1764. struct mvpp2_cls_lookup_entry *le)
  1765. {
  1766. u32 val;
  1767. val = (le->way << MVPP2_CLS_LKP_INDEX_WAY_OFFS) | le->lkpid;
  1768. mvpp2_write(priv, MVPP2_CLS_LKP_INDEX_REG, val);
  1769. mvpp2_write(priv, MVPP2_CLS_LKP_TBL_REG, le->data);
  1770. }
  1771. /* Classifier default initialization */
  1772. static void mvpp2_cls_init(struct mvpp2 *priv)
  1773. {
  1774. struct mvpp2_cls_lookup_entry le;
  1775. struct mvpp2_cls_flow_entry fe;
  1776. int index;
  1777. /* Enable classifier */
  1778. mvpp2_write(priv, MVPP2_CLS_MODE_REG, MVPP2_CLS_MODE_ACTIVE_MASK);
  1779. /* Clear classifier flow table */
  1780. memset(&fe.data, 0, MVPP2_CLS_FLOWS_TBL_DATA_WORDS);
  1781. for (index = 0; index < MVPP2_CLS_FLOWS_TBL_SIZE; index++) {
  1782. fe.index = index;
  1783. mvpp2_cls_flow_write(priv, &fe);
  1784. }
  1785. /* Clear classifier lookup table */
  1786. le.data = 0;
  1787. for (index = 0; index < MVPP2_CLS_LKP_TBL_SIZE; index++) {
  1788. le.lkpid = index;
  1789. le.way = 0;
  1790. mvpp2_cls_lookup_write(priv, &le);
  1791. le.way = 1;
  1792. mvpp2_cls_lookup_write(priv, &le);
  1793. }
  1794. }
  1795. static void mvpp2_cls_port_config(struct mvpp2_port *port)
  1796. {
  1797. struct mvpp2_cls_lookup_entry le;
  1798. u32 val;
  1799. /* Set way for the port */
  1800. val = mvpp2_read(port->priv, MVPP2_CLS_PORT_WAY_REG);
  1801. val &= ~MVPP2_CLS_PORT_WAY_MASK(port->id);
  1802. mvpp2_write(port->priv, MVPP2_CLS_PORT_WAY_REG, val);
  1803. /* Pick the entry to be accessed in lookup ID decoding table
  1804. * according to the way and lkpid.
  1805. */
  1806. le.lkpid = port->id;
  1807. le.way = 0;
  1808. le.data = 0;
  1809. /* Set initial CPU queue for receiving packets */
  1810. le.data &= ~MVPP2_CLS_LKP_TBL_RXQ_MASK;
  1811. le.data |= port->first_rxq;
  1812. /* Disable classification engines */
  1813. le.data &= ~MVPP2_CLS_LKP_TBL_LOOKUP_EN_MASK;
  1814. /* Update lookup ID table entry */
  1815. mvpp2_cls_lookup_write(port->priv, &le);
  1816. }
  1817. /* Set CPU queue number for oversize packets */
  1818. static void mvpp2_cls_oversize_rxq_set(struct mvpp2_port *port)
  1819. {
  1820. u32 val;
  1821. mvpp2_write(port->priv, MVPP2_CLS_OVERSIZE_RXQ_LOW_REG(port->id),
  1822. port->first_rxq & MVPP2_CLS_OVERSIZE_RXQ_LOW_MASK);
  1823. mvpp2_write(port->priv, MVPP2_CLS_SWFWD_P2HQ_REG(port->id),
  1824. (port->first_rxq >> MVPP2_CLS_OVERSIZE_RXQ_LOW_BITS));
  1825. val = mvpp2_read(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG);
  1826. val |= MVPP2_CLS_SWFWD_PCTRL_MASK(port->id);
  1827. mvpp2_write(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG, val);
  1828. }
  1829. /* Buffer Manager configuration routines */
  1830. /* Create pool */
  1831. static int mvpp2_bm_pool_create(struct udevice *dev,
  1832. struct mvpp2 *priv,
  1833. struct mvpp2_bm_pool *bm_pool, int size)
  1834. {
  1835. u32 val;
  1836. bm_pool->virt_addr = buffer_loc.bm_pool[bm_pool->id];
  1837. bm_pool->phys_addr = (dma_addr_t)buffer_loc.bm_pool[bm_pool->id];
  1838. if (!bm_pool->virt_addr)
  1839. return -ENOMEM;
  1840. if (!IS_ALIGNED((u32)bm_pool->virt_addr, MVPP2_BM_POOL_PTR_ALIGN)) {
  1841. dev_err(&pdev->dev, "BM pool %d is not %d bytes aligned\n",
  1842. bm_pool->id, MVPP2_BM_POOL_PTR_ALIGN);
  1843. return -ENOMEM;
  1844. }
  1845. mvpp2_write(priv, MVPP2_BM_POOL_BASE_REG(bm_pool->id),
  1846. bm_pool->phys_addr);
  1847. mvpp2_write(priv, MVPP2_BM_POOL_SIZE_REG(bm_pool->id), size);
  1848. val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id));
  1849. val |= MVPP2_BM_START_MASK;
  1850. mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val);
  1851. bm_pool->type = MVPP2_BM_FREE;
  1852. bm_pool->size = size;
  1853. bm_pool->pkt_size = 0;
  1854. bm_pool->buf_num = 0;
  1855. return 0;
  1856. }
  1857. /* Set pool buffer size */
  1858. static void mvpp2_bm_pool_bufsize_set(struct mvpp2 *priv,
  1859. struct mvpp2_bm_pool *bm_pool,
  1860. int buf_size)
  1861. {
  1862. u32 val;
  1863. bm_pool->buf_size = buf_size;
  1864. val = ALIGN(buf_size, 1 << MVPP2_POOL_BUF_SIZE_OFFSET);
  1865. mvpp2_write(priv, MVPP2_POOL_BUF_SIZE_REG(bm_pool->id), val);
  1866. }
  1867. /* Free all buffers from the pool */
  1868. static void mvpp2_bm_bufs_free(struct udevice *dev, struct mvpp2 *priv,
  1869. struct mvpp2_bm_pool *bm_pool)
  1870. {
  1871. bm_pool->buf_num = 0;
  1872. }
  1873. /* Cleanup pool */
  1874. static int mvpp2_bm_pool_destroy(struct udevice *dev,
  1875. struct mvpp2 *priv,
  1876. struct mvpp2_bm_pool *bm_pool)
  1877. {
  1878. u32 val;
  1879. mvpp2_bm_bufs_free(dev, priv, bm_pool);
  1880. if (bm_pool->buf_num) {
  1881. dev_err(dev, "cannot free all buffers in pool %d\n", bm_pool->id);
  1882. return 0;
  1883. }
  1884. val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id));
  1885. val |= MVPP2_BM_STOP_MASK;
  1886. mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val);
  1887. return 0;
  1888. }
  1889. static int mvpp2_bm_pools_init(struct udevice *dev,
  1890. struct mvpp2 *priv)
  1891. {
  1892. int i, err, size;
  1893. struct mvpp2_bm_pool *bm_pool;
  1894. /* Create all pools with maximum size */
  1895. size = MVPP2_BM_POOL_SIZE_MAX;
  1896. for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) {
  1897. bm_pool = &priv->bm_pools[i];
  1898. bm_pool->id = i;
  1899. err = mvpp2_bm_pool_create(dev, priv, bm_pool, size);
  1900. if (err)
  1901. goto err_unroll_pools;
  1902. mvpp2_bm_pool_bufsize_set(priv, bm_pool, 0);
  1903. }
  1904. return 0;
  1905. err_unroll_pools:
  1906. dev_err(&pdev->dev, "failed to create BM pool %d, size %d\n", i, size);
  1907. for (i = i - 1; i >= 0; i--)
  1908. mvpp2_bm_pool_destroy(dev, priv, &priv->bm_pools[i]);
  1909. return err;
  1910. }
  1911. static int mvpp2_bm_init(struct udevice *dev, struct mvpp2 *priv)
  1912. {
  1913. int i, err;
  1914. for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) {
  1915. /* Mask BM all interrupts */
  1916. mvpp2_write(priv, MVPP2_BM_INTR_MASK_REG(i), 0);
  1917. /* Clear BM cause register */
  1918. mvpp2_write(priv, MVPP2_BM_INTR_CAUSE_REG(i), 0);
  1919. }
  1920. /* Allocate and initialize BM pools */
  1921. priv->bm_pools = devm_kcalloc(dev, MVPP2_BM_POOLS_NUM,
  1922. sizeof(struct mvpp2_bm_pool), GFP_KERNEL);
  1923. if (!priv->bm_pools)
  1924. return -ENOMEM;
  1925. err = mvpp2_bm_pools_init(dev, priv);
  1926. if (err < 0)
  1927. return err;
  1928. return 0;
  1929. }
  1930. /* Attach long pool to rxq */
  1931. static void mvpp2_rxq_long_pool_set(struct mvpp2_port *port,
  1932. int lrxq, int long_pool)
  1933. {
  1934. u32 val;
  1935. int prxq;
  1936. /* Get queue physical ID */
  1937. prxq = port->rxqs[lrxq]->id;
  1938. val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));
  1939. val &= ~MVPP2_RXQ_POOL_LONG_MASK;
  1940. val |= ((long_pool << MVPP2_RXQ_POOL_LONG_OFFS) &
  1941. MVPP2_RXQ_POOL_LONG_MASK);
  1942. mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);
  1943. }
  1944. /* Set pool number in a BM cookie */
  1945. static inline u32 mvpp2_bm_cookie_pool_set(u32 cookie, int pool)
  1946. {
  1947. u32 bm;
  1948. bm = cookie & ~(0xFF << MVPP2_BM_COOKIE_POOL_OFFS);
  1949. bm |= ((pool & 0xFF) << MVPP2_BM_COOKIE_POOL_OFFS);
  1950. return bm;
  1951. }
  1952. /* Get pool number from a BM cookie */
  1953. static inline int mvpp2_bm_cookie_pool_get(u32 cookie)
  1954. {
  1955. return (cookie >> MVPP2_BM_COOKIE_POOL_OFFS) & 0xFF;
  1956. }
  1957. /* Release buffer to BM */
  1958. static inline void mvpp2_bm_pool_put(struct mvpp2_port *port, int pool,
  1959. u32 buf_phys_addr, u32 buf_virt_addr)
  1960. {
  1961. mvpp2_write(port->priv, MVPP2_BM_VIRT_RLS_REG, buf_virt_addr);
  1962. mvpp2_write(port->priv, MVPP2_BM_PHY_RLS_REG(pool), buf_phys_addr);
  1963. }
  1964. /* Refill BM pool */
  1965. static void mvpp2_pool_refill(struct mvpp2_port *port, u32 bm,
  1966. u32 phys_addr, u32 cookie)
  1967. {
  1968. int pool = mvpp2_bm_cookie_pool_get(bm);
  1969. mvpp2_bm_pool_put(port, pool, phys_addr, cookie);
  1970. }
  1971. /* Allocate buffers for the pool */
  1972. static int mvpp2_bm_bufs_add(struct mvpp2_port *port,
  1973. struct mvpp2_bm_pool *bm_pool, int buf_num)
  1974. {
  1975. int i;
  1976. if (buf_num < 0 ||
  1977. (buf_num + bm_pool->buf_num > bm_pool->size)) {
  1978. netdev_err(port->dev,
  1979. "cannot allocate %d buffers for pool %d\n",
  1980. buf_num, bm_pool->id);
  1981. return 0;
  1982. }
  1983. for (i = 0; i < buf_num; i++) {
  1984. mvpp2_bm_pool_put(port, bm_pool->id,
  1985. (u32)buffer_loc.rx_buffer[i],
  1986. (u32)buffer_loc.rx_buffer[i]);
  1987. }
  1988. /* Update BM driver with number of buffers added to pool */
  1989. bm_pool->buf_num += i;
  1990. bm_pool->in_use_thresh = bm_pool->buf_num / 4;
  1991. return i;
  1992. }
  1993. /* Notify the driver that BM pool is being used as specific type and return the
  1994. * pool pointer on success
  1995. */
  1996. static struct mvpp2_bm_pool *
  1997. mvpp2_bm_pool_use(struct mvpp2_port *port, int pool, enum mvpp2_bm_type type,
  1998. int pkt_size)
  1999. {
  2000. struct mvpp2_bm_pool *new_pool = &port->priv->bm_pools[pool];
  2001. int num;
  2002. if (new_pool->type != MVPP2_BM_FREE && new_pool->type != type) {
  2003. netdev_err(port->dev, "mixing pool types is forbidden\n");
  2004. return NULL;
  2005. }
  2006. if (new_pool->type == MVPP2_BM_FREE)
  2007. new_pool->type = type;
  2008. /* Allocate buffers in case BM pool is used as long pool, but packet
  2009. * size doesn't match MTU or BM pool hasn't being used yet
  2010. */
  2011. if (((type == MVPP2_BM_SWF_LONG) && (pkt_size > new_pool->pkt_size)) ||
  2012. (new_pool->pkt_size == 0)) {
  2013. int pkts_num;
  2014. /* Set default buffer number or free all the buffers in case
  2015. * the pool is not empty
  2016. */
  2017. pkts_num = new_pool->buf_num;
  2018. if (pkts_num == 0)
  2019. pkts_num = type == MVPP2_BM_SWF_LONG ?
  2020. MVPP2_BM_LONG_BUF_NUM :
  2021. MVPP2_BM_SHORT_BUF_NUM;
  2022. else
  2023. mvpp2_bm_bufs_free(NULL,
  2024. port->priv, new_pool);
  2025. new_pool->pkt_size = pkt_size;
  2026. /* Allocate buffers for this pool */
  2027. num = mvpp2_bm_bufs_add(port, new_pool, pkts_num);
  2028. if (num != pkts_num) {
  2029. dev_err(dev, "pool %d: %d of %d allocated\n",
  2030. new_pool->id, num, pkts_num);
  2031. return NULL;
  2032. }
  2033. }
  2034. mvpp2_bm_pool_bufsize_set(port->priv, new_pool,
  2035. MVPP2_RX_BUF_SIZE(new_pool->pkt_size));
  2036. return new_pool;
  2037. }
  2038. /* Initialize pools for swf */
  2039. static int mvpp2_swf_bm_pool_init(struct mvpp2_port *port)
  2040. {
  2041. int rxq;
  2042. if (!port->pool_long) {
  2043. port->pool_long =
  2044. mvpp2_bm_pool_use(port, MVPP2_BM_SWF_LONG_POOL(port->id),
  2045. MVPP2_BM_SWF_LONG,
  2046. port->pkt_size);
  2047. if (!port->pool_long)
  2048. return -ENOMEM;
  2049. port->pool_long->port_map |= (1 << port->id);
  2050. for (rxq = 0; rxq < rxq_number; rxq++)
  2051. mvpp2_rxq_long_pool_set(port, rxq, port->pool_long->id);
  2052. }
  2053. return 0;
  2054. }
  2055. /* Port configuration routines */
  2056. static void mvpp2_port_mii_set(struct mvpp2_port *port)
  2057. {
  2058. u32 val;
  2059. val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
  2060. switch (port->phy_interface) {
  2061. case PHY_INTERFACE_MODE_SGMII:
  2062. val |= MVPP2_GMAC_INBAND_AN_MASK;
  2063. break;
  2064. case PHY_INTERFACE_MODE_RGMII:
  2065. val |= MVPP2_GMAC_PORT_RGMII_MASK;
  2066. default:
  2067. val &= ~MVPP2_GMAC_PCS_ENABLE_MASK;
  2068. }
  2069. writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
  2070. }
  2071. static void mvpp2_port_fc_adv_enable(struct mvpp2_port *port)
  2072. {
  2073. u32 val;
  2074. val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
  2075. val |= MVPP2_GMAC_FC_ADV_EN;
  2076. writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
  2077. }
  2078. static void mvpp2_port_enable(struct mvpp2_port *port)
  2079. {
  2080. u32 val;
  2081. val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
  2082. val |= MVPP2_GMAC_PORT_EN_MASK;
  2083. val |= MVPP2_GMAC_MIB_CNTR_EN_MASK;
  2084. writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
  2085. }
  2086. static void mvpp2_port_disable(struct mvpp2_port *port)
  2087. {
  2088. u32 val;
  2089. val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
  2090. val &= ~(MVPP2_GMAC_PORT_EN_MASK);
  2091. writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
  2092. }
  2093. /* Set IEEE 802.3x Flow Control Xon Packet Transmission Mode */
  2094. static void mvpp2_port_periodic_xon_disable(struct mvpp2_port *port)
  2095. {
  2096. u32 val;
  2097. val = readl(port->base + MVPP2_GMAC_CTRL_1_REG) &
  2098. ~MVPP2_GMAC_PERIODIC_XON_EN_MASK;
  2099. writel(val, port->base + MVPP2_GMAC_CTRL_1_REG);
  2100. }
  2101. /* Configure loopback port */
  2102. static void mvpp2_port_loopback_set(struct mvpp2_port *port)
  2103. {
  2104. u32 val;
  2105. val = readl(port->base + MVPP2_GMAC_CTRL_1_REG);
  2106. if (port->speed == 1000)
  2107. val |= MVPP2_GMAC_GMII_LB_EN_MASK;
  2108. else
  2109. val &= ~MVPP2_GMAC_GMII_LB_EN_MASK;
  2110. if (port->phy_interface == PHY_INTERFACE_MODE_SGMII)
  2111. val |= MVPP2_GMAC_PCS_LB_EN_MASK;
  2112. else
  2113. val &= ~MVPP2_GMAC_PCS_LB_EN_MASK;
  2114. writel(val, port->base + MVPP2_GMAC_CTRL_1_REG);
  2115. }
  2116. static void mvpp2_port_reset(struct mvpp2_port *port)
  2117. {
  2118. u32 val;
  2119. val = readl(port->base + MVPP2_GMAC_CTRL_2_REG) &
  2120. ~MVPP2_GMAC_PORT_RESET_MASK;
  2121. writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
  2122. while (readl(port->base + MVPP2_GMAC_CTRL_2_REG) &
  2123. MVPP2_GMAC_PORT_RESET_MASK)
  2124. continue;
  2125. }
  2126. /* Change maximum receive size of the port */
  2127. static inline void mvpp2_gmac_max_rx_size_set(struct mvpp2_port *port)
  2128. {
  2129. u32 val;
  2130. val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
  2131. val &= ~MVPP2_GMAC_MAX_RX_SIZE_MASK;
  2132. val |= (((port->pkt_size - MVPP2_MH_SIZE) / 2) <<
  2133. MVPP2_GMAC_MAX_RX_SIZE_OFFS);
  2134. writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
  2135. }
  2136. /* Set defaults to the MVPP2 port */
  2137. static void mvpp2_defaults_set(struct mvpp2_port *port)
  2138. {
  2139. int tx_port_num, val, queue, ptxq, lrxq;
  2140. /* Configure port to loopback if needed */
  2141. if (port->flags & MVPP2_F_LOOPBACK)
  2142. mvpp2_port_loopback_set(port);
  2143. /* Update TX FIFO MIN Threshold */
  2144. val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
  2145. val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK;
  2146. /* Min. TX threshold must be less than minimal packet length */
  2147. val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(64 - 4 - 2);
  2148. writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
  2149. /* Disable Legacy WRR, Disable EJP, Release from reset */
  2150. tx_port_num = mvpp2_egress_port(port);
  2151. mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG,
  2152. tx_port_num);
  2153. mvpp2_write(port->priv, MVPP2_TXP_SCHED_CMD_1_REG, 0);
  2154. /* Close bandwidth for all queues */
  2155. for (queue = 0; queue < MVPP2_MAX_TXQ; queue++) {
  2156. ptxq = mvpp2_txq_phys(port->id, queue);
  2157. mvpp2_write(port->priv,
  2158. MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(ptxq), 0);
  2159. }
  2160. /* Set refill period to 1 usec, refill tokens
  2161. * and bucket size to maximum
  2162. */
  2163. mvpp2_write(port->priv, MVPP2_TXP_SCHED_PERIOD_REG, 0xc8);
  2164. val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_REFILL_REG);
  2165. val &= ~MVPP2_TXP_REFILL_PERIOD_ALL_MASK;
  2166. val |= MVPP2_TXP_REFILL_PERIOD_MASK(1);
  2167. val |= MVPP2_TXP_REFILL_TOKENS_ALL_MASK;
  2168. mvpp2_write(port->priv, MVPP2_TXP_SCHED_REFILL_REG, val);
  2169. val = MVPP2_TXP_TOKEN_SIZE_MAX;
  2170. mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val);
  2171. /* Set MaximumLowLatencyPacketSize value to 256 */
  2172. mvpp2_write(port->priv, MVPP2_RX_CTRL_REG(port->id),
  2173. MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK |
  2174. MVPP2_RX_LOW_LATENCY_PKT_SIZE(256));
  2175. /* Enable Rx cache snoop */
  2176. for (lrxq = 0; lrxq < rxq_number; lrxq++) {
  2177. queue = port->rxqs[lrxq]->id;
  2178. val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
  2179. val |= MVPP2_SNOOP_PKT_SIZE_MASK |
  2180. MVPP2_SNOOP_BUF_HDR_MASK;
  2181. mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
  2182. }
  2183. }
  2184. /* Enable/disable receiving packets */
  2185. static void mvpp2_ingress_enable(struct mvpp2_port *port)
  2186. {
  2187. u32 val;
  2188. int lrxq, queue;
  2189. for (lrxq = 0; lrxq < rxq_number; lrxq++) {
  2190. queue = port->rxqs[lrxq]->id;
  2191. val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
  2192. val &= ~MVPP2_RXQ_DISABLE_MASK;
  2193. mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
  2194. }
  2195. }
  2196. static void mvpp2_ingress_disable(struct mvpp2_port *port)
  2197. {
  2198. u32 val;
  2199. int lrxq, queue;
  2200. for (lrxq = 0; lrxq < rxq_number; lrxq++) {
  2201. queue = port->rxqs[lrxq]->id;
  2202. val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
  2203. val |= MVPP2_RXQ_DISABLE_MASK;
  2204. mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
  2205. }
  2206. }
  2207. /* Enable transmit via physical egress queue
  2208. * - HW starts take descriptors from DRAM
  2209. */
  2210. static void mvpp2_egress_enable(struct mvpp2_port *port)
  2211. {
  2212. u32 qmap;
  2213. int queue;
  2214. int tx_port_num = mvpp2_egress_port(port);
  2215. /* Enable all initialized TXs. */
  2216. qmap = 0;
  2217. for (queue = 0; queue < txq_number; queue++) {
  2218. struct mvpp2_tx_queue *txq = port->txqs[queue];
  2219. if (txq->descs != NULL)
  2220. qmap |= (1 << queue);
  2221. }
  2222. mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
  2223. mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG, qmap);
  2224. }
  2225. /* Disable transmit via physical egress queue
  2226. * - HW doesn't take descriptors from DRAM
  2227. */
  2228. static void mvpp2_egress_disable(struct mvpp2_port *port)
  2229. {
  2230. u32 reg_data;
  2231. int delay;
  2232. int tx_port_num = mvpp2_egress_port(port);
  2233. /* Issue stop command for active channels only */
  2234. mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
  2235. reg_data = (mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG)) &
  2236. MVPP2_TXP_SCHED_ENQ_MASK;
  2237. if (reg_data != 0)
  2238. mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG,
  2239. (reg_data << MVPP2_TXP_SCHED_DISQ_OFFSET));
  2240. /* Wait for all Tx activity to terminate. */
  2241. delay = 0;
  2242. do {
  2243. if (delay >= MVPP2_TX_DISABLE_TIMEOUT_MSEC) {
  2244. netdev_warn(port->dev,
  2245. "Tx stop timed out, status=0x%08x\n",
  2246. reg_data);
  2247. break;
  2248. }
  2249. mdelay(1);
  2250. delay++;
  2251. /* Check port TX Command register that all
  2252. * Tx queues are stopped
  2253. */
  2254. reg_data = mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG);
  2255. } while (reg_data & MVPP2_TXP_SCHED_ENQ_MASK);
  2256. }
  2257. /* Rx descriptors helper methods */
  2258. /* Get number of Rx descriptors occupied by received packets */
  2259. static inline int
  2260. mvpp2_rxq_received(struct mvpp2_port *port, int rxq_id)
  2261. {
  2262. u32 val = mvpp2_read(port->priv, MVPP2_RXQ_STATUS_REG(rxq_id));
  2263. return val & MVPP2_RXQ_OCCUPIED_MASK;
  2264. }
  2265. /* Update Rx queue status with the number of occupied and available
  2266. * Rx descriptor slots.
  2267. */
  2268. static inline void
  2269. mvpp2_rxq_status_update(struct mvpp2_port *port, int rxq_id,
  2270. int used_count, int free_count)
  2271. {
  2272. /* Decrement the number of used descriptors and increment count
  2273. * increment the number of free descriptors.
  2274. */
  2275. u32 val = used_count | (free_count << MVPP2_RXQ_NUM_NEW_OFFSET);
  2276. mvpp2_write(port->priv, MVPP2_RXQ_STATUS_UPDATE_REG(rxq_id), val);
  2277. }
  2278. /* Get pointer to next RX descriptor to be processed by SW */
  2279. static inline struct mvpp2_rx_desc *
  2280. mvpp2_rxq_next_desc_get(struct mvpp2_rx_queue *rxq)
  2281. {
  2282. int rx_desc = rxq->next_desc_to_proc;
  2283. rxq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(rxq, rx_desc);
  2284. prefetch(rxq->descs + rxq->next_desc_to_proc);
  2285. return rxq->descs + rx_desc;
  2286. }
  2287. /* Set rx queue offset */
  2288. static void mvpp2_rxq_offset_set(struct mvpp2_port *port,
  2289. int prxq, int offset)
  2290. {
  2291. u32 val;
  2292. /* Convert offset from bytes to units of 32 bytes */
  2293. offset = offset >> 5;
  2294. val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));
  2295. val &= ~MVPP2_RXQ_PACKET_OFFSET_MASK;
  2296. /* Offset is in */
  2297. val |= ((offset << MVPP2_RXQ_PACKET_OFFSET_OFFS) &
  2298. MVPP2_RXQ_PACKET_OFFSET_MASK);
  2299. mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);
  2300. }
  2301. /* Obtain BM cookie information from descriptor */
  2302. static u32 mvpp2_bm_cookie_build(struct mvpp2_rx_desc *rx_desc)
  2303. {
  2304. int pool = (rx_desc->status & MVPP2_RXD_BM_POOL_ID_MASK) >>
  2305. MVPP2_RXD_BM_POOL_ID_OFFS;
  2306. int cpu = smp_processor_id();
  2307. return ((pool & 0xFF) << MVPP2_BM_COOKIE_POOL_OFFS) |
  2308. ((cpu & 0xFF) << MVPP2_BM_COOKIE_CPU_OFFS);
  2309. }
  2310. /* Tx descriptors helper methods */
  2311. /* Get number of Tx descriptors waiting to be transmitted by HW */
  2312. static int mvpp2_txq_pend_desc_num_get(struct mvpp2_port *port,
  2313. struct mvpp2_tx_queue *txq)
  2314. {
  2315. u32 val;
  2316. mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
  2317. val = mvpp2_read(port->priv, MVPP2_TXQ_PENDING_REG);
  2318. return val & MVPP2_TXQ_PENDING_MASK;
  2319. }
  2320. /* Get pointer to next Tx descriptor to be processed (send) by HW */
  2321. static struct mvpp2_tx_desc *
  2322. mvpp2_txq_next_desc_get(struct mvpp2_tx_queue *txq)
  2323. {
  2324. int tx_desc = txq->next_desc_to_proc;
  2325. txq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(txq, tx_desc);
  2326. return txq->descs + tx_desc;
  2327. }
  2328. /* Update HW with number of aggregated Tx descriptors to be sent */
  2329. static void mvpp2_aggr_txq_pend_desc_add(struct mvpp2_port *port, int pending)
  2330. {
  2331. /* aggregated access - relevant TXQ number is written in TX desc */
  2332. mvpp2_write(port->priv, MVPP2_AGGR_TXQ_UPDATE_REG, pending);
  2333. }
  2334. /* Get number of sent descriptors and decrement counter.
  2335. * The number of sent descriptors is returned.
  2336. * Per-CPU access
  2337. */
  2338. static inline int mvpp2_txq_sent_desc_proc(struct mvpp2_port *port,
  2339. struct mvpp2_tx_queue *txq)
  2340. {
  2341. u32 val;
  2342. /* Reading status reg resets transmitted descriptor counter */
  2343. val = mvpp2_read(port->priv, MVPP2_TXQ_SENT_REG(txq->id));
  2344. return (val & MVPP2_TRANSMITTED_COUNT_MASK) >>
  2345. MVPP2_TRANSMITTED_COUNT_OFFSET;
  2346. }
  2347. static void mvpp2_txq_sent_counter_clear(void *arg)
  2348. {
  2349. struct mvpp2_port *port = arg;
  2350. int queue;
  2351. for (queue = 0; queue < txq_number; queue++) {
  2352. int id = port->txqs[queue]->id;
  2353. mvpp2_read(port->priv, MVPP2_TXQ_SENT_REG(id));
  2354. }
  2355. }
  2356. /* Set max sizes for Tx queues */
  2357. static void mvpp2_txp_max_tx_size_set(struct mvpp2_port *port)
  2358. {
  2359. u32 val, size, mtu;
  2360. int txq, tx_port_num;
  2361. mtu = port->pkt_size * 8;
  2362. if (mtu > MVPP2_TXP_MTU_MAX)
  2363. mtu = MVPP2_TXP_MTU_MAX;
  2364. /* WA for wrong Token bucket update: Set MTU value = 3*real MTU value */
  2365. mtu = 3 * mtu;
  2366. /* Indirect access to registers */
  2367. tx_port_num = mvpp2_egress_port(port);
  2368. mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
  2369. /* Set MTU */
  2370. val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_MTU_REG);
  2371. val &= ~MVPP2_TXP_MTU_MAX;
  2372. val |= mtu;
  2373. mvpp2_write(port->priv, MVPP2_TXP_SCHED_MTU_REG, val);
  2374. /* TXP token size and all TXQs token size must be larger that MTU */
  2375. val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG);
  2376. size = val & MVPP2_TXP_TOKEN_SIZE_MAX;
  2377. if (size < mtu) {
  2378. size = mtu;
  2379. val &= ~MVPP2_TXP_TOKEN_SIZE_MAX;
  2380. val |= size;
  2381. mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val);
  2382. }
  2383. for (txq = 0; txq < txq_number; txq++) {
  2384. val = mvpp2_read(port->priv,
  2385. MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq));
  2386. size = val & MVPP2_TXQ_TOKEN_SIZE_MAX;
  2387. if (size < mtu) {
  2388. size = mtu;
  2389. val &= ~MVPP2_TXQ_TOKEN_SIZE_MAX;
  2390. val |= size;
  2391. mvpp2_write(port->priv,
  2392. MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq),
  2393. val);
  2394. }
  2395. }
  2396. }
  2397. /* Free Tx queue skbuffs */
  2398. static void mvpp2_txq_bufs_free(struct mvpp2_port *port,
  2399. struct mvpp2_tx_queue *txq,
  2400. struct mvpp2_txq_pcpu *txq_pcpu, int num)
  2401. {
  2402. int i;
  2403. for (i = 0; i < num; i++)
  2404. mvpp2_txq_inc_get(txq_pcpu);
  2405. }
  2406. static inline struct mvpp2_rx_queue *mvpp2_get_rx_queue(struct mvpp2_port *port,
  2407. u32 cause)
  2408. {
  2409. int queue = fls(cause) - 1;
  2410. return port->rxqs[queue];
  2411. }
  2412. static inline struct mvpp2_tx_queue *mvpp2_get_tx_queue(struct mvpp2_port *port,
  2413. u32 cause)
  2414. {
  2415. int queue = fls(cause) - 1;
  2416. return port->txqs[queue];
  2417. }
  2418. /* Rx/Tx queue initialization/cleanup methods */
  2419. /* Allocate and initialize descriptors for aggr TXQ */
  2420. static int mvpp2_aggr_txq_init(struct udevice *dev,
  2421. struct mvpp2_tx_queue *aggr_txq,
  2422. int desc_num, int cpu,
  2423. struct mvpp2 *priv)
  2424. {
  2425. /* Allocate memory for TX descriptors */
  2426. aggr_txq->descs = buffer_loc.aggr_tx_descs;
  2427. aggr_txq->descs_phys = (dma_addr_t)buffer_loc.aggr_tx_descs;
  2428. if (!aggr_txq->descs)
  2429. return -ENOMEM;
  2430. /* Make sure descriptor address is cache line size aligned */
  2431. BUG_ON(aggr_txq->descs !=
  2432. PTR_ALIGN(aggr_txq->descs, MVPP2_CPU_D_CACHE_LINE_SIZE));
  2433. aggr_txq->last_desc = aggr_txq->size - 1;
  2434. /* Aggr TXQ no reset WA */
  2435. aggr_txq->next_desc_to_proc = mvpp2_read(priv,
  2436. MVPP2_AGGR_TXQ_INDEX_REG(cpu));
  2437. /* Set Tx descriptors queue starting address */
  2438. /* indirect access */
  2439. mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_ADDR_REG(cpu),
  2440. aggr_txq->descs_phys);
  2441. mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_SIZE_REG(cpu), desc_num);
  2442. return 0;
  2443. }
  2444. /* Create a specified Rx queue */
  2445. static int mvpp2_rxq_init(struct mvpp2_port *port,
  2446. struct mvpp2_rx_queue *rxq)
  2447. {
  2448. rxq->size = port->rx_ring_size;
  2449. /* Allocate memory for RX descriptors */
  2450. rxq->descs = buffer_loc.rx_descs;
  2451. rxq->descs_phys = (dma_addr_t)buffer_loc.rx_descs;
  2452. if (!rxq->descs)
  2453. return -ENOMEM;
  2454. BUG_ON(rxq->descs !=
  2455. PTR_ALIGN(rxq->descs, MVPP2_CPU_D_CACHE_LINE_SIZE));
  2456. rxq->last_desc = rxq->size - 1;
  2457. /* Zero occupied and non-occupied counters - direct access */
  2458. mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0);
  2459. /* Set Rx descriptors queue starting address - indirect access */
  2460. mvpp2_write(port->priv, MVPP2_RXQ_NUM_REG, rxq->id);
  2461. mvpp2_write(port->priv, MVPP2_RXQ_DESC_ADDR_REG, rxq->descs_phys);
  2462. mvpp2_write(port->priv, MVPP2_RXQ_DESC_SIZE_REG, rxq->size);
  2463. mvpp2_write(port->priv, MVPP2_RXQ_INDEX_REG, 0);
  2464. /* Set Offset */
  2465. mvpp2_rxq_offset_set(port, rxq->id, NET_SKB_PAD);
  2466. /* Add number of descriptors ready for receiving packets */
  2467. mvpp2_rxq_status_update(port, rxq->id, 0, rxq->size);
  2468. return 0;
  2469. }
  2470. /* Push packets received by the RXQ to BM pool */
  2471. static void mvpp2_rxq_drop_pkts(struct mvpp2_port *port,
  2472. struct mvpp2_rx_queue *rxq)
  2473. {
  2474. int rx_received, i;
  2475. rx_received = mvpp2_rxq_received(port, rxq->id);
  2476. if (!rx_received)
  2477. return;
  2478. for (i = 0; i < rx_received; i++) {
  2479. struct mvpp2_rx_desc *rx_desc = mvpp2_rxq_next_desc_get(rxq);
  2480. u32 bm = mvpp2_bm_cookie_build(rx_desc);
  2481. mvpp2_pool_refill(port, bm, rx_desc->buf_phys_addr,
  2482. rx_desc->buf_cookie);
  2483. }
  2484. mvpp2_rxq_status_update(port, rxq->id, rx_received, rx_received);
  2485. }
  2486. /* Cleanup Rx queue */
  2487. static void mvpp2_rxq_deinit(struct mvpp2_port *port,
  2488. struct mvpp2_rx_queue *rxq)
  2489. {
  2490. mvpp2_rxq_drop_pkts(port, rxq);
  2491. rxq->descs = NULL;
  2492. rxq->last_desc = 0;
  2493. rxq->next_desc_to_proc = 0;
  2494. rxq->descs_phys = 0;
  2495. /* Clear Rx descriptors queue starting address and size;
  2496. * free descriptor number
  2497. */
  2498. mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0);
  2499. mvpp2_write(port->priv, MVPP2_RXQ_NUM_REG, rxq->id);
  2500. mvpp2_write(port->priv, MVPP2_RXQ_DESC_ADDR_REG, 0);
  2501. mvpp2_write(port->priv, MVPP2_RXQ_DESC_SIZE_REG, 0);
  2502. }
  2503. /* Create and initialize a Tx queue */
  2504. static int mvpp2_txq_init(struct mvpp2_port *port,
  2505. struct mvpp2_tx_queue *txq)
  2506. {
  2507. u32 val;
  2508. int cpu, desc, desc_per_txq, tx_port_num;
  2509. struct mvpp2_txq_pcpu *txq_pcpu;
  2510. txq->size = port->tx_ring_size;
  2511. /* Allocate memory for Tx descriptors */
  2512. txq->descs = buffer_loc.tx_descs;
  2513. txq->descs_phys = (dma_addr_t)buffer_loc.tx_descs;
  2514. if (!txq->descs)
  2515. return -ENOMEM;
  2516. /* Make sure descriptor address is cache line size aligned */
  2517. BUG_ON(txq->descs !=
  2518. PTR_ALIGN(txq->descs, MVPP2_CPU_D_CACHE_LINE_SIZE));
  2519. txq->last_desc = txq->size - 1;
  2520. /* Set Tx descriptors queue starting address - indirect access */
  2521. mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
  2522. mvpp2_write(port->priv, MVPP2_TXQ_DESC_ADDR_REG, txq->descs_phys);
  2523. mvpp2_write(port->priv, MVPP2_TXQ_DESC_SIZE_REG, txq->size &
  2524. MVPP2_TXQ_DESC_SIZE_MASK);
  2525. mvpp2_write(port->priv, MVPP2_TXQ_INDEX_REG, 0);
  2526. mvpp2_write(port->priv, MVPP2_TXQ_RSVD_CLR_REG,
  2527. txq->id << MVPP2_TXQ_RSVD_CLR_OFFSET);
  2528. val = mvpp2_read(port->priv, MVPP2_TXQ_PENDING_REG);
  2529. val &= ~MVPP2_TXQ_PENDING_MASK;
  2530. mvpp2_write(port->priv, MVPP2_TXQ_PENDING_REG, val);
  2531. /* Calculate base address in prefetch buffer. We reserve 16 descriptors
  2532. * for each existing TXQ.
  2533. * TCONTS for PON port must be continuous from 0 to MVPP2_MAX_TCONT
  2534. * GBE ports assumed to be continious from 0 to MVPP2_MAX_PORTS
  2535. */
  2536. desc_per_txq = 16;
  2537. desc = (port->id * MVPP2_MAX_TXQ * desc_per_txq) +
  2538. (txq->log_id * desc_per_txq);
  2539. mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG,
  2540. MVPP2_PREF_BUF_PTR(desc) | MVPP2_PREF_BUF_SIZE_16 |
  2541. MVPP2_PREF_BUF_THRESH(desc_per_txq/2));
  2542. /* WRR / EJP configuration - indirect access */
  2543. tx_port_num = mvpp2_egress_port(port);
  2544. mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
  2545. val = mvpp2_read(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id));
  2546. val &= ~MVPP2_TXQ_REFILL_PERIOD_ALL_MASK;
  2547. val |= MVPP2_TXQ_REFILL_PERIOD_MASK(1);
  2548. val |= MVPP2_TXQ_REFILL_TOKENS_ALL_MASK;
  2549. mvpp2_write(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id), val);
  2550. val = MVPP2_TXQ_TOKEN_SIZE_MAX;
  2551. mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq->log_id),
  2552. val);
  2553. for_each_present_cpu(cpu) {
  2554. txq_pcpu = per_cpu_ptr(txq->pcpu, cpu);
  2555. txq_pcpu->size = txq->size;
  2556. }
  2557. return 0;
  2558. }
  2559. /* Free allocated TXQ resources */
  2560. static void mvpp2_txq_deinit(struct mvpp2_port *port,
  2561. struct mvpp2_tx_queue *txq)
  2562. {
  2563. txq->descs = NULL;
  2564. txq->last_desc = 0;
  2565. txq->next_desc_to_proc = 0;
  2566. txq->descs_phys = 0;
  2567. /* Set minimum bandwidth for disabled TXQs */
  2568. mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(txq->id), 0);
  2569. /* Set Tx descriptors queue starting address and size */
  2570. mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
  2571. mvpp2_write(port->priv, MVPP2_TXQ_DESC_ADDR_REG, 0);
  2572. mvpp2_write(port->priv, MVPP2_TXQ_DESC_SIZE_REG, 0);
  2573. }
  2574. /* Cleanup Tx ports */
  2575. static void mvpp2_txq_clean(struct mvpp2_port *port, struct mvpp2_tx_queue *txq)
  2576. {
  2577. struct mvpp2_txq_pcpu *txq_pcpu;
  2578. int delay, pending, cpu;
  2579. u32 val;
  2580. mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
  2581. val = mvpp2_read(port->priv, MVPP2_TXQ_PREF_BUF_REG);
  2582. val |= MVPP2_TXQ_DRAIN_EN_MASK;
  2583. mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG, val);
  2584. /* The napi queue has been stopped so wait for all packets
  2585. * to be transmitted.
  2586. */
  2587. delay = 0;
  2588. do {
  2589. if (delay >= MVPP2_TX_PENDING_TIMEOUT_MSEC) {
  2590. netdev_warn(port->dev,
  2591. "port %d: cleaning queue %d timed out\n",
  2592. port->id, txq->log_id);
  2593. break;
  2594. }
  2595. mdelay(1);
  2596. delay++;
  2597. pending = mvpp2_txq_pend_desc_num_get(port, txq);
  2598. } while (pending);
  2599. val &= ~MVPP2_TXQ_DRAIN_EN_MASK;
  2600. mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG, val);
  2601. for_each_present_cpu(cpu) {
  2602. txq_pcpu = per_cpu_ptr(txq->pcpu, cpu);
  2603. /* Release all packets */
  2604. mvpp2_txq_bufs_free(port, txq, txq_pcpu, txq_pcpu->count);
  2605. /* Reset queue */
  2606. txq_pcpu->count = 0;
  2607. txq_pcpu->txq_put_index = 0;
  2608. txq_pcpu->txq_get_index = 0;
  2609. }
  2610. }
  2611. /* Cleanup all Tx queues */
  2612. static void mvpp2_cleanup_txqs(struct mvpp2_port *port)
  2613. {
  2614. struct mvpp2_tx_queue *txq;
  2615. int queue;
  2616. u32 val;
  2617. val = mvpp2_read(port->priv, MVPP2_TX_PORT_FLUSH_REG);
  2618. /* Reset Tx ports and delete Tx queues */
  2619. val |= MVPP2_TX_PORT_FLUSH_MASK(port->id);
  2620. mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val);
  2621. for (queue = 0; queue < txq_number; queue++) {
  2622. txq = port->txqs[queue];
  2623. mvpp2_txq_clean(port, txq);
  2624. mvpp2_txq_deinit(port, txq);
  2625. }
  2626. mvpp2_txq_sent_counter_clear(port);
  2627. val &= ~MVPP2_TX_PORT_FLUSH_MASK(port->id);
  2628. mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val);
  2629. }
  2630. /* Cleanup all Rx queues */
  2631. static void mvpp2_cleanup_rxqs(struct mvpp2_port *port)
  2632. {
  2633. int queue;
  2634. for (queue = 0; queue < rxq_number; queue++)
  2635. mvpp2_rxq_deinit(port, port->rxqs[queue]);
  2636. }
  2637. /* Init all Rx queues for port */
  2638. static int mvpp2_setup_rxqs(struct mvpp2_port *port)
  2639. {
  2640. int queue, err;
  2641. for (queue = 0; queue < rxq_number; queue++) {
  2642. err = mvpp2_rxq_init(port, port->rxqs[queue]);
  2643. if (err)
  2644. goto err_cleanup;
  2645. }
  2646. return 0;
  2647. err_cleanup:
  2648. mvpp2_cleanup_rxqs(port);
  2649. return err;
  2650. }
  2651. /* Init all tx queues for port */
  2652. static int mvpp2_setup_txqs(struct mvpp2_port *port)
  2653. {
  2654. struct mvpp2_tx_queue *txq;
  2655. int queue, err;
  2656. for (queue = 0; queue < txq_number; queue++) {
  2657. txq = port->txqs[queue];
  2658. err = mvpp2_txq_init(port, txq);
  2659. if (err)
  2660. goto err_cleanup;
  2661. }
  2662. mvpp2_txq_sent_counter_clear(port);
  2663. return 0;
  2664. err_cleanup:
  2665. mvpp2_cleanup_txqs(port);
  2666. return err;
  2667. }
  2668. /* Adjust link */
  2669. static void mvpp2_link_event(struct mvpp2_port *port)
  2670. {
  2671. struct phy_device *phydev = port->phy_dev;
  2672. int status_change = 0;
  2673. u32 val;
  2674. if (phydev->link) {
  2675. if ((port->speed != phydev->speed) ||
  2676. (port->duplex != phydev->duplex)) {
  2677. u32 val;
  2678. val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
  2679. val &= ~(MVPP2_GMAC_CONFIG_MII_SPEED |
  2680. MVPP2_GMAC_CONFIG_GMII_SPEED |
  2681. MVPP2_GMAC_CONFIG_FULL_DUPLEX |
  2682. MVPP2_GMAC_AN_SPEED_EN |
  2683. MVPP2_GMAC_AN_DUPLEX_EN);
  2684. if (phydev->duplex)
  2685. val |= MVPP2_GMAC_CONFIG_FULL_DUPLEX;
  2686. if (phydev->speed == SPEED_1000)
  2687. val |= MVPP2_GMAC_CONFIG_GMII_SPEED;
  2688. else if (phydev->speed == SPEED_100)
  2689. val |= MVPP2_GMAC_CONFIG_MII_SPEED;
  2690. writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
  2691. port->duplex = phydev->duplex;
  2692. port->speed = phydev->speed;
  2693. }
  2694. }
  2695. if (phydev->link != port->link) {
  2696. if (!phydev->link) {
  2697. port->duplex = -1;
  2698. port->speed = 0;
  2699. }
  2700. port->link = phydev->link;
  2701. status_change = 1;
  2702. }
  2703. if (status_change) {
  2704. if (phydev->link) {
  2705. val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
  2706. val |= (MVPP2_GMAC_FORCE_LINK_PASS |
  2707. MVPP2_GMAC_FORCE_LINK_DOWN);
  2708. writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
  2709. mvpp2_egress_enable(port);
  2710. mvpp2_ingress_enable(port);
  2711. } else {
  2712. mvpp2_ingress_disable(port);
  2713. mvpp2_egress_disable(port);
  2714. }
  2715. }
  2716. }
  2717. /* Main RX/TX processing routines */
  2718. /* Display more error info */
  2719. static void mvpp2_rx_error(struct mvpp2_port *port,
  2720. struct mvpp2_rx_desc *rx_desc)
  2721. {
  2722. u32 status = rx_desc->status;
  2723. switch (status & MVPP2_RXD_ERR_CODE_MASK) {
  2724. case MVPP2_RXD_ERR_CRC:
  2725. netdev_err(port->dev, "bad rx status %08x (crc error), size=%d\n",
  2726. status, rx_desc->data_size);
  2727. break;
  2728. case MVPP2_RXD_ERR_OVERRUN:
  2729. netdev_err(port->dev, "bad rx status %08x (overrun error), size=%d\n",
  2730. status, rx_desc->data_size);
  2731. break;
  2732. case MVPP2_RXD_ERR_RESOURCE:
  2733. netdev_err(port->dev, "bad rx status %08x (resource error), size=%d\n",
  2734. status, rx_desc->data_size);
  2735. break;
  2736. }
  2737. }
  2738. /* Reuse skb if possible, or allocate a new skb and add it to BM pool */
  2739. static int mvpp2_rx_refill(struct mvpp2_port *port,
  2740. struct mvpp2_bm_pool *bm_pool,
  2741. u32 bm, u32 phys_addr)
  2742. {
  2743. mvpp2_pool_refill(port, bm, phys_addr, phys_addr);
  2744. return 0;
  2745. }
  2746. /* Set hw internals when starting port */
  2747. static void mvpp2_start_dev(struct mvpp2_port *port)
  2748. {
  2749. mvpp2_gmac_max_rx_size_set(port);
  2750. mvpp2_txp_max_tx_size_set(port);
  2751. mvpp2_port_enable(port);
  2752. }
  2753. /* Set hw internals when stopping port */
  2754. static void mvpp2_stop_dev(struct mvpp2_port *port)
  2755. {
  2756. /* Stop new packets from arriving to RXQs */
  2757. mvpp2_ingress_disable(port);
  2758. mvpp2_egress_disable(port);
  2759. mvpp2_port_disable(port);
  2760. }
  2761. static int mvpp2_phy_connect(struct udevice *dev, struct mvpp2_port *port)
  2762. {
  2763. struct phy_device *phy_dev;
  2764. if (!port->init || port->link == 0) {
  2765. phy_dev = phy_connect(port->priv->bus, port->phyaddr, dev,
  2766. port->phy_interface);
  2767. port->phy_dev = phy_dev;
  2768. if (!phy_dev) {
  2769. netdev_err(port->dev, "cannot connect to phy\n");
  2770. return -ENODEV;
  2771. }
  2772. phy_dev->supported &= PHY_GBIT_FEATURES;
  2773. phy_dev->advertising = phy_dev->supported;
  2774. port->phy_dev = phy_dev;
  2775. port->link = 0;
  2776. port->duplex = 0;
  2777. port->speed = 0;
  2778. phy_config(phy_dev);
  2779. phy_startup(phy_dev);
  2780. if (!phy_dev->link) {
  2781. printf("%s: No link\n", phy_dev->dev->name);
  2782. return -1;
  2783. }
  2784. port->init = 1;
  2785. } else {
  2786. mvpp2_egress_enable(port);
  2787. mvpp2_ingress_enable(port);
  2788. }
  2789. return 0;
  2790. }
  2791. static int mvpp2_open(struct udevice *dev, struct mvpp2_port *port)
  2792. {
  2793. unsigned char mac_bcast[ETH_ALEN] = {
  2794. 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
  2795. int err;
  2796. err = mvpp2_prs_mac_da_accept(port->priv, port->id, mac_bcast, true);
  2797. if (err) {
  2798. netdev_err(dev, "mvpp2_prs_mac_da_accept BC failed\n");
  2799. return err;
  2800. }
  2801. err = mvpp2_prs_mac_da_accept(port->priv, port->id,
  2802. port->dev_addr, true);
  2803. if (err) {
  2804. netdev_err(dev, "mvpp2_prs_mac_da_accept MC failed\n");
  2805. return err;
  2806. }
  2807. err = mvpp2_prs_def_flow(port);
  2808. if (err) {
  2809. netdev_err(dev, "mvpp2_prs_def_flow failed\n");
  2810. return err;
  2811. }
  2812. /* Allocate the Rx/Tx queues */
  2813. err = mvpp2_setup_rxqs(port);
  2814. if (err) {
  2815. netdev_err(port->dev, "cannot allocate Rx queues\n");
  2816. return err;
  2817. }
  2818. err = mvpp2_setup_txqs(port);
  2819. if (err) {
  2820. netdev_err(port->dev, "cannot allocate Tx queues\n");
  2821. return err;
  2822. }
  2823. err = mvpp2_phy_connect(dev, port);
  2824. if (err < 0)
  2825. return err;
  2826. mvpp2_link_event(port);
  2827. mvpp2_start_dev(port);
  2828. return 0;
  2829. }
  2830. /* No Device ops here in U-Boot */
  2831. /* Driver initialization */
  2832. static void mvpp2_port_power_up(struct mvpp2_port *port)
  2833. {
  2834. mvpp2_port_mii_set(port);
  2835. mvpp2_port_periodic_xon_disable(port);
  2836. mvpp2_port_fc_adv_enable(port);
  2837. mvpp2_port_reset(port);
  2838. }
  2839. /* Initialize port HW */
  2840. static int mvpp2_port_init(struct udevice *dev, struct mvpp2_port *port)
  2841. {
  2842. struct mvpp2 *priv = port->priv;
  2843. struct mvpp2_txq_pcpu *txq_pcpu;
  2844. int queue, cpu, err;
  2845. if (port->first_rxq + rxq_number > MVPP2_RXQ_TOTAL_NUM)
  2846. return -EINVAL;
  2847. /* Disable port */
  2848. mvpp2_egress_disable(port);
  2849. mvpp2_port_disable(port);
  2850. port->txqs = devm_kcalloc(dev, txq_number, sizeof(*port->txqs),
  2851. GFP_KERNEL);
  2852. if (!port->txqs)
  2853. return -ENOMEM;
  2854. /* Associate physical Tx queues to this port and initialize.
  2855. * The mapping is predefined.
  2856. */
  2857. for (queue = 0; queue < txq_number; queue++) {
  2858. int queue_phy_id = mvpp2_txq_phys(port->id, queue);
  2859. struct mvpp2_tx_queue *txq;
  2860. txq = devm_kzalloc(dev, sizeof(*txq), GFP_KERNEL);
  2861. if (!txq)
  2862. return -ENOMEM;
  2863. txq->pcpu = devm_kzalloc(dev, sizeof(struct mvpp2_txq_pcpu),
  2864. GFP_KERNEL);
  2865. if (!txq->pcpu)
  2866. return -ENOMEM;
  2867. txq->id = queue_phy_id;
  2868. txq->log_id = queue;
  2869. txq->done_pkts_coal = MVPP2_TXDONE_COAL_PKTS_THRESH;
  2870. for_each_present_cpu(cpu) {
  2871. txq_pcpu = per_cpu_ptr(txq->pcpu, cpu);
  2872. txq_pcpu->cpu = cpu;
  2873. }
  2874. port->txqs[queue] = txq;
  2875. }
  2876. port->rxqs = devm_kcalloc(dev, rxq_number, sizeof(*port->rxqs),
  2877. GFP_KERNEL);
  2878. if (!port->rxqs)
  2879. return -ENOMEM;
  2880. /* Allocate and initialize Rx queue for this port */
  2881. for (queue = 0; queue < rxq_number; queue++) {
  2882. struct mvpp2_rx_queue *rxq;
  2883. /* Map physical Rx queue to port's logical Rx queue */
  2884. rxq = devm_kzalloc(dev, sizeof(*rxq), GFP_KERNEL);
  2885. if (!rxq)
  2886. return -ENOMEM;
  2887. /* Map this Rx queue to a physical queue */
  2888. rxq->id = port->first_rxq + queue;
  2889. rxq->port = port->id;
  2890. rxq->logic_rxq = queue;
  2891. port->rxqs[queue] = rxq;
  2892. }
  2893. /* Configure Rx queue group interrupt for this port */
  2894. mvpp2_write(priv, MVPP2_ISR_RXQ_GROUP_REG(port->id), CONFIG_MV_ETH_RXQ);
  2895. /* Create Rx descriptor rings */
  2896. for (queue = 0; queue < rxq_number; queue++) {
  2897. struct mvpp2_rx_queue *rxq = port->rxqs[queue];
  2898. rxq->size = port->rx_ring_size;
  2899. rxq->pkts_coal = MVPP2_RX_COAL_PKTS;
  2900. rxq->time_coal = MVPP2_RX_COAL_USEC;
  2901. }
  2902. mvpp2_ingress_disable(port);
  2903. /* Port default configuration */
  2904. mvpp2_defaults_set(port);
  2905. /* Port's classifier configuration */
  2906. mvpp2_cls_oversize_rxq_set(port);
  2907. mvpp2_cls_port_config(port);
  2908. /* Provide an initial Rx packet size */
  2909. port->pkt_size = MVPP2_RX_PKT_SIZE(PKTSIZE_ALIGN);
  2910. /* Initialize pools for swf */
  2911. err = mvpp2_swf_bm_pool_init(port);
  2912. if (err)
  2913. return err;
  2914. return 0;
  2915. }
  2916. /* Ports initialization */
  2917. static int mvpp2_port_probe(struct udevice *dev,
  2918. struct mvpp2_port *port,
  2919. int port_node,
  2920. struct mvpp2 *priv,
  2921. int *next_first_rxq)
  2922. {
  2923. int phy_node;
  2924. u32 id;
  2925. u32 phyaddr;
  2926. const char *phy_mode_str;
  2927. int phy_mode = -1;
  2928. int priv_common_regs_num = 2;
  2929. int err;
  2930. phy_node = fdtdec_lookup_phandle(gd->fdt_blob, port_node, "phy");
  2931. if (phy_node < 0) {
  2932. dev_err(&pdev->dev, "missing phy\n");
  2933. return -ENODEV;
  2934. }
  2935. phy_mode_str = fdt_getprop(gd->fdt_blob, port_node, "phy-mode", NULL);
  2936. if (phy_mode_str)
  2937. phy_mode = phy_get_interface_by_name(phy_mode_str);
  2938. if (phy_mode == -1) {
  2939. dev_err(&pdev->dev, "incorrect phy mode\n");
  2940. return -EINVAL;
  2941. }
  2942. id = fdtdec_get_int(gd->fdt_blob, port_node, "port-id", -1);
  2943. if (id == -1) {
  2944. dev_err(&pdev->dev, "missing port-id value\n");
  2945. return -EINVAL;
  2946. }
  2947. phyaddr = fdtdec_get_int(gd->fdt_blob, phy_node, "reg", 0);
  2948. port->priv = priv;
  2949. port->id = id;
  2950. port->first_rxq = *next_first_rxq;
  2951. port->phy_node = phy_node;
  2952. port->phy_interface = phy_mode;
  2953. port->phyaddr = phyaddr;
  2954. port->base = (void __iomem *)dev_get_addr_index(dev->parent,
  2955. priv_common_regs_num
  2956. + id);
  2957. if (IS_ERR(port->base))
  2958. return PTR_ERR(port->base);
  2959. port->tx_ring_size = MVPP2_MAX_TXD;
  2960. port->rx_ring_size = MVPP2_MAX_RXD;
  2961. err = mvpp2_port_init(dev, port);
  2962. if (err < 0) {
  2963. dev_err(&pdev->dev, "failed to init port %d\n", id);
  2964. return err;
  2965. }
  2966. mvpp2_port_power_up(port);
  2967. /* Increment the first Rx queue number to be used by the next port */
  2968. *next_first_rxq += CONFIG_MV_ETH_RXQ;
  2969. priv->port_list[id] = port;
  2970. return 0;
  2971. }
  2972. /* Initialize decoding windows */
  2973. static void mvpp2_conf_mbus_windows(const struct mbus_dram_target_info *dram,
  2974. struct mvpp2 *priv)
  2975. {
  2976. u32 win_enable;
  2977. int i;
  2978. for (i = 0; i < 6; i++) {
  2979. mvpp2_write(priv, MVPP2_WIN_BASE(i), 0);
  2980. mvpp2_write(priv, MVPP2_WIN_SIZE(i), 0);
  2981. if (i < 4)
  2982. mvpp2_write(priv, MVPP2_WIN_REMAP(i), 0);
  2983. }
  2984. win_enable = 0;
  2985. for (i = 0; i < dram->num_cs; i++) {
  2986. const struct mbus_dram_window *cs = dram->cs + i;
  2987. mvpp2_write(priv, MVPP2_WIN_BASE(i),
  2988. (cs->base & 0xffff0000) | (cs->mbus_attr << 8) |
  2989. dram->mbus_dram_target_id);
  2990. mvpp2_write(priv, MVPP2_WIN_SIZE(i),
  2991. (cs->size - 1) & 0xffff0000);
  2992. win_enable |= (1 << i);
  2993. }
  2994. mvpp2_write(priv, MVPP2_BASE_ADDR_ENABLE, win_enable);
  2995. }
  2996. /* Initialize Rx FIFO's */
  2997. static void mvpp2_rx_fifo_init(struct mvpp2 *priv)
  2998. {
  2999. int port;
  3000. for (port = 0; port < MVPP2_MAX_PORTS; port++) {
  3001. mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port),
  3002. MVPP2_RX_FIFO_PORT_DATA_SIZE);
  3003. mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
  3004. MVPP2_RX_FIFO_PORT_ATTR_SIZE);
  3005. }
  3006. mvpp2_write(priv, MVPP2_RX_MIN_PKT_SIZE_REG,
  3007. MVPP2_RX_FIFO_PORT_MIN_PKT);
  3008. mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1);
  3009. }
  3010. /* Initialize network controller common part HW */
  3011. static int mvpp2_init(struct udevice *dev, struct mvpp2 *priv)
  3012. {
  3013. const struct mbus_dram_target_info *dram_target_info;
  3014. int err, i;
  3015. u32 val;
  3016. /* Checks for hardware constraints (U-Boot uses only one rxq) */
  3017. if ((rxq_number > MVPP2_MAX_RXQ) || (txq_number > MVPP2_MAX_TXQ)) {
  3018. dev_err(&pdev->dev, "invalid queue size parameter\n");
  3019. return -EINVAL;
  3020. }
  3021. /* MBUS windows configuration */
  3022. dram_target_info = mvebu_mbus_dram_info();
  3023. if (dram_target_info)
  3024. mvpp2_conf_mbus_windows(dram_target_info, priv);
  3025. /* Disable HW PHY polling */
  3026. val = readl(priv->lms_base + MVPP2_PHY_AN_CFG0_REG);
  3027. val |= MVPP2_PHY_AN_STOP_SMI0_MASK;
  3028. writel(val, priv->lms_base + MVPP2_PHY_AN_CFG0_REG);
  3029. /* Allocate and initialize aggregated TXQs */
  3030. priv->aggr_txqs = devm_kcalloc(dev, num_present_cpus(),
  3031. sizeof(struct mvpp2_tx_queue),
  3032. GFP_KERNEL);
  3033. if (!priv->aggr_txqs)
  3034. return -ENOMEM;
  3035. for_each_present_cpu(i) {
  3036. priv->aggr_txqs[i].id = i;
  3037. priv->aggr_txqs[i].size = MVPP2_AGGR_TXQ_SIZE;
  3038. err = mvpp2_aggr_txq_init(dev, &priv->aggr_txqs[i],
  3039. MVPP2_AGGR_TXQ_SIZE, i, priv);
  3040. if (err < 0)
  3041. return err;
  3042. }
  3043. /* Rx Fifo Init */
  3044. mvpp2_rx_fifo_init(priv);
  3045. /* Reset Rx queue group interrupt configuration */
  3046. for (i = 0; i < MVPP2_MAX_PORTS; i++)
  3047. mvpp2_write(priv, MVPP2_ISR_RXQ_GROUP_REG(i),
  3048. CONFIG_MV_ETH_RXQ);
  3049. writel(MVPP2_EXT_GLOBAL_CTRL_DEFAULT,
  3050. priv->lms_base + MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG);
  3051. /* Allow cache snoop when transmiting packets */
  3052. mvpp2_write(priv, MVPP2_TX_SNOOP_REG, 0x1);
  3053. /* Buffer Manager initialization */
  3054. err = mvpp2_bm_init(dev, priv);
  3055. if (err < 0)
  3056. return err;
  3057. /* Parser default initialization */
  3058. err = mvpp2_prs_default_init(dev, priv);
  3059. if (err < 0)
  3060. return err;
  3061. /* Classifier default initialization */
  3062. mvpp2_cls_init(priv);
  3063. return 0;
  3064. }
  3065. /* SMI / MDIO functions */
  3066. static int smi_wait_ready(struct mvpp2 *priv)
  3067. {
  3068. u32 timeout = MVPP2_SMI_TIMEOUT;
  3069. u32 smi_reg;
  3070. /* wait till the SMI is not busy */
  3071. do {
  3072. /* read smi register */
  3073. smi_reg = readl(priv->lms_base + MVPP2_SMI);
  3074. if (timeout-- == 0) {
  3075. printf("Error: SMI busy timeout\n");
  3076. return -EFAULT;
  3077. }
  3078. } while (smi_reg & MVPP2_SMI_BUSY);
  3079. return 0;
  3080. }
  3081. /*
  3082. * mpp2_mdio_read - miiphy_read callback function.
  3083. *
  3084. * Returns 16bit phy register value, or 0xffff on error
  3085. */
  3086. static int mpp2_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
  3087. {
  3088. struct mvpp2 *priv = bus->priv;
  3089. u32 smi_reg;
  3090. u32 timeout;
  3091. /* check parameters */
  3092. if (addr > MVPP2_PHY_ADDR_MASK) {
  3093. printf("Error: Invalid PHY address %d\n", addr);
  3094. return -EFAULT;
  3095. }
  3096. if (reg > MVPP2_PHY_REG_MASK) {
  3097. printf("Err: Invalid register offset %d\n", reg);
  3098. return -EFAULT;
  3099. }
  3100. /* wait till the SMI is not busy */
  3101. if (smi_wait_ready(priv) < 0)
  3102. return -EFAULT;
  3103. /* fill the phy address and regiser offset and read opcode */
  3104. smi_reg = (addr << MVPP2_SMI_DEV_ADDR_OFFS)
  3105. | (reg << MVPP2_SMI_REG_ADDR_OFFS)
  3106. | MVPP2_SMI_OPCODE_READ;
  3107. /* write the smi register */
  3108. writel(smi_reg, priv->lms_base + MVPP2_SMI);
  3109. /* wait till read value is ready */
  3110. timeout = MVPP2_SMI_TIMEOUT;
  3111. do {
  3112. /* read smi register */
  3113. smi_reg = readl(priv->lms_base + MVPP2_SMI);
  3114. if (timeout-- == 0) {
  3115. printf("Err: SMI read ready timeout\n");
  3116. return -EFAULT;
  3117. }
  3118. } while (!(smi_reg & MVPP2_SMI_READ_VALID));
  3119. /* Wait for the data to update in the SMI register */
  3120. for (timeout = 0; timeout < MVPP2_SMI_TIMEOUT; timeout++)
  3121. ;
  3122. return readl(priv->lms_base + MVPP2_SMI) & MVPP2_SMI_DATA_MASK;
  3123. }
  3124. /*
  3125. * mpp2_mdio_write - miiphy_write callback function.
  3126. *
  3127. * Returns 0 if write succeed, -EINVAL on bad parameters
  3128. * -ETIME on timeout
  3129. */
  3130. static int mpp2_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
  3131. u16 value)
  3132. {
  3133. struct mvpp2 *priv = bus->priv;
  3134. u32 smi_reg;
  3135. /* check parameters */
  3136. if (addr > MVPP2_PHY_ADDR_MASK) {
  3137. printf("Error: Invalid PHY address %d\n", addr);
  3138. return -EFAULT;
  3139. }
  3140. if (reg > MVPP2_PHY_REG_MASK) {
  3141. printf("Err: Invalid register offset %d\n", reg);
  3142. return -EFAULT;
  3143. }
  3144. /* wait till the SMI is not busy */
  3145. if (smi_wait_ready(priv) < 0)
  3146. return -EFAULT;
  3147. /* fill the phy addr and reg offset and write opcode and data */
  3148. smi_reg = value << MVPP2_SMI_DATA_OFFS;
  3149. smi_reg |= (addr << MVPP2_SMI_DEV_ADDR_OFFS)
  3150. | (reg << MVPP2_SMI_REG_ADDR_OFFS);
  3151. smi_reg &= ~MVPP2_SMI_OPCODE_READ;
  3152. /* write the smi register */
  3153. writel(smi_reg, priv->lms_base + MVPP2_SMI);
  3154. return 0;
  3155. }
  3156. static int mvpp2_recv(struct udevice *dev, int flags, uchar **packetp)
  3157. {
  3158. struct mvpp2_port *port = dev_get_priv(dev);
  3159. struct mvpp2_rx_desc *rx_desc;
  3160. struct mvpp2_bm_pool *bm_pool;
  3161. dma_addr_t phys_addr;
  3162. u32 bm, rx_status;
  3163. int pool, rx_bytes, err;
  3164. int rx_received;
  3165. struct mvpp2_rx_queue *rxq;
  3166. u32 cause_rx_tx, cause_rx, cause_misc;
  3167. u8 *data;
  3168. cause_rx_tx = mvpp2_read(port->priv,
  3169. MVPP2_ISR_RX_TX_CAUSE_REG(port->id));
  3170. cause_rx_tx &= ~MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK;
  3171. cause_misc = cause_rx_tx & MVPP2_CAUSE_MISC_SUM_MASK;
  3172. if (!cause_rx_tx && !cause_misc)
  3173. return 0;
  3174. cause_rx = cause_rx_tx & MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK;
  3175. /* Process RX packets */
  3176. cause_rx |= port->pending_cause_rx;
  3177. rxq = mvpp2_get_rx_queue(port, cause_rx);
  3178. /* Get number of received packets and clamp the to-do */
  3179. rx_received = mvpp2_rxq_received(port, rxq->id);
  3180. /* Return if no packets are received */
  3181. if (!rx_received)
  3182. return 0;
  3183. rx_desc = mvpp2_rxq_next_desc_get(rxq);
  3184. rx_status = rx_desc->status;
  3185. rx_bytes = rx_desc->data_size - MVPP2_MH_SIZE;
  3186. phys_addr = rx_desc->buf_phys_addr;
  3187. bm = mvpp2_bm_cookie_build(rx_desc);
  3188. pool = mvpp2_bm_cookie_pool_get(bm);
  3189. bm_pool = &port->priv->bm_pools[pool];
  3190. /* Check if buffer header is used */
  3191. if (rx_status & MVPP2_RXD_BUF_HDR)
  3192. return 0;
  3193. /* In case of an error, release the requested buffer pointer
  3194. * to the Buffer Manager. This request process is controlled
  3195. * by the hardware, and the information about the buffer is
  3196. * comprised by the RX descriptor.
  3197. */
  3198. if (rx_status & MVPP2_RXD_ERR_SUMMARY) {
  3199. mvpp2_rx_error(port, rx_desc);
  3200. /* Return the buffer to the pool */
  3201. mvpp2_pool_refill(port, bm, rx_desc->buf_phys_addr,
  3202. rx_desc->buf_cookie);
  3203. return 0;
  3204. }
  3205. err = mvpp2_rx_refill(port, bm_pool, bm, phys_addr);
  3206. if (err) {
  3207. netdev_err(port->dev, "failed to refill BM pools\n");
  3208. return 0;
  3209. }
  3210. /* Update Rx queue management counters */
  3211. mb();
  3212. mvpp2_rxq_status_update(port, rxq->id, 1, 1);
  3213. /* give packet to stack - skip on first n bytes */
  3214. data = (u8 *)phys_addr + 2 + 32;
  3215. if (rx_bytes <= 0)
  3216. return 0;
  3217. /*
  3218. * No cache invalidation needed here, since the rx_buffer's are
  3219. * located in a uncached memory region
  3220. */
  3221. *packetp = data;
  3222. return rx_bytes;
  3223. }
  3224. /* Drain Txq */
  3225. static void mvpp2_txq_drain(struct mvpp2_port *port, struct mvpp2_tx_queue *txq,
  3226. int enable)
  3227. {
  3228. u32 val;
  3229. mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
  3230. val = mvpp2_read(port->priv, MVPP2_TXQ_PREF_BUF_REG);
  3231. if (enable)
  3232. val |= MVPP2_TXQ_DRAIN_EN_MASK;
  3233. else
  3234. val &= ~MVPP2_TXQ_DRAIN_EN_MASK;
  3235. mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG, val);
  3236. }
  3237. static int mvpp2_send(struct udevice *dev, void *packet, int length)
  3238. {
  3239. struct mvpp2_port *port = dev_get_priv(dev);
  3240. struct mvpp2_tx_queue *txq, *aggr_txq;
  3241. struct mvpp2_tx_desc *tx_desc;
  3242. int tx_done;
  3243. int timeout;
  3244. txq = port->txqs[0];
  3245. aggr_txq = &port->priv->aggr_txqs[smp_processor_id()];
  3246. /* Get a descriptor for the first part of the packet */
  3247. tx_desc = mvpp2_txq_next_desc_get(aggr_txq);
  3248. tx_desc->phys_txq = txq->id;
  3249. tx_desc->data_size = length;
  3250. tx_desc->packet_offset = (u32)packet & MVPP2_TX_DESC_ALIGN;
  3251. tx_desc->buf_phys_addr = (u32)packet & ~MVPP2_TX_DESC_ALIGN;
  3252. /* First and Last descriptor */
  3253. tx_desc->command = MVPP2_TXD_L4_CSUM_NOT | MVPP2_TXD_IP_CSUM_DISABLE
  3254. | MVPP2_TXD_F_DESC | MVPP2_TXD_L_DESC;
  3255. /* Flush tx data */
  3256. flush_dcache_range((unsigned long)packet,
  3257. (unsigned long)packet + ALIGN(length, PKTALIGN));
  3258. /* Enable transmit */
  3259. mb();
  3260. mvpp2_aggr_txq_pend_desc_add(port, 1);
  3261. mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
  3262. timeout = 0;
  3263. do {
  3264. if (timeout++ > 10000) {
  3265. printf("timeout: packet not sent from aggregated to phys TXQ\n");
  3266. return 0;
  3267. }
  3268. tx_done = mvpp2_txq_pend_desc_num_get(port, txq);
  3269. } while (tx_done);
  3270. /* Enable TXQ drain */
  3271. mvpp2_txq_drain(port, txq, 1);
  3272. timeout = 0;
  3273. do {
  3274. if (timeout++ > 10000) {
  3275. printf("timeout: packet not sent\n");
  3276. return 0;
  3277. }
  3278. tx_done = mvpp2_txq_sent_desc_proc(port, txq);
  3279. } while (!tx_done);
  3280. /* Disable TXQ drain */
  3281. mvpp2_txq_drain(port, txq, 0);
  3282. return 0;
  3283. }
  3284. static int mvpp2_start(struct udevice *dev)
  3285. {
  3286. struct eth_pdata *pdata = dev_get_platdata(dev);
  3287. struct mvpp2_port *port = dev_get_priv(dev);
  3288. /* Load current MAC address */
  3289. memcpy(port->dev_addr, pdata->enetaddr, ETH_ALEN);
  3290. /* Reconfigure parser accept the original MAC address */
  3291. mvpp2_prs_update_mac_da(port, port->dev_addr);
  3292. mvpp2_port_power_up(port);
  3293. mvpp2_open(dev, port);
  3294. return 0;
  3295. }
  3296. static void mvpp2_stop(struct udevice *dev)
  3297. {
  3298. struct mvpp2_port *port = dev_get_priv(dev);
  3299. mvpp2_stop_dev(port);
  3300. mvpp2_cleanup_rxqs(port);
  3301. mvpp2_cleanup_txqs(port);
  3302. }
  3303. static int mvpp2_probe(struct udevice *dev)
  3304. {
  3305. struct mvpp2_port *port = dev_get_priv(dev);
  3306. struct mvpp2 *priv = dev_get_priv(dev->parent);
  3307. int err;
  3308. /* Initialize network controller */
  3309. err = mvpp2_init(dev, priv);
  3310. if (err < 0) {
  3311. dev_err(&pdev->dev, "failed to initialize controller\n");
  3312. return err;
  3313. }
  3314. return mvpp2_port_probe(dev, port, dev_of_offset(dev), priv,
  3315. &buffer_loc.first_rxq);
  3316. }
  3317. static const struct eth_ops mvpp2_ops = {
  3318. .start = mvpp2_start,
  3319. .send = mvpp2_send,
  3320. .recv = mvpp2_recv,
  3321. .stop = mvpp2_stop,
  3322. };
  3323. static struct driver mvpp2_driver = {
  3324. .name = "mvpp2",
  3325. .id = UCLASS_ETH,
  3326. .probe = mvpp2_probe,
  3327. .ops = &mvpp2_ops,
  3328. .priv_auto_alloc_size = sizeof(struct mvpp2_port),
  3329. .platdata_auto_alloc_size = sizeof(struct eth_pdata),
  3330. };
  3331. /*
  3332. * Use a MISC device to bind the n instances (child nodes) of the
  3333. * network base controller in UCLASS_ETH.
  3334. */
  3335. static int mvpp2_base_probe(struct udevice *dev)
  3336. {
  3337. struct mvpp2 *priv = dev_get_priv(dev);
  3338. struct mii_dev *bus;
  3339. void *bd_space;
  3340. u32 size = 0;
  3341. int i;
  3342. /*
  3343. * U-Boot special buffer handling:
  3344. *
  3345. * Allocate buffer area for descs and rx_buffers. This is only
  3346. * done once for all interfaces. As only one interface can
  3347. * be active. Make this area DMA-safe by disabling the D-cache
  3348. */
  3349. /* Align buffer area for descs and rx_buffers to 1MiB */
  3350. bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE);
  3351. mmu_set_region_dcache_behaviour((u32)bd_space, BD_SPACE, DCACHE_OFF);
  3352. buffer_loc.aggr_tx_descs = (struct mvpp2_tx_desc *)bd_space;
  3353. size += MVPP2_AGGR_TXQ_SIZE * MVPP2_DESC_ALIGNED_SIZE;
  3354. buffer_loc.tx_descs = (struct mvpp2_tx_desc *)((u32)bd_space + size);
  3355. size += MVPP2_MAX_TXD * MVPP2_DESC_ALIGNED_SIZE;
  3356. buffer_loc.rx_descs = (struct mvpp2_rx_desc *)((u32)bd_space + size);
  3357. size += MVPP2_MAX_RXD * MVPP2_DESC_ALIGNED_SIZE;
  3358. for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) {
  3359. buffer_loc.bm_pool[i] = (u32 *)((u32)bd_space + size);
  3360. size += MVPP2_BM_POOL_SIZE_MAX * sizeof(u32);
  3361. }
  3362. for (i = 0; i < MVPP2_BM_LONG_BUF_NUM; i++) {
  3363. buffer_loc.rx_buffer[i] = (u32 *)((u32)bd_space + size);
  3364. size += RX_BUFFER_SIZE;
  3365. }
  3366. /* Save base addresses for later use */
  3367. priv->base = (void *)dev_get_addr_index(dev, 0);
  3368. if (IS_ERR(priv->base))
  3369. return PTR_ERR(priv->base);
  3370. priv->lms_base = (void *)dev_get_addr_index(dev, 1);
  3371. if (IS_ERR(priv->lms_base))
  3372. return PTR_ERR(priv->lms_base);
  3373. /* Finally create and register the MDIO bus driver */
  3374. bus = mdio_alloc();
  3375. if (!bus) {
  3376. printf("Failed to allocate MDIO bus\n");
  3377. return -ENOMEM;
  3378. }
  3379. bus->read = mpp2_mdio_read;
  3380. bus->write = mpp2_mdio_write;
  3381. snprintf(bus->name, sizeof(bus->name), dev->name);
  3382. bus->priv = (void *)priv;
  3383. priv->bus = bus;
  3384. return mdio_register(bus);
  3385. }
  3386. static int mvpp2_base_bind(struct udevice *parent)
  3387. {
  3388. const void *blob = gd->fdt_blob;
  3389. int node = dev_of_offset(parent);
  3390. struct uclass_driver *drv;
  3391. struct udevice *dev;
  3392. struct eth_pdata *plat;
  3393. char *name;
  3394. int subnode;
  3395. u32 id;
  3396. /* Lookup eth driver */
  3397. drv = lists_uclass_lookup(UCLASS_ETH);
  3398. if (!drv) {
  3399. puts("Cannot find eth driver\n");
  3400. return -ENOENT;
  3401. }
  3402. fdt_for_each_subnode(subnode, blob, node) {
  3403. /* Skip disabled ports */
  3404. if (!fdtdec_get_is_enabled(blob, subnode))
  3405. continue;
  3406. plat = calloc(1, sizeof(*plat));
  3407. if (!plat)
  3408. return -ENOMEM;
  3409. id = fdtdec_get_int(blob, subnode, "port-id", -1);
  3410. name = calloc(1, 16);
  3411. sprintf(name, "mvpp2-%d", id);
  3412. /* Create child device UCLASS_ETH and bind it */
  3413. device_bind(parent, &mvpp2_driver, name, plat, subnode, &dev);
  3414. dev_set_of_offset(dev, subnode);
  3415. }
  3416. return 0;
  3417. }
  3418. static const struct udevice_id mvpp2_ids[] = {
  3419. { .compatible = "marvell,armada-375-pp2" },
  3420. { }
  3421. };
  3422. U_BOOT_DRIVER(mvpp2_base) = {
  3423. .name = "mvpp2_base",
  3424. .id = UCLASS_MISC,
  3425. .of_match = mvpp2_ids,
  3426. .bind = mvpp2_base_bind,
  3427. .probe = mvpp2_base_probe,
  3428. .priv_auto_alloc_size = sizeof(struct mvpp2),
  3429. };