chromebook_link.dts 9.6 KB

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  1. /dts-v1/;
  2. #include <dt-bindings/gpio/x86-gpio.h>
  3. /include/ "skeleton.dtsi"
  4. /include/ "keyboard.dtsi"
  5. /include/ "serial.dtsi"
  6. /include/ "rtc.dtsi"
  7. /include/ "tsc_timer.dtsi"
  8. / {
  9. model = "Google Link";
  10. compatible = "google,link", "intel,celeron-ivybridge";
  11. aliases {
  12. spi0 = &spi;
  13. usb0 = &usb_0;
  14. usb1 = &usb_1;
  15. };
  16. config {
  17. silent_console = <0>;
  18. };
  19. cpus {
  20. #address-cells = <1>;
  21. #size-cells = <0>;
  22. cpu@0 {
  23. device_type = "cpu";
  24. compatible = "intel,core-gen3";
  25. reg = <0>;
  26. intel,apic-id = <0>;
  27. };
  28. cpu@1 {
  29. device_type = "cpu";
  30. compatible = "intel,core-gen3";
  31. reg = <1>;
  32. intel,apic-id = <1>;
  33. };
  34. cpu@2 {
  35. device_type = "cpu";
  36. compatible = "intel,core-gen3";
  37. reg = <2>;
  38. intel,apic-id = <2>;
  39. };
  40. cpu@3 {
  41. device_type = "cpu";
  42. compatible = "intel,core-gen3";
  43. reg = <3>;
  44. intel,apic-id = <3>;
  45. };
  46. };
  47. chosen {
  48. stdout-path = "/serial";
  49. };
  50. keyboard {
  51. intel,duplicate-por;
  52. };
  53. pch_pinctrl {
  54. compatible = "intel,x86-pinctrl";
  55. u-boot,dm-pre-reloc;
  56. reg = <0 0>;
  57. gpio_a0 {
  58. gpio-offset = <0 0>;
  59. mode-gpio;
  60. direction = <PIN_INPUT>;
  61. };
  62. gpio_a1 {
  63. gpio-offset = <0>;
  64. mode-gpio;
  65. direction = <PIN_OUTPUT>;
  66. output-value = <1>;
  67. };
  68. gpio_a3 {
  69. gpio-offset = <0 3>;
  70. mode-gpio;
  71. direction = <PIN_INPUT>;
  72. };
  73. gpio_a5 {
  74. gpio-offset = <0 5>;
  75. mode-gpio;
  76. direction = <PIN_INPUT>;
  77. };
  78. gpio_a6 {
  79. gpio-offset = <0 6>;
  80. mode-gpio;
  81. direction = <PIN_OUTPUT>;
  82. output-value = <1>;
  83. };
  84. gpio_a7 {
  85. gpio-offset = <0 7>;
  86. mode-gpio;
  87. direction = <PIN_INPUT>;
  88. invert;
  89. };
  90. gpio_a8 {
  91. gpio-offset = <0 8>;
  92. mode-gpio;
  93. direction = <PIN_INPUT>;
  94. invert;
  95. };
  96. gpio_a9 {
  97. gpio-offset = <0 9>;
  98. mode-gpio;
  99. direction = <PIN_INPUT>;
  100. };
  101. gpio_a10 {
  102. u-boot,dm-pre-reloc;
  103. gpio-offset = <0 10>;
  104. mode-gpio;
  105. direction = <PIN_INPUT>;
  106. };
  107. gpio_a11 {
  108. gpio-offset = <0 11>;
  109. mode-gpio;
  110. direction = <PIN_INPUT>;
  111. };
  112. gpio_a12 {
  113. gpio-offset = <0 12>;
  114. mode-gpio;
  115. direction = <PIN_INPUT>;
  116. invert;
  117. };
  118. gpio_a14 {
  119. gpio-offset = <0 14>;
  120. mode-gpio;
  121. direction = <PIN_INPUT>;
  122. invert;
  123. };
  124. gpio_a15 {
  125. gpio-offset = <0 15>;
  126. mode-gpio;
  127. direction = <PIN_INPUT>;
  128. invert;
  129. };
  130. gpio_a21 {
  131. gpio-offset = <0 21>;
  132. mode-gpio;
  133. direction = <PIN_INPUT>;
  134. };
  135. gpio_a24 {
  136. gpio-offset = <0 24>;
  137. mode-gpio;
  138. output-value = <0>;
  139. direction = <PIN_OUTPUT>;
  140. };
  141. gpio_a28 {
  142. gpio-offset = <0 28>;
  143. mode-gpio;
  144. direction = <PIN_INPUT>;
  145. };
  146. gpio_b4 {
  147. gpio-offset = <0x30 4>;
  148. mode-gpio;
  149. direction = <PIN_OUTPUT>;
  150. output-value = <1>;
  151. };
  152. gpio_b9 {
  153. u-boot,dm-pre-reloc;
  154. gpio-offset = <0x30 9>;
  155. mode-gpio;
  156. direction = <PIN_INPUT>;
  157. };
  158. gpio_b10 {
  159. u-boot,dm-pre-reloc;
  160. gpio-offset = <0x30 10>;
  161. mode-gpio;
  162. direction = <PIN_INPUT>;
  163. };
  164. gpio_b11 {
  165. u-boot,dm-pre-reloc;
  166. gpio-offset = <0x30 11>;
  167. mode-gpio;
  168. direction = <PIN_INPUT>;
  169. };
  170. gpio_b25 {
  171. gpio-offset = <0x30 25>;
  172. mode-gpio;
  173. direction = <PIN_INPUT>;
  174. };
  175. gpio_b28 {
  176. gpio-offset = <0x30 28>;
  177. mode-gpio;
  178. direction = <PIN_OUTPUT>;
  179. output-value = <1>;
  180. };
  181. };
  182. pci {
  183. compatible = "pci-x86";
  184. #address-cells = <3>;
  185. #size-cells = <2>;
  186. u-boot,dm-pre-reloc;
  187. ranges = <0x02000000 0x0 0xe0000000 0xe0000000 0 0x10000000
  188. 0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000
  189. 0x01000000 0x0 0x1000 0x1000 0 0xefff>;
  190. northbridge@0,0 {
  191. reg = <0x00000000 0 0 0 0>;
  192. compatible = "intel,bd82x6x-northbridge";
  193. board-id-gpios = <&gpio_b 9 0>, <&gpio_b 10 0>,
  194. <&gpio_b 11 0>, <&gpio_a 10 0>;
  195. u-boot,dm-pre-reloc;
  196. spd {
  197. #address-cells = <1>;
  198. #size-cells = <0>;
  199. elpida_4Gb_1600_x16 {
  200. reg = <0>;
  201. data = [92 10 0b 03 04 19 02 02
  202. 03 52 01 08 0a 00 fe 00
  203. 69 78 69 3c 69 11 18 81
  204. 20 08 3c 3c 01 40 83 81
  205. 00 00 00 00 00 00 00 00
  206. 00 00 00 00 00 00 00 00
  207. 00 00 00 00 00 00 00 00
  208. 00 00 00 00 0f 11 42 00
  209. 00 00 00 00 00 00 00 00
  210. 00 00 00 00 00 00 00 00
  211. 00 00 00 00 00 00 00 00
  212. 00 00 00 00 00 00 00 00
  213. 00 00 00 00 00 00 00 00
  214. 00 00 00 00 00 00 00 00
  215. 00 00 00 00 00 02 fe 00
  216. 11 52 00 00 00 07 7f 37
  217. 45 42 4a 32 30 55 47 36
  218. 45 42 55 30 2d 47 4e 2d
  219. 46 20 30 20 02 fe 00 00
  220. 00 00 00 00 00 00 00 00
  221. 00 00 00 00 00 00 00 00
  222. 00 00 00 00 00 00 00 00
  223. 00 00 00 00 00 00 00 00
  224. 00 00 00 00 00 00 00 00
  225. 00 00 00 00 00 00 00 00
  226. 00 00 00 00 00 00 00 00
  227. 00 00 00 00 00 00 00 00
  228. 00 00 00 00 00 00 00 00
  229. 00 00 00 00 00 00 00 00
  230. 00 00 00 00 00 00 00 00
  231. 00 00 00 00 00 00 00 00
  232. 00 00 00 00 00 00 00 00];
  233. };
  234. samsung_4Gb_1600_1.35v_x16 {
  235. reg = <1>;
  236. data = [92 11 0b 03 04 19 02 02
  237. 03 11 01 08 0a 00 fe 00
  238. 69 78 69 3c 69 11 18 81
  239. f0 0a 3c 3c 01 40 83 01
  240. 00 80 00 00 00 00 00 00
  241. 00 00 00 00 00 00 00 00
  242. 00 00 00 00 00 00 00 00
  243. 00 00 00 00 0f 11 02 00
  244. 00 00 00 00 00 00 00 00
  245. 00 00 00 00 00 00 00 00
  246. 00 00 00 00 00 00 00 00
  247. 00 00 00 00 00 00 00 00
  248. 00 00 00 00 00 00 00 00
  249. 00 00 00 00 00 00 00 00
  250. 00 00 00 00 00 80 ce 01
  251. 00 00 00 00 00 00 6a 04
  252. 4d 34 37 31 42 35 36 37
  253. 34 42 48 30 2d 59 4b 30
  254. 20 20 00 00 80 ce 00 00
  255. 00 00 00 00 00 00 00 00
  256. 00 00 00 00 00 00 00 00
  257. 00 00 00 00 00 00 00 00
  258. 00 00 00 00 00 00 00 00
  259. 00 00 00 00 00 00 00 00
  260. 00 00 00 00 00 00 00 00
  261. 00 00 00 00 00 00 00 00
  262. 00 00 00 00 00 00 00 00
  263. 00 00 00 00 00 00 00 00
  264. 00 00 00 00 00 00 00 00
  265. 00 00 00 00 00 00 00 00
  266. 00 00 00 00 00 00 00 00
  267. 00 00 00 00 00 00 00 00];
  268. };
  269. micron_4Gb_1600_1.35v_x16 {
  270. reg = <2>;
  271. data = [92 11 0b 03 04 19 02 02
  272. 03 11 01 08 0a 00 fe 00
  273. 69 78 69 3c 69 11 18 81
  274. 20 08 3c 3c 01 40 83 05
  275. 00 00 00 00 00 00 00 00
  276. 00 00 00 00 00 00 00 00
  277. 00 00 00 00 00 00 00 00
  278. 00 00 00 00 0f 01 02 00
  279. 00 00 00 00 00 00 00 00
  280. 00 00 00 00 00 00 00 00
  281. 00 00 00 00 00 00 00 00
  282. 00 00 00 00 00 00 00 00
  283. 00 00 00 00 00 00 00 00
  284. 00 00 00 00 00 00 00 00
  285. 00 00 00 00 00 80 2c 00
  286. 00 00 00 00 00 00 ad 75
  287. 34 4b 54 46 32 35 36 36
  288. 34 48 5a 2d 31 47 36 45
  289. 31 20 45 31 80 2c 00 00
  290. 00 00 00 00 00 00 00 00
  291. 00 00 00 00 00 00 00 00
  292. 00 00 00 00 00 00 00 00
  293. ff ff ff ff ff ff ff ff
  294. ff ff ff ff ff ff ff ff
  295. ff ff ff ff ff ff ff ff
  296. ff ff ff ff ff ff ff ff
  297. ff ff ff ff ff ff ff ff
  298. ff ff ff ff ff ff ff ff
  299. ff ff ff ff ff ff ff ff
  300. ff ff ff ff ff ff ff ff
  301. ff ff ff ff ff ff ff ff
  302. ff ff ff ff ff ff ff ff];
  303. };
  304. };
  305. };
  306. gma@2,0 {
  307. reg = <0x00001000 0 0 0 0>;
  308. compatible = "intel,gma";
  309. intel,dp_hotplug = <0 0 0x06>;
  310. intel,panel-port-select = <1>;
  311. intel,panel-power-cycle-delay = <6>;
  312. intel,panel-power-up-delay = <2000>;
  313. intel,panel-power-down-delay = <500>;
  314. intel,panel-power-backlight-on-delay = <2000>;
  315. intel,panel-power-backlight-off-delay = <2000>;
  316. intel,cpu-backlight = <0x00000200>;
  317. intel,pch-backlight = <0x04000000>;
  318. };
  319. me@16,0 {
  320. reg = <0x0000b000 0 0 0 0>;
  321. compatible = "intel,me";
  322. u-boot,dm-pre-reloc;
  323. };
  324. usb_1: usb@1a,0 {
  325. reg = <0x0000d000 0 0 0 0>;
  326. compatible = "ehci-pci";
  327. };
  328. usb_0: usb@1d,0 {
  329. reg = <0x0000e800 0 0 0 0>;
  330. compatible = "ehci-pci";
  331. };
  332. pch@1f,0 {
  333. reg = <0x0000f800 0 0 0 0>;
  334. compatible = "intel,bd82x6x", "intel,pch9";
  335. u-boot,dm-pre-reloc;
  336. #address-cells = <1>;
  337. #size-cells = <1>;
  338. intel,pirq-routing = <0x8b 0x8a 0x8b 0x8b
  339. 0x80 0x80 0x80 0x80>;
  340. intel,gpi-routing = <0 0 0 0 0 0 0 2
  341. 1 0 0 0 0 0 0 0>;
  342. /* Enable EC SMI source */
  343. intel,alt-gp-smi-enable = <0x0100>;
  344. spi: spi {
  345. #address-cells = <1>;
  346. #size-cells = <0>;
  347. compatible = "intel,ich9-spi";
  348. spi-flash@0 {
  349. #size-cells = <1>;
  350. #address-cells = <1>;
  351. reg = <0>;
  352. compatible = "winbond,w25q64",
  353. "spi-flash";
  354. memory-map = <0xff800000 0x00800000>;
  355. rw-mrc-cache {
  356. label = "rw-mrc-cache";
  357. reg = <0x003e0000 0x00010000>;
  358. };
  359. };
  360. };
  361. gpio_a: gpioa {
  362. compatible = "intel,ich6-gpio";
  363. u-boot,dm-pre-reloc;
  364. #gpio-cells = <2>;
  365. gpio-controller;
  366. reg = <0 0x10>;
  367. bank-name = "A";
  368. };
  369. gpio_b: gpiob {
  370. compatible = "intel,ich6-gpio";
  371. u-boot,dm-pre-reloc;
  372. #gpio-cells = <2>;
  373. gpio-controller;
  374. reg = <0x30 0x10>;
  375. bank-name = "B";
  376. };
  377. gpio_c: gpioc {
  378. compatible = "intel,ich6-gpio";
  379. u-boot,dm-pre-reloc;
  380. #gpio-cells = <2>;
  381. gpio-controller;
  382. reg = <0x40 0x10>;
  383. bank-name = "C";
  384. };
  385. lpc {
  386. compatible = "intel,bd82x6x-lpc";
  387. #address-cells = <1>;
  388. #size-cells = <0>;
  389. u-boot,dm-pre-reloc;
  390. intel,gen-dec = <0x800 0xfc 0x900 0xfc>;
  391. cros-ec@200 {
  392. compatible = "google,cros-ec";
  393. reg = <0x204 1 0x200 1 0x880 0x80>;
  394. /*
  395. * Describes the flash memory within
  396. * the EC
  397. */
  398. #address-cells = <1>;
  399. #size-cells = <1>;
  400. flash@8000000 {
  401. reg = <0x08000000 0x20000>;
  402. erase-value = <0xff>;
  403. };
  404. };
  405. };
  406. };
  407. sata@1f,2 {
  408. compatible = "intel,pantherpoint-ahci";
  409. reg = <0x0000fa00 0 0 0 0>;
  410. u-boot,dm-pre-reloc;
  411. intel,sata-mode = "ahci";
  412. intel,sata-port-map = <1>;
  413. intel,sata-port0-gen3-tx = <0x00880a7f>;
  414. };
  415. smbus: smbus@1f,3 {
  416. compatible = "intel,ich-i2c";
  417. reg = <0x0000fb00 0 0 0 0>;
  418. u-boot,dm-pre-reloc;
  419. };
  420. };
  421. tpm {
  422. reg = <0xfed40000 0x5000>;
  423. compatible = "infineon,slb9635lpc";
  424. };
  425. microcode {
  426. update@0 {
  427. #include "microcode/m12306a9_0000001b.dtsi"
  428. };
  429. };
  430. };