i2c-uniphier-f.c 8.6 KB

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  1. /*
  2. * Copyright (C) 2014 Panasonic Corporation
  3. * Copyright (C) 2015 Socionext Inc.
  4. * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  5. *
  6. * SPDX-License-Identifier: GPL-2.0+
  7. */
  8. #include <common.h>
  9. #include <linux/types.h>
  10. #include <asm/io.h>
  11. #include <asm/errno.h>
  12. #include <dm/device.h>
  13. #include <dm/root.h>
  14. #include <i2c.h>
  15. #include <fdtdec.h>
  16. DECLARE_GLOBAL_DATA_PTR;
  17. struct uniphier_fi2c_regs {
  18. u32 cr; /* control register */
  19. #define I2C_CR_MST (1 << 3) /* master mode */
  20. #define I2C_CR_STA (1 << 2) /* start condition */
  21. #define I2C_CR_STO (1 << 1) /* stop condition */
  22. #define I2C_CR_NACK (1 << 0) /* not ACK */
  23. u32 dttx; /* send FIFO (write-only) */
  24. #define dtrx dttx /* receive FIFO (read-only) */
  25. #define I2C_DTTX_CMD (1 << 8) /* send command (slave addr) */
  26. #define I2C_DTTX_RD (1 << 0) /* read */
  27. u32 __reserved; /* no register at offset 0x08 */
  28. u32 slad; /* slave address */
  29. u32 cyc; /* clock cycle control */
  30. u32 lctl; /* clock low period control */
  31. u32 ssut; /* restart/stop setup time control */
  32. u32 dsut; /* data setup time control */
  33. u32 intr; /* interrupt status */
  34. u32 ie; /* interrupt enable */
  35. u32 ic; /* interrupt clear */
  36. #define I2C_INT_TE (1 << 9) /* TX FIFO empty */
  37. #define I2C_INT_RB (1 << 4) /* received specified bytes */
  38. #define I2C_INT_NA (1 << 2) /* no answer */
  39. #define I2C_INT_AL (1 << 1) /* arbitration lost */
  40. u32 sr; /* status register */
  41. #define I2C_SR_DB (1 << 12) /* device busy */
  42. #define I2C_SR_BB (1 << 8) /* bus busy */
  43. #define I2C_SR_RFF (1 << 3) /* Rx FIFO full */
  44. #define I2C_SR_RNE (1 << 2) /* Rx FIFO not empty */
  45. #define I2C_SR_TNF (1 << 1) /* Tx FIFO not full */
  46. #define I2C_SR_TFE (1 << 0) /* Tx FIFO empty */
  47. u32 __reserved2; /* no register at offset 0x30 */
  48. u32 rst; /* reset control */
  49. #define I2C_RST_TBRST (1 << 2) /* clear Tx FIFO */
  50. #define I2C_RST_RBRST (1 << 1) /* clear Rx FIFO */
  51. #define I2C_RST_RST (1 << 0) /* forcible bus reset */
  52. u32 bm; /* bus monitor */
  53. u32 noise; /* noise filter control */
  54. u32 tbc; /* Tx byte count setting */
  55. u32 rbc; /* Rx byte count setting */
  56. u32 tbcm; /* Tx byte count monitor */
  57. u32 rbcm; /* Rx byte count monitor */
  58. u32 brst; /* bus reset */
  59. #define I2C_BRST_FOEN (1 << 1) /* normal operation */
  60. #define I2C_BRST_RSCLO (1 << 0) /* release SCL low fixing */
  61. };
  62. #define FIOCLK 50000000
  63. struct uniphier_fi2c_dev {
  64. struct uniphier_fi2c_regs __iomem *regs; /* register base */
  65. unsigned long fioclk; /* internal operation clock */
  66. unsigned long timeout; /* time out (us) */
  67. };
  68. static int poll_status(u32 __iomem *reg, u32 flag)
  69. {
  70. int wait = 1000000; /* 1 sec is long enough */
  71. while (readl(reg) & flag) {
  72. if (wait-- < 0)
  73. return -EREMOTEIO;
  74. udelay(1);
  75. }
  76. return 0;
  77. }
  78. static int reset_bus(struct uniphier_fi2c_regs __iomem *regs)
  79. {
  80. int ret;
  81. /* bus forcible reset */
  82. writel(I2C_RST_RST, &regs->rst);
  83. ret = poll_status(&regs->rst, I2C_RST_RST);
  84. if (ret < 0)
  85. debug("error: fail to reset I2C controller\n");
  86. return ret;
  87. }
  88. static int check_device_busy(struct uniphier_fi2c_regs __iomem *regs)
  89. {
  90. int ret;
  91. ret = poll_status(&regs->sr, I2C_SR_DB);
  92. if (ret < 0) {
  93. debug("error: device busy too long. reset...\n");
  94. ret = reset_bus(regs);
  95. }
  96. return ret;
  97. }
  98. static int uniphier_fi2c_probe(struct udevice *dev)
  99. {
  100. fdt_addr_t addr;
  101. fdt_size_t size;
  102. struct uniphier_fi2c_dev *priv = dev_get_priv(dev);
  103. int ret;
  104. addr = fdtdec_get_addr_size(gd->fdt_blob, dev->of_offset, "reg",
  105. &size);
  106. priv->regs = map_sysmem(addr, size);
  107. if (!priv->regs)
  108. return -ENOMEM;
  109. priv->fioclk = FIOCLK;
  110. /* bus forcible reset */
  111. ret = reset_bus(priv->regs);
  112. if (ret < 0)
  113. return ret;
  114. writel(I2C_BRST_FOEN | I2C_BRST_RSCLO, &priv->regs->brst);
  115. return 0;
  116. }
  117. static int uniphier_fi2c_remove(struct udevice *dev)
  118. {
  119. struct uniphier_fi2c_dev *priv = dev_get_priv(dev);
  120. unmap_sysmem(priv->regs);
  121. return 0;
  122. }
  123. static int wait_for_irq(struct uniphier_fi2c_dev *dev, u32 flags,
  124. bool *stop)
  125. {
  126. u32 irq;
  127. unsigned long wait = dev->timeout;
  128. int ret = -EREMOTEIO;
  129. do {
  130. udelay(1);
  131. irq = readl(&dev->regs->intr);
  132. } while (!(irq & flags) && wait--);
  133. if (wait < 0) {
  134. debug("error: time out\n");
  135. return ret;
  136. }
  137. if (irq & I2C_INT_AL) {
  138. debug("error: arbitration lost\n");
  139. *stop = false;
  140. return ret;
  141. }
  142. if (irq & I2C_INT_NA) {
  143. debug("error: no answer\n");
  144. return ret;
  145. }
  146. return 0;
  147. }
  148. static int issue_stop(struct uniphier_fi2c_dev *dev, int old_ret)
  149. {
  150. int ret;
  151. debug("stop condition\n");
  152. writel(I2C_CR_MST | I2C_CR_STO, &dev->regs->cr);
  153. ret = poll_status(&dev->regs->sr, I2C_SR_DB);
  154. if (ret < 0)
  155. debug("error: device busy after operation\n");
  156. return old_ret ? old_ret : ret;
  157. }
  158. static int uniphier_fi2c_transmit(struct uniphier_fi2c_dev *dev, uint addr,
  159. uint len, const u8 *buf, bool *stop)
  160. {
  161. int ret;
  162. const u32 irq_flags = I2C_INT_TE | I2C_INT_NA | I2C_INT_AL;
  163. struct uniphier_fi2c_regs __iomem *regs = dev->regs;
  164. debug("%s: addr = %x, len = %d\n", __func__, addr, len);
  165. writel(I2C_DTTX_CMD | addr << 1, &regs->dttx);
  166. writel(irq_flags, &regs->ie);
  167. writel(irq_flags, &regs->ic);
  168. debug("start condition\n");
  169. writel(I2C_CR_MST | I2C_CR_STA, &regs->cr);
  170. ret = wait_for_irq(dev, irq_flags, stop);
  171. if (ret < 0)
  172. goto error;
  173. while (len--) {
  174. debug("sending %x\n", *buf);
  175. writel(*buf++, &regs->dttx);
  176. writel(irq_flags, &regs->ic);
  177. ret = wait_for_irq(dev, irq_flags, stop);
  178. if (ret < 0)
  179. goto error;
  180. }
  181. error:
  182. writel(irq_flags, &regs->ic);
  183. if (*stop)
  184. ret = issue_stop(dev, ret);
  185. return ret;
  186. }
  187. static int uniphier_fi2c_receive(struct uniphier_fi2c_dev *dev, uint addr,
  188. uint len, u8 *buf, bool *stop)
  189. {
  190. int ret = 0;
  191. const u32 irq_flags = I2C_INT_RB | I2C_INT_NA | I2C_INT_AL;
  192. struct uniphier_fi2c_regs __iomem *regs = dev->regs;
  193. debug("%s: addr = %x, len = %d\n", __func__, addr, len);
  194. /*
  195. * In case 'len == 0', only the slave address should be sent
  196. * for probing, which is covered by the transmit function.
  197. */
  198. if (len == 0)
  199. return uniphier_fi2c_transmit(dev, addr, len, buf, stop);
  200. writel(I2C_DTTX_CMD | I2C_DTTX_RD | addr << 1, &regs->dttx);
  201. writel(0, &regs->rbc);
  202. writel(irq_flags, &regs->ie);
  203. writel(irq_flags, &regs->ic);
  204. debug("start condition\n");
  205. writel(I2C_CR_MST | I2C_CR_STA | (len == 1 ? I2C_CR_NACK : 0),
  206. &regs->cr);
  207. while (len--) {
  208. ret = wait_for_irq(dev, irq_flags, stop);
  209. if (ret < 0)
  210. goto error;
  211. *buf++ = readl(&regs->dtrx);
  212. debug("received %x\n", *(buf - 1));
  213. if (len == 1)
  214. writel(I2C_CR_MST | I2C_CR_NACK, &regs->cr);
  215. writel(irq_flags, &regs->ic);
  216. }
  217. error:
  218. writel(irq_flags, &regs->ic);
  219. if (*stop)
  220. ret = issue_stop(dev, ret);
  221. return ret;
  222. }
  223. static int uniphier_fi2c_xfer(struct udevice *bus, struct i2c_msg *msg,
  224. int nmsgs)
  225. {
  226. int ret;
  227. struct uniphier_fi2c_dev *dev = dev_get_priv(bus);
  228. bool stop;
  229. ret = check_device_busy(dev->regs);
  230. if (ret < 0)
  231. return ret;
  232. for (; nmsgs > 0; nmsgs--, msg++) {
  233. /* If next message is read, skip the stop condition */
  234. stop = nmsgs > 1 && msg[1].flags & I2C_M_RD ? false : true;
  235. if (msg->flags & I2C_M_RD)
  236. ret = uniphier_fi2c_receive(dev, msg->addr, msg->len,
  237. msg->buf, &stop);
  238. else
  239. ret = uniphier_fi2c_transmit(dev, msg->addr, msg->len,
  240. msg->buf, &stop);
  241. if (ret < 0)
  242. break;
  243. }
  244. return ret;
  245. }
  246. static int uniphier_fi2c_set_bus_speed(struct udevice *bus, unsigned int speed)
  247. {
  248. int ret;
  249. unsigned int clk_count;
  250. struct uniphier_fi2c_dev *dev = dev_get_priv(bus);
  251. struct uniphier_fi2c_regs __iomem *regs = dev->regs;
  252. /* max supported frequency is 400 kHz */
  253. if (speed > 400000)
  254. return -EINVAL;
  255. ret = check_device_busy(dev->regs);
  256. if (ret < 0)
  257. return ret;
  258. /* make sure the bus is idle when changing the frequency */
  259. writel(I2C_BRST_RSCLO, &regs->brst);
  260. clk_count = dev->fioclk / speed;
  261. writel(clk_count, &regs->cyc);
  262. writel(clk_count / 2, &regs->lctl);
  263. writel(clk_count / 2, &regs->ssut);
  264. writel(clk_count / 16, &regs->dsut);
  265. writel(I2C_BRST_FOEN | I2C_BRST_RSCLO, &regs->brst);
  266. /*
  267. * Theoretically, each byte can be transferred in
  268. * 1000000 * 9 / speed usec.
  269. * This time out value is long enough.
  270. */
  271. dev->timeout = 100000000L / speed;
  272. return 0;
  273. }
  274. static const struct dm_i2c_ops uniphier_fi2c_ops = {
  275. .xfer = uniphier_fi2c_xfer,
  276. .set_bus_speed = uniphier_fi2c_set_bus_speed,
  277. };
  278. static const struct udevice_id uniphier_fi2c_of_match[] = {
  279. { .compatible = "socionext,uniphier-fi2c" },
  280. { /* sentinel */ }
  281. };
  282. U_BOOT_DRIVER(uniphier_fi2c) = {
  283. .name = "uniphier-fi2c",
  284. .id = UCLASS_I2C,
  285. .of_match = uniphier_fi2c_of_match,
  286. .probe = uniphier_fi2c_probe,
  287. .remove = uniphier_fi2c_remove,
  288. .priv_auto_alloc_size = sizeof(struct uniphier_fi2c_dev),
  289. .ops = &uniphier_fi2c_ops,
  290. };