speed.c 21 KB

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  1. /*
  2. * Copyright 2004, 2007-2011 Freescale Semiconductor, Inc.
  3. *
  4. * (C) Copyright 2003 Motorola Inc.
  5. * Xianghua Xiao, (X.Xiao@motorola.com)
  6. *
  7. * (C) Copyright 2000
  8. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  9. *
  10. * SPDX-License-Identifier: GPL-2.0+
  11. */
  12. #include <common.h>
  13. #include <ppc_asm.tmpl>
  14. #include <linux/compiler.h>
  15. #include <asm/processor.h>
  16. #include <asm/io.h>
  17. DECLARE_GLOBAL_DATA_PTR;
  18. #ifndef CONFIG_SYS_FSL_NUM_CC_PLLS
  19. #define CONFIG_SYS_FSL_NUM_CC_PLLS 6
  20. #endif
  21. /* --------------------------------------------------------------- */
  22. void get_sys_info(sys_info_t *sys_info)
  23. {
  24. volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  25. #ifdef CONFIG_FSL_IFC
  26. struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
  27. u32 ccr;
  28. #endif
  29. #ifdef CONFIG_FSL_CORENET
  30. volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR);
  31. unsigned int cpu;
  32. #ifdef CONFIG_HETROGENOUS_CLUSTERS
  33. unsigned int dsp_cpu;
  34. uint rcw_tmp1, rcw_tmp2;
  35. #endif
  36. #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
  37. int cc_group[12] = CONFIG_SYS_FSL_CLUSTER_CLOCKS;
  38. #endif
  39. __maybe_unused u32 svr;
  40. const u8 core_cplx_PLL[16] = {
  41. [ 0] = 0, /* CC1 PPL / 1 */
  42. [ 1] = 0, /* CC1 PPL / 2 */
  43. [ 2] = 0, /* CC1 PPL / 4 */
  44. [ 4] = 1, /* CC2 PPL / 1 */
  45. [ 5] = 1, /* CC2 PPL / 2 */
  46. [ 6] = 1, /* CC2 PPL / 4 */
  47. [ 8] = 2, /* CC3 PPL / 1 */
  48. [ 9] = 2, /* CC3 PPL / 2 */
  49. [10] = 2, /* CC3 PPL / 4 */
  50. [12] = 3, /* CC4 PPL / 1 */
  51. [13] = 3, /* CC4 PPL / 2 */
  52. [14] = 3, /* CC4 PPL / 4 */
  53. };
  54. const u8 core_cplx_pll_div[16] = {
  55. [ 0] = 1, /* CC1 PPL / 1 */
  56. [ 1] = 2, /* CC1 PPL / 2 */
  57. [ 2] = 4, /* CC1 PPL / 4 */
  58. [ 4] = 1, /* CC2 PPL / 1 */
  59. [ 5] = 2, /* CC2 PPL / 2 */
  60. [ 6] = 4, /* CC2 PPL / 4 */
  61. [ 8] = 1, /* CC3 PPL / 1 */
  62. [ 9] = 2, /* CC3 PPL / 2 */
  63. [10] = 4, /* CC3 PPL / 4 */
  64. [12] = 1, /* CC4 PPL / 1 */
  65. [13] = 2, /* CC4 PPL / 2 */
  66. [14] = 4, /* CC4 PPL / 4 */
  67. };
  68. uint i, freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
  69. #if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV) || \
  70. defined(CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK)
  71. uint rcw_tmp;
  72. #endif
  73. uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
  74. unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
  75. uint mem_pll_rat;
  76. sys_info->freq_systembus = sysclk;
  77. #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
  78. uint ddr_refclk_sel;
  79. unsigned int porsr1_sys_clk;
  80. porsr1_sys_clk = in_be32(&gur->porsr1) >> FSL_DCFG_PORSR1_SYSCLK_SHIFT
  81. & FSL_DCFG_PORSR1_SYSCLK_MASK;
  82. if (porsr1_sys_clk == FSL_DCFG_PORSR1_SYSCLK_DIFF)
  83. sys_info->diff_sysclk = 1;
  84. else
  85. sys_info->diff_sysclk = 0;
  86. /*
  87. * DDR_REFCLK_SEL rcw bit is used to determine if DDR PLLS
  88. * are driven by separate DDR Refclock or single source
  89. * differential clock.
  90. */
  91. ddr_refclk_sel = (in_be32(&gur->rcwsr[5]) >>
  92. FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_SHIFT) &
  93. FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_MASK;
  94. /*
  95. * For single source clocking, both ddrclock and sysclock
  96. * are driven by differential sysclock.
  97. */
  98. if (ddr_refclk_sel == FSL_CORENET2_RCWSR5_DDR_REFCLK_SINGLE_CLK)
  99. sys_info->freq_ddrbus = CONFIG_SYS_CLK_FREQ;
  100. else
  101. #endif
  102. #ifdef CONFIG_DDR_CLK_FREQ
  103. sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
  104. #else
  105. sys_info->freq_ddrbus = sysclk;
  106. #endif
  107. sys_info->freq_systembus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
  108. mem_pll_rat = (in_be32(&gur->rcwsr[0]) >>
  109. FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT)
  110. & FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
  111. #ifdef CONFIG_SYS_FSL_ERRATUM_A007212
  112. if (mem_pll_rat == 0) {
  113. mem_pll_rat = (in_be32(&gur->rcwsr[0]) >>
  114. FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT) &
  115. FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
  116. }
  117. #endif
  118. /* T4240/T4160 Rev2.0 MEM_PLL_RAT uses a value which is half of
  119. * T4240/T4160 Rev1.0. eg. It's 12 in Rev1.0, however, for Rev2.0
  120. * it uses 6.
  121. * T2080 rev 1.1 and later also use half mem_pll comparing with rev 1.0
  122. */
  123. #if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \
  124. defined(CONFIG_PPC_T4080) || defined(CONFIG_PPC_T2080) || \
  125. defined(CONFIG_PPC_T2081)
  126. svr = get_svr();
  127. switch (SVR_SOC_VER(svr)) {
  128. case SVR_T4240:
  129. case SVR_T4160:
  130. case SVR_T4120:
  131. case SVR_T4080:
  132. if (SVR_MAJ(svr) >= 2)
  133. mem_pll_rat *= 2;
  134. break;
  135. case SVR_T2080:
  136. case SVR_T2081:
  137. if ((SVR_MAJ(svr) > 1) || (SVR_MIN(svr) >= 1))
  138. mem_pll_rat *= 2;
  139. break;
  140. default:
  141. break;
  142. }
  143. #endif
  144. if (mem_pll_rat > 2)
  145. sys_info->freq_ddrbus *= mem_pll_rat;
  146. else
  147. sys_info->freq_ddrbus = sys_info->freq_systembus * mem_pll_rat;
  148. for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) {
  149. ratio[i] = (in_be32(&clk->pllcgsr[i].pllcngsr) >> 1) & 0x3f;
  150. if (ratio[i] > 4)
  151. freq_c_pll[i] = sysclk * ratio[i];
  152. else
  153. freq_c_pll[i] = sys_info->freq_systembus * ratio[i];
  154. }
  155. #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
  156. /*
  157. * As per CHASSIS2 architeture total 12 clusters are posible and
  158. * Each cluster has up to 4 cores, sharing the same PLL selection.
  159. * The cluster clock assignment is SoC defined.
  160. *
  161. * Total 4 clock groups are possible with 3 PLLs each.
  162. * as per array indices, clock group A has 0, 1, 2 numbered PLLs &
  163. * clock group B has 3, 4, 6 and so on.
  164. *
  165. * Clock group A having PLL1, PLL2, PLL3, feeding cores of any cluster
  166. * depends upon the SoC architeture. Same applies to other
  167. * clock groups and clusters.
  168. *
  169. */
  170. for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
  171. int cluster = fsl_qoriq_core_to_cluster(cpu);
  172. u32 c_pll_sel = (in_be32(&clk->clkcsr[cluster].clkcncsr) >> 27)
  173. & 0xf;
  174. u32 cplx_pll = core_cplx_PLL[c_pll_sel];
  175. cplx_pll += cc_group[cluster] - 1;
  176. sys_info->freq_processor[cpu] =
  177. freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
  178. }
  179. #ifdef CONFIG_HETROGENOUS_CLUSTERS
  180. for_each_cpu(i, dsp_cpu, cpu_num_dspcores(), cpu_dsp_mask()) {
  181. int dsp_cluster = fsl_qoriq_dsp_core_to_cluster(dsp_cpu);
  182. u32 c_pll_sel = (in_be32
  183. (&clk->clkcsr[dsp_cluster].clkcncsr) >> 27)
  184. & 0xf;
  185. u32 cplx_pll = core_cplx_PLL[c_pll_sel];
  186. cplx_pll += cc_group[dsp_cluster] - 1;
  187. sys_info->freq_processor_dsp[dsp_cpu] =
  188. freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
  189. }
  190. #endif
  191. #if defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420) || \
  192. defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
  193. #define FM1_CLK_SEL 0xe0000000
  194. #define FM1_CLK_SHIFT 29
  195. #elif defined(CONFIG_PPC_T1024) || defined(CONFIG_ARCH_T1023)
  196. #define FM1_CLK_SEL 0x00000007
  197. #define FM1_CLK_SHIFT 0
  198. #else
  199. #define PME_CLK_SEL 0xe0000000
  200. #define PME_CLK_SHIFT 29
  201. #define FM1_CLK_SEL 0x1c000000
  202. #define FM1_CLK_SHIFT 26
  203. #endif
  204. #if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV)
  205. #if defined(CONFIG_PPC_T1024) || defined(CONFIG_ARCH_T1023)
  206. rcw_tmp = in_be32(&gur->rcwsr[15]) - 4;
  207. #else
  208. rcw_tmp = in_be32(&gur->rcwsr[7]);
  209. #endif
  210. #endif
  211. #ifdef CONFIG_SYS_DPAA_PME
  212. #ifndef CONFIG_PME_PLAT_CLK_DIV
  213. switch ((rcw_tmp & PME_CLK_SEL) >> PME_CLK_SHIFT) {
  214. case 1:
  215. sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK];
  216. break;
  217. case 2:
  218. sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 2;
  219. break;
  220. case 3:
  221. sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 3;
  222. break;
  223. case 4:
  224. sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 4;
  225. break;
  226. case 6:
  227. sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK + 1] / 2;
  228. break;
  229. case 7:
  230. sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK + 1] / 3;
  231. break;
  232. default:
  233. printf("Error: Unknown PME clock select!\n");
  234. case 0:
  235. sys_info->freq_pme = sys_info->freq_systembus / 2;
  236. break;
  237. }
  238. #else
  239. sys_info->freq_pme = sys_info->freq_systembus / CONFIG_SYS_PME_CLK;
  240. #endif
  241. #endif
  242. #ifdef CONFIG_SYS_DPAA_QBMAN
  243. #ifndef CONFIG_QBMAN_CLK_DIV
  244. #define CONFIG_QBMAN_CLK_DIV 2
  245. #endif
  246. sys_info->freq_qman = sys_info->freq_systembus / CONFIG_QBMAN_CLK_DIV;
  247. #endif
  248. #if defined(CONFIG_SYS_MAPLE)
  249. #define CPRI_CLK_SEL 0x1C000000
  250. #define CPRI_CLK_SHIFT 26
  251. #define CPRI_ALT_CLK_SEL 0x00007000
  252. #define CPRI_ALT_CLK_SHIFT 12
  253. rcw_tmp1 = in_be32(&gur->rcwsr[7]); /* Reading RCW bits: 224-255*/
  254. rcw_tmp2 = in_be32(&gur->rcwsr[15]); /* Reading RCW bits: 480-511*/
  255. /* For MAPLE and CPRI frequency */
  256. switch ((rcw_tmp1 & CPRI_CLK_SEL) >> CPRI_CLK_SHIFT) {
  257. case 1:
  258. sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK];
  259. sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK];
  260. break;
  261. case 2:
  262. sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 2;
  263. sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 2;
  264. break;
  265. case 3:
  266. sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 3;
  267. sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 3;
  268. break;
  269. case 4:
  270. sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 4;
  271. sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 4;
  272. break;
  273. case 5:
  274. if (((rcw_tmp2 & CPRI_ALT_CLK_SEL)
  275. >> CPRI_ALT_CLK_SHIFT) == 6) {
  276. sys_info->freq_maple =
  277. freq_c_pll[CONFIG_SYS_CPRI_CLK - 2] / 2;
  278. sys_info->freq_cpri =
  279. freq_c_pll[CONFIG_SYS_CPRI_CLK - 2] / 2;
  280. }
  281. if (((rcw_tmp2 & CPRI_ALT_CLK_SEL)
  282. >> CPRI_ALT_CLK_SHIFT) == 7) {
  283. sys_info->freq_maple =
  284. freq_c_pll[CONFIG_SYS_CPRI_CLK - 2] / 3;
  285. sys_info->freq_cpri =
  286. freq_c_pll[CONFIG_SYS_CPRI_CLK - 2] / 3;
  287. }
  288. break;
  289. case 6:
  290. sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK + 1] / 2;
  291. sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK + 1] / 2;
  292. break;
  293. case 7:
  294. sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK + 1] / 3;
  295. sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK + 1] / 3;
  296. break;
  297. default:
  298. printf("Error: Unknown MAPLE/CPRI clock select!\n");
  299. }
  300. /* For MAPLE ULB and eTVPE frequencies */
  301. #define ULB_CLK_SEL 0x00000038
  302. #define ULB_CLK_SHIFT 3
  303. #define ETVPE_CLK_SEL 0x00000007
  304. #define ETVPE_CLK_SHIFT 0
  305. switch ((rcw_tmp2 & ULB_CLK_SEL) >> ULB_CLK_SHIFT) {
  306. case 1:
  307. sys_info->freq_maple_ulb = freq_c_pll[CONFIG_SYS_ULB_CLK];
  308. break;
  309. case 2:
  310. sys_info->freq_maple_ulb = freq_c_pll[CONFIG_SYS_ULB_CLK] / 2;
  311. break;
  312. case 3:
  313. sys_info->freq_maple_ulb = freq_c_pll[CONFIG_SYS_ULB_CLK] / 3;
  314. break;
  315. case 4:
  316. sys_info->freq_maple_ulb = freq_c_pll[CONFIG_SYS_ULB_CLK] / 4;
  317. break;
  318. case 5:
  319. sys_info->freq_maple_ulb = sys_info->freq_systembus;
  320. break;
  321. case 6:
  322. sys_info->freq_maple_ulb =
  323. freq_c_pll[CONFIG_SYS_ULB_CLK - 1] / 2;
  324. break;
  325. case 7:
  326. sys_info->freq_maple_ulb =
  327. freq_c_pll[CONFIG_SYS_ULB_CLK - 1] / 3;
  328. break;
  329. default:
  330. printf("Error: Unknown MAPLE ULB clock select!\n");
  331. }
  332. switch ((rcw_tmp2 & ETVPE_CLK_SEL) >> ETVPE_CLK_SHIFT) {
  333. case 1:
  334. sys_info->freq_maple_etvpe = freq_c_pll[CONFIG_SYS_ETVPE_CLK];
  335. break;
  336. case 2:
  337. sys_info->freq_maple_etvpe =
  338. freq_c_pll[CONFIG_SYS_ETVPE_CLK] / 2;
  339. break;
  340. case 3:
  341. sys_info->freq_maple_etvpe =
  342. freq_c_pll[CONFIG_SYS_ETVPE_CLK] / 3;
  343. break;
  344. case 4:
  345. sys_info->freq_maple_etvpe =
  346. freq_c_pll[CONFIG_SYS_ETVPE_CLK] / 4;
  347. break;
  348. case 5:
  349. sys_info->freq_maple_etvpe = sys_info->freq_systembus;
  350. break;
  351. case 6:
  352. sys_info->freq_maple_etvpe =
  353. freq_c_pll[CONFIG_SYS_ETVPE_CLK - 1] / 2;
  354. break;
  355. case 7:
  356. sys_info->freq_maple_etvpe =
  357. freq_c_pll[CONFIG_SYS_ETVPE_CLK - 1] / 3;
  358. break;
  359. default:
  360. printf("Error: Unknown MAPLE eTVPE clock select!\n");
  361. }
  362. #endif
  363. #ifdef CONFIG_SYS_DPAA_FMAN
  364. #ifndef CONFIG_FM_PLAT_CLK_DIV
  365. switch ((rcw_tmp & FM1_CLK_SEL) >> FM1_CLK_SHIFT) {
  366. case 1:
  367. sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK];
  368. break;
  369. case 2:
  370. sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 2;
  371. break;
  372. case 3:
  373. sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 3;
  374. break;
  375. case 4:
  376. sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 4;
  377. break;
  378. case 5:
  379. sys_info->freq_fman[0] = sys_info->freq_systembus;
  380. break;
  381. case 6:
  382. sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK + 1] / 2;
  383. break;
  384. case 7:
  385. sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK + 1] / 3;
  386. break;
  387. default:
  388. printf("Error: Unknown FMan1 clock select!\n");
  389. case 0:
  390. sys_info->freq_fman[0] = sys_info->freq_systembus / 2;
  391. break;
  392. }
  393. #if (CONFIG_SYS_NUM_FMAN) == 2
  394. #ifdef CONFIG_SYS_FM2_CLK
  395. #define FM2_CLK_SEL 0x00000038
  396. #define FM2_CLK_SHIFT 3
  397. rcw_tmp = in_be32(&gur->rcwsr[15]);
  398. switch ((rcw_tmp & FM2_CLK_SEL) >> FM2_CLK_SHIFT) {
  399. case 1:
  400. sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1];
  401. break;
  402. case 2:
  403. sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 2;
  404. break;
  405. case 3:
  406. sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 3;
  407. break;
  408. case 4:
  409. sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 4;
  410. break;
  411. case 5:
  412. sys_info->freq_fman[1] = sys_info->freq_systembus;
  413. break;
  414. case 6:
  415. sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK] / 2;
  416. break;
  417. case 7:
  418. sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK] / 3;
  419. break;
  420. default:
  421. printf("Error: Unknown FMan2 clock select!\n");
  422. case 0:
  423. sys_info->freq_fman[1] = sys_info->freq_systembus / 2;
  424. break;
  425. }
  426. #endif
  427. #endif /* CONFIG_SYS_NUM_FMAN == 2 */
  428. #else
  429. sys_info->freq_fman[0] = sys_info->freq_systembus / CONFIG_SYS_FM1_CLK;
  430. #endif
  431. #endif
  432. #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
  433. #if defined(CONFIG_PPC_T2080)
  434. #define ESDHC_CLK_SEL 0x00000007
  435. #define ESDHC_CLK_SHIFT 0
  436. #define ESDHC_CLK_RCWSR 15
  437. #else /* Support T1040 T1024 by now */
  438. #define ESDHC_CLK_SEL 0xe0000000
  439. #define ESDHC_CLK_SHIFT 29
  440. #define ESDHC_CLK_RCWSR 7
  441. #endif
  442. rcw_tmp = in_be32(&gur->rcwsr[ESDHC_CLK_RCWSR]);
  443. switch ((rcw_tmp & ESDHC_CLK_SEL) >> ESDHC_CLK_SHIFT) {
  444. case 1:
  445. sys_info->freq_sdhc = freq_c_pll[CONFIG_SYS_SDHC_CLK];
  446. break;
  447. case 2:
  448. sys_info->freq_sdhc = freq_c_pll[CONFIG_SYS_SDHC_CLK] / 2;
  449. break;
  450. case 3:
  451. sys_info->freq_sdhc = freq_c_pll[CONFIG_SYS_SDHC_CLK] / 3;
  452. break;
  453. #if defined(CONFIG_SYS_SDHC_CLK_2_PLL)
  454. case 4:
  455. sys_info->freq_sdhc = freq_c_pll[CONFIG_SYS_SDHC_CLK] / 4;
  456. break;
  457. #if defined(CONFIG_PPC_T2080)
  458. case 5:
  459. sys_info->freq_sdhc = freq_c_pll[1 - CONFIG_SYS_SDHC_CLK];
  460. break;
  461. #endif
  462. case 6:
  463. sys_info->freq_sdhc = freq_c_pll[1 - CONFIG_SYS_SDHC_CLK] / 2;
  464. break;
  465. case 7:
  466. sys_info->freq_sdhc = freq_c_pll[1 - CONFIG_SYS_SDHC_CLK] / 3;
  467. break;
  468. #endif
  469. default:
  470. sys_info->freq_sdhc = 0;
  471. printf("Error: Unknown SDHC peripheral clock select!\n");
  472. }
  473. #endif
  474. #else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
  475. for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
  476. u32 c_pll_sel = (in_be32(&clk->clkcsr[cpu].clkcncsr) >> 27)
  477. & 0xf;
  478. u32 cplx_pll = core_cplx_PLL[c_pll_sel];
  479. sys_info->freq_processor[cpu] =
  480. freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
  481. }
  482. #define PME_CLK_SEL 0x80000000
  483. #define FM1_CLK_SEL 0x40000000
  484. #define FM2_CLK_SEL 0x20000000
  485. #define HWA_ASYNC_DIV 0x04000000
  486. #if (CONFIG_SYS_FSL_NUM_CC_PLLS == 2)
  487. #define HWA_CC_PLL 1
  488. #elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 3)
  489. #define HWA_CC_PLL 2
  490. #elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 4)
  491. #define HWA_CC_PLL 2
  492. #else
  493. #error CONFIG_SYS_FSL_NUM_CC_PLLS not set or unknown case
  494. #endif
  495. rcw_tmp = in_be32(&gur->rcwsr[7]);
  496. #ifdef CONFIG_SYS_DPAA_PME
  497. if (rcw_tmp & PME_CLK_SEL) {
  498. if (rcw_tmp & HWA_ASYNC_DIV)
  499. sys_info->freq_pme = freq_c_pll[HWA_CC_PLL] / 4;
  500. else
  501. sys_info->freq_pme = freq_c_pll[HWA_CC_PLL] / 2;
  502. } else {
  503. sys_info->freq_pme = sys_info->freq_systembus / 2;
  504. }
  505. #endif
  506. #ifdef CONFIG_SYS_DPAA_FMAN
  507. if (rcw_tmp & FM1_CLK_SEL) {
  508. if (rcw_tmp & HWA_ASYNC_DIV)
  509. sys_info->freq_fman[0] = freq_c_pll[HWA_CC_PLL] / 4;
  510. else
  511. sys_info->freq_fman[0] = freq_c_pll[HWA_CC_PLL] / 2;
  512. } else {
  513. sys_info->freq_fman[0] = sys_info->freq_systembus / 2;
  514. }
  515. #if (CONFIG_SYS_NUM_FMAN) == 2
  516. if (rcw_tmp & FM2_CLK_SEL) {
  517. if (rcw_tmp & HWA_ASYNC_DIV)
  518. sys_info->freq_fman[1] = freq_c_pll[HWA_CC_PLL] / 4;
  519. else
  520. sys_info->freq_fman[1] = freq_c_pll[HWA_CC_PLL] / 2;
  521. } else {
  522. sys_info->freq_fman[1] = sys_info->freq_systembus / 2;
  523. }
  524. #endif
  525. #endif
  526. #ifdef CONFIG_SYS_DPAA_QBMAN
  527. sys_info->freq_qman = sys_info->freq_systembus / 2;
  528. #endif
  529. #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
  530. #ifdef CONFIG_U_QE
  531. sys_info->freq_qe = sys_info->freq_systembus / 2;
  532. #endif
  533. #else /* CONFIG_FSL_CORENET */
  534. uint plat_ratio, e500_ratio, half_freq_systembus;
  535. int i;
  536. #ifdef CONFIG_QE
  537. __maybe_unused u32 qe_ratio;
  538. #endif
  539. plat_ratio = (gur->porpllsr) & 0x0000003e;
  540. plat_ratio >>= 1;
  541. sys_info->freq_systembus = plat_ratio * CONFIG_SYS_CLK_FREQ;
  542. /* Divide before multiply to avoid integer
  543. * overflow for processor speeds above 2GHz */
  544. half_freq_systembus = sys_info->freq_systembus/2;
  545. for (i = 0; i < cpu_numcores(); i++) {
  546. e500_ratio = ((gur->porpllsr) >> (i * 8 + 16)) & 0x3f;
  547. sys_info->freq_processor[i] = e500_ratio * half_freq_systembus;
  548. }
  549. /* Note: freq_ddrbus is the MCLK frequency, not the data rate. */
  550. sys_info->freq_ddrbus = sys_info->freq_systembus;
  551. #ifdef CONFIG_DDR_CLK_FREQ
  552. {
  553. u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
  554. >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
  555. if (ddr_ratio != 0x7)
  556. sys_info->freq_ddrbus = ddr_ratio * CONFIG_DDR_CLK_FREQ;
  557. }
  558. #endif
  559. #ifdef CONFIG_QE
  560. #if defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025)
  561. sys_info->freq_qe = sys_info->freq_systembus;
  562. #else
  563. qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO)
  564. >> MPC85xx_PORPLLSR_QE_RATIO_SHIFT;
  565. sys_info->freq_qe = qe_ratio * CONFIG_SYS_CLK_FREQ;
  566. #endif
  567. #endif
  568. #ifdef CONFIG_SYS_DPAA_FMAN
  569. sys_info->freq_fman[0] = sys_info->freq_systembus;
  570. #endif
  571. #endif /* CONFIG_FSL_CORENET */
  572. #if defined(CONFIG_FSL_LBC)
  573. uint lcrr_div;
  574. #if defined(CONFIG_SYS_LBC_LCRR)
  575. /* We will program LCRR to this value later */
  576. lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV;
  577. #else
  578. lcrr_div = in_be32(&(LBC_BASE_ADDR)->lcrr) & LCRR_CLKDIV;
  579. #endif
  580. if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) {
  581. #if defined(CONFIG_FSL_CORENET)
  582. /* If this is corenet based SoC, bit-representation
  583. * for four times the clock divider values.
  584. */
  585. lcrr_div *= 4;
  586. #elif !defined(CONFIG_ARCH_MPC8540) && !defined(CONFIG_ARCH_MPC8541) && \
  587. !defined(CONFIG_ARCH_MPC8555) && !defined(CONFIG_ARCH_MPC8560)
  588. /*
  589. * Yes, the entire PQ38 family use the same
  590. * bit-representation for twice the clock divider values.
  591. */
  592. lcrr_div *= 2;
  593. #endif
  594. sys_info->freq_localbus = sys_info->freq_systembus / lcrr_div;
  595. } else {
  596. /* In case anyone cares what the unknown value is */
  597. sys_info->freq_localbus = lcrr_div;
  598. }
  599. #endif
  600. #if defined(CONFIG_FSL_IFC)
  601. ccr = ifc_in32(&ifc_regs.gregs->ifc_ccr);
  602. ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1;
  603. sys_info->freq_localbus = sys_info->freq_systembus / ccr;
  604. #endif
  605. }
  606. int get_clocks (void)
  607. {
  608. sys_info_t sys_info;
  609. #ifdef CONFIG_ARCH_MPC8544
  610. volatile ccsr_gur_t *gur = (void *) CONFIG_SYS_MPC85xx_GUTS_ADDR;
  611. #endif
  612. #if defined(CONFIG_CPM2)
  613. volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
  614. uint sccr, dfbrg;
  615. /* set VCO = 4 * BRG */
  616. cpm->im_cpm_intctl.sccr &= 0xfffffffc;
  617. sccr = cpm->im_cpm_intctl.sccr;
  618. dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT;
  619. #endif
  620. get_sys_info (&sys_info);
  621. gd->cpu_clk = sys_info.freq_processor[0];
  622. gd->bus_clk = sys_info.freq_systembus;
  623. gd->mem_clk = sys_info.freq_ddrbus;
  624. gd->arch.lbc_clk = sys_info.freq_localbus;
  625. #ifdef CONFIG_QE
  626. gd->arch.qe_clk = sys_info.freq_qe;
  627. gd->arch.brg_clk = gd->arch.qe_clk / 2;
  628. #endif
  629. /*
  630. * The base clock for I2C depends on the actual SOC. Unfortunately,
  631. * there is no pattern that can be used to determine the frequency, so
  632. * the only choice is to look up the actual SOC number and use the value
  633. * for that SOC. This information is taken from application note
  634. * AN2919.
  635. */
  636. #if defined(CONFIG_ARCH_MPC8540) || defined(CONFIG_ARCH_MPC8541) || \
  637. defined(CONFIG_ARCH_MPC8560) || defined(CONFIG_ARCH_MPC8555) || \
  638. defined(CONFIG_ARCH_P1022)
  639. gd->arch.i2c1_clk = sys_info.freq_systembus;
  640. #elif defined(CONFIG_ARCH_MPC8544)
  641. /*
  642. * On the 8544, the I2C clock is the same as the SEC clock. This can be
  643. * either CCB/2 or CCB/3, depending on the value of cfg_sec_freq. See
  644. * 4.4.3.3 of the 8544 RM. Note that this might actually work for all
  645. * 85xx, but only the 8544 has cfg_sec_freq, so it's unknown if the
  646. * PORDEVSR2_SEC_CFG bit is 0 on all 85xx boards that are not an 8544.
  647. */
  648. if (gur->pordevsr2 & MPC85xx_PORDEVSR2_SEC_CFG)
  649. gd->arch.i2c1_clk = sys_info.freq_systembus / 3;
  650. else
  651. gd->arch.i2c1_clk = sys_info.freq_systembus / 2;
  652. #else
  653. /* Most 85xx SOCs use CCB/2, so this is the default behavior. */
  654. gd->arch.i2c1_clk = sys_info.freq_systembus / 2;
  655. #endif
  656. gd->arch.i2c2_clk = gd->arch.i2c1_clk;
  657. #if defined(CONFIG_FSL_ESDHC)
  658. #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
  659. gd->arch.sdhc_clk = sys_info.freq_sdhc / 2;
  660. #else
  661. #if defined(CONFIG_ARCH_MPC8569) || defined(CONFIG_ARCH_P1010)
  662. gd->arch.sdhc_clk = gd->bus_clk;
  663. #else
  664. gd->arch.sdhc_clk = gd->bus_clk / 2;
  665. #endif
  666. #endif
  667. #endif /* defined(CONFIG_FSL_ESDHC) */
  668. #if defined(CONFIG_CPM2)
  669. gd->arch.vco_out = 2*sys_info.freq_systembus;
  670. gd->arch.cpm_clk = gd->arch.vco_out / 2;
  671. gd->arch.scc_clk = gd->arch.vco_out / 4;
  672. gd->arch.brg_clk = gd->arch.vco_out / (1 << (2 * (dfbrg + 1)));
  673. #endif
  674. if(gd->cpu_clk != 0) return (0);
  675. else return (1);
  676. }
  677. /********************************************
  678. * get_bus_freq
  679. * return system bus freq in Hz
  680. *********************************************/
  681. ulong get_bus_freq (ulong dummy)
  682. {
  683. return gd->bus_clk;
  684. }
  685. /********************************************
  686. * get_ddr_freq
  687. * return ddr bus freq in Hz
  688. *********************************************/
  689. ulong get_ddr_freq (ulong dummy)
  690. {
  691. return gd->mem_clk;
  692. }