ehci-s5p.c 2.8 KB

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  1. /*
  2. * SAMSUNG S5P USB HOST EHCI Controller
  3. *
  4. * Copyright (C) 2012 Samsung Electronics Co.Ltd
  5. * Vivek Gautam <gautam.vivek@samsung.com>
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License as
  9. * published by the Free Software Foundation; either version 2 of
  10. * the License, or (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
  20. * MA 02110-1301 USA
  21. */
  22. #include <common.h>
  23. #include <usb.h>
  24. #include <asm/arch/cpu.h>
  25. #include <asm/arch/ehci-s5p.h>
  26. #include "ehci.h"
  27. #include "ehci-core.h"
  28. /* Setup the EHCI host controller. */
  29. static void setup_usb_phy(struct s5p_usb_phy *usb)
  30. {
  31. clrbits_le32(&usb->usbphyctrl0,
  32. HOST_CTRL0_FSEL_MASK |
  33. HOST_CTRL0_COMMONON_N |
  34. /* HOST Phy setting */
  35. HOST_CTRL0_PHYSWRST |
  36. HOST_CTRL0_PHYSWRSTALL |
  37. HOST_CTRL0_SIDDQ |
  38. HOST_CTRL0_FORCESUSPEND |
  39. HOST_CTRL0_FORCESLEEP);
  40. setbits_le32(&usb->usbphyctrl0,
  41. /* Setting up the ref freq */
  42. (CLK_24MHZ << 16) |
  43. /* HOST Phy setting */
  44. HOST_CTRL0_LINKSWRST |
  45. HOST_CTRL0_UTMISWRST);
  46. udelay(10);
  47. clrbits_le32(&usb->usbphyctrl0,
  48. HOST_CTRL0_LINKSWRST |
  49. HOST_CTRL0_UTMISWRST);
  50. udelay(20);
  51. /* EHCI Ctrl setting */
  52. setbits_le32(&usb->ehcictrl,
  53. EHCICTRL_ENAINCRXALIGN |
  54. EHCICTRL_ENAINCR4 |
  55. EHCICTRL_ENAINCR8 |
  56. EHCICTRL_ENAINCR16);
  57. }
  58. /* Reset the EHCI host controller. */
  59. static void reset_usb_phy(struct s5p_usb_phy *usb)
  60. {
  61. /* HOST_PHY reset */
  62. setbits_le32(&usb->usbphyctrl0,
  63. HOST_CTRL0_PHYSWRST |
  64. HOST_CTRL0_PHYSWRSTALL |
  65. HOST_CTRL0_SIDDQ |
  66. HOST_CTRL0_FORCESUSPEND |
  67. HOST_CTRL0_FORCESLEEP);
  68. }
  69. /*
  70. * EHCI-initialization
  71. * Create the appropriate control structures to manage
  72. * a new EHCI host controller.
  73. */
  74. int ehci_hcd_init(void)
  75. {
  76. struct s5p_usb_phy *usb;
  77. usb = (struct s5p_usb_phy *)samsung_get_base_usb_phy();
  78. setup_usb_phy(usb);
  79. hccr = (struct ehci_hccr *)(EXYNOS5_USB_HOST_EHCI_BASE);
  80. hcor = (struct ehci_hcor *)((uint32_t) hccr
  81. + HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
  82. debug("Exynos5-ehci: init hccr %x and hcor %x hc_length %d\n",
  83. (uint32_t)hccr, (uint32_t)hcor,
  84. (uint32_t)HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
  85. return 0;
  86. }
  87. /*
  88. * Destroy the appropriate control structures corresponding
  89. * the EHCI host controller.
  90. */
  91. int ehci_hcd_stop()
  92. {
  93. struct s5p_usb_phy *usb;
  94. usb = (struct s5p_usb_phy *)samsung_get_base_usb_phy();
  95. reset_usb_phy(usb);
  96. return 0;
  97. }