mpc5xxx_fec.c 24 KB

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  1. /*
  2. * (C) Copyright 2003-2010
  3. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4. *
  5. * This file is based on mpc4200fec.c,
  6. * (C) Copyright Motorola, Inc., 2000
  7. */
  8. #include <common.h>
  9. #include <mpc5xxx.h>
  10. #include <mpc5xxx_sdma.h>
  11. #include <malloc.h>
  12. #include <net.h>
  13. #include <netdev.h>
  14. #include <miiphy.h>
  15. #include "mpc5xxx_fec.h"
  16. DECLARE_GLOBAL_DATA_PTR;
  17. /* #define DEBUG 0x28 */
  18. #if !(defined(CONFIG_MII) || defined(CONFIG_CMD_MII))
  19. #error "CONFIG_MII has to be defined!"
  20. #endif
  21. #if (DEBUG & 0x60)
  22. static void tfifo_print(char *devname, mpc5xxx_fec_priv *fec);
  23. static void rfifo_print(char *devname, mpc5xxx_fec_priv *fec);
  24. #endif /* DEBUG */
  25. typedef struct {
  26. uint8 data[1500]; /* actual data */
  27. int length; /* actual length */
  28. int used; /* buffer in use or not */
  29. uint8 head[16]; /* MAC header(6 + 6 + 2) + 2(aligned) */
  30. } NBUF;
  31. int fec5xxx_miiphy_read(const char *devname, uint8 phyAddr, uint8 regAddr, uint16 *retVal);
  32. int fec5xxx_miiphy_write(const char *devname, uint8 phyAddr, uint8 regAddr, uint16 data);
  33. static int mpc5xxx_fec_init_phy(struct eth_device *dev, bd_t * bis);
  34. /********************************************************************/
  35. #if (DEBUG & 0x2)
  36. static void mpc5xxx_fec_phydump (char *devname)
  37. {
  38. uint16 phyStatus, i;
  39. uint8 phyAddr = CONFIG_PHY_ADDR;
  40. uint8 reg_mask[] = {
  41. #if CONFIG_PHY_TYPE == 0x79c874 /* AMD Am79C874 */
  42. /* regs to print: 0...7, 16...19, 21, 23, 24 */
  43. 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0,
  44. 1, 1, 1, 1, 0, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0,
  45. #else
  46. /* regs to print: 0...8, 16...20 */
  47. 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0,
  48. 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  49. #endif
  50. };
  51. for (i = 0; i < 32; i++) {
  52. if (reg_mask[i]) {
  53. miiphy_read(devname, phyAddr, i, &phyStatus);
  54. printf("Mii reg %d: 0x%04x\n", i, phyStatus);
  55. }
  56. }
  57. }
  58. #endif
  59. /********************************************************************/
  60. static int mpc5xxx_fec_rbd_init(mpc5xxx_fec_priv *fec)
  61. {
  62. int ix;
  63. char *data;
  64. static int once = 0;
  65. for (ix = 0; ix < FEC_RBD_NUM; ix++) {
  66. if (!once) {
  67. data = (char *)malloc(FEC_MAX_PKT_SIZE);
  68. if (data == NULL) {
  69. printf ("RBD INIT FAILED\n");
  70. return -1;
  71. }
  72. fec->rbdBase[ix].dataPointer = (uint32)data;
  73. }
  74. fec->rbdBase[ix].status = FEC_RBD_EMPTY;
  75. fec->rbdBase[ix].dataLength = 0;
  76. }
  77. once ++;
  78. /*
  79. * have the last RBD to close the ring
  80. */
  81. fec->rbdBase[ix - 1].status |= FEC_RBD_WRAP;
  82. fec->rbdIndex = 0;
  83. return 0;
  84. }
  85. /********************************************************************/
  86. static void mpc5xxx_fec_tbd_init(mpc5xxx_fec_priv *fec)
  87. {
  88. int ix;
  89. for (ix = 0; ix < FEC_TBD_NUM; ix++) {
  90. fec->tbdBase[ix].status = 0;
  91. }
  92. /*
  93. * Have the last TBD to close the ring
  94. */
  95. fec->tbdBase[ix - 1].status |= FEC_TBD_WRAP;
  96. /*
  97. * Initialize some indices
  98. */
  99. fec->tbdIndex = 0;
  100. fec->usedTbdIndex = 0;
  101. fec->cleanTbdNum = FEC_TBD_NUM;
  102. }
  103. /********************************************************************/
  104. static void mpc5xxx_fec_rbd_clean(mpc5xxx_fec_priv *fec, volatile FEC_RBD * pRbd)
  105. {
  106. /*
  107. * Reset buffer descriptor as empty
  108. */
  109. if ((fec->rbdIndex) == (FEC_RBD_NUM - 1))
  110. pRbd->status = (FEC_RBD_WRAP | FEC_RBD_EMPTY);
  111. else
  112. pRbd->status = FEC_RBD_EMPTY;
  113. pRbd->dataLength = 0;
  114. /*
  115. * Now, we have an empty RxBD, restart the SmartDMA receive task
  116. */
  117. SDMA_TASK_ENABLE(FEC_RECV_TASK_NO);
  118. /*
  119. * Increment BD count
  120. */
  121. fec->rbdIndex = (fec->rbdIndex + 1) % FEC_RBD_NUM;
  122. }
  123. /********************************************************************/
  124. static void mpc5xxx_fec_tbd_scrub(mpc5xxx_fec_priv *fec)
  125. {
  126. volatile FEC_TBD *pUsedTbd;
  127. #if (DEBUG & 0x1)
  128. printf ("tbd_scrub: fec->cleanTbdNum = %d, fec->usedTbdIndex = %d\n",
  129. fec->cleanTbdNum, fec->usedTbdIndex);
  130. #endif
  131. /*
  132. * process all the consumed TBDs
  133. */
  134. while (fec->cleanTbdNum < FEC_TBD_NUM) {
  135. pUsedTbd = &fec->tbdBase[fec->usedTbdIndex];
  136. if (pUsedTbd->status & FEC_TBD_READY) {
  137. #if (DEBUG & 0x20)
  138. printf("Cannot clean TBD %d, in use\n", fec->cleanTbdNum);
  139. #endif
  140. return;
  141. }
  142. /*
  143. * clean this buffer descriptor
  144. */
  145. if (fec->usedTbdIndex == (FEC_TBD_NUM - 1))
  146. pUsedTbd->status = FEC_TBD_WRAP;
  147. else
  148. pUsedTbd->status = 0;
  149. /*
  150. * update some indeces for a correct handling of the TBD ring
  151. */
  152. fec->cleanTbdNum++;
  153. fec->usedTbdIndex = (fec->usedTbdIndex + 1) % FEC_TBD_NUM;
  154. }
  155. }
  156. /********************************************************************/
  157. static void mpc5xxx_fec_set_hwaddr(mpc5xxx_fec_priv *fec, char *mac)
  158. {
  159. uint8 currByte; /* byte for which to compute the CRC */
  160. int byte; /* loop - counter */
  161. int bit; /* loop - counter */
  162. uint32 crc = 0xffffffff; /* initial value */
  163. /*
  164. * The algorithm used is the following:
  165. * we loop on each of the six bytes of the provided address,
  166. * and we compute the CRC by left-shifting the previous
  167. * value by one position, so that each bit in the current
  168. * byte of the address may contribute the calculation. If
  169. * the latter and the MSB in the CRC are different, then
  170. * the CRC value so computed is also ex-ored with the
  171. * "polynomium generator". The current byte of the address
  172. * is also shifted right by one bit at each iteration.
  173. * This is because the CRC generatore in hardware is implemented
  174. * as a shift-register with as many ex-ores as the radixes
  175. * in the polynomium. This suggests that we represent the
  176. * polynomiumm itself as a 32-bit constant.
  177. */
  178. for (byte = 0; byte < 6; byte++) {
  179. currByte = mac[byte];
  180. for (bit = 0; bit < 8; bit++) {
  181. if ((currByte & 0x01) ^ (crc & 0x01)) {
  182. crc >>= 1;
  183. crc = crc ^ 0xedb88320;
  184. } else {
  185. crc >>= 1;
  186. }
  187. currByte >>= 1;
  188. }
  189. }
  190. crc = crc >> 26;
  191. /*
  192. * Set individual hash table register
  193. */
  194. if (crc >= 32) {
  195. fec->eth->iaddr1 = (1 << (crc - 32));
  196. fec->eth->iaddr2 = 0;
  197. } else {
  198. fec->eth->iaddr1 = 0;
  199. fec->eth->iaddr2 = (1 << crc);
  200. }
  201. /*
  202. * Set physical address
  203. */
  204. fec->eth->paddr1 = (mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3];
  205. fec->eth->paddr2 = (mac[4] << 24) + (mac[5] << 16) + 0x8808;
  206. }
  207. /********************************************************************/
  208. static int mpc5xxx_fec_init(struct eth_device *dev, bd_t * bis)
  209. {
  210. mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
  211. struct mpc5xxx_sdma *sdma = (struct mpc5xxx_sdma *)MPC5XXX_SDMA;
  212. #if (DEBUG & 0x1)
  213. printf ("mpc5xxx_fec_init... Begin\n");
  214. #endif
  215. mpc5xxx_fec_init_phy(dev, bis);
  216. /*
  217. * Initialize RxBD/TxBD rings
  218. */
  219. mpc5xxx_fec_rbd_init(fec);
  220. mpc5xxx_fec_tbd_init(fec);
  221. /*
  222. * Clear FEC-Lite interrupt event register(IEVENT)
  223. */
  224. fec->eth->ievent = 0xffffffff;
  225. /*
  226. * Set interrupt mask register
  227. */
  228. fec->eth->imask = 0x00000000;
  229. /*
  230. * Set FEC-Lite receive control register(R_CNTRL):
  231. */
  232. if (fec->xcv_type == SEVENWIRE) {
  233. /*
  234. * Frame length=1518; 7-wire mode
  235. */
  236. fec->eth->r_cntrl = 0x05ee0020; /*0x05ee0000;FIXME */
  237. } else {
  238. /*
  239. * Frame length=1518; MII mode;
  240. */
  241. fec->eth->r_cntrl = 0x05ee0024; /*0x05ee0004;FIXME */
  242. }
  243. fec->eth->x_cntrl = 0x00000000; /* half-duplex, heartbeat disabled */
  244. /*
  245. * Set Opcode/Pause Duration Register
  246. */
  247. fec->eth->op_pause = 0x00010020; /*FIXME 0xffff0020; */
  248. /*
  249. * Set Rx FIFO alarm and granularity value
  250. */
  251. fec->eth->rfifo_cntrl = 0x0c000000
  252. | (fec->eth->rfifo_cntrl & ~0x0f000000);
  253. fec->eth->rfifo_alarm = 0x0000030c;
  254. #if (DEBUG & 0x22)
  255. if (fec->eth->rfifo_status & 0x00700000 ) {
  256. printf("mpc5xxx_fec_init() RFIFO error\n");
  257. }
  258. #endif
  259. /*
  260. * Set Tx FIFO granularity value
  261. */
  262. fec->eth->tfifo_cntrl = 0x0c000000
  263. | (fec->eth->tfifo_cntrl & ~0x0f000000);
  264. #if (DEBUG & 0x2)
  265. printf("tfifo_status: 0x%08x\n", fec->eth->tfifo_status);
  266. printf("tfifo_alarm: 0x%08x\n", fec->eth->tfifo_alarm);
  267. #endif
  268. /*
  269. * Set transmit fifo watermark register(X_WMRK), default = 64
  270. */
  271. fec->eth->tfifo_alarm = 0x00000080;
  272. fec->eth->x_wmrk = 0x2;
  273. /*
  274. * Set individual address filter for unicast address
  275. * and set physical address registers.
  276. */
  277. mpc5xxx_fec_set_hwaddr(fec, (char *)dev->enetaddr);
  278. /*
  279. * Set multicast address filter
  280. */
  281. fec->eth->gaddr1 = 0x00000000;
  282. fec->eth->gaddr2 = 0x00000000;
  283. /*
  284. * Turn ON cheater FSM: ????
  285. */
  286. fec->eth->xmit_fsm = 0x03000000;
  287. /*
  288. * Turn off COMM bus prefetch in the MPC5200 BestComm. It doesn't
  289. * work w/ the current receive task.
  290. */
  291. sdma->PtdCntrl |= 0x00000001;
  292. /*
  293. * Set priority of different initiators
  294. */
  295. sdma->IPR0 = 7; /* always */
  296. sdma->IPR3 = 6; /* Eth RX */
  297. sdma->IPR4 = 5; /* Eth Tx */
  298. /*
  299. * Clear SmartDMA task interrupt pending bits
  300. */
  301. SDMA_CLEAR_IEVENT(FEC_RECV_TASK_NO);
  302. /*
  303. * Initialize SmartDMA parameters stored in SRAM
  304. */
  305. *(volatile int *)FEC_TBD_BASE = (int)fec->tbdBase;
  306. *(volatile int *)FEC_RBD_BASE = (int)fec->rbdBase;
  307. *(volatile int *)FEC_TBD_NEXT = (int)fec->tbdBase;
  308. *(volatile int *)FEC_RBD_NEXT = (int)fec->rbdBase;
  309. /*
  310. * Enable FEC-Lite controller
  311. */
  312. fec->eth->ecntrl |= 0x00000006;
  313. #if (DEBUG & 0x2)
  314. if (fec->xcv_type != SEVENWIRE)
  315. mpc5xxx_fec_phydump (dev->name);
  316. #endif
  317. /*
  318. * Enable SmartDMA receive task
  319. */
  320. SDMA_TASK_ENABLE(FEC_RECV_TASK_NO);
  321. #if (DEBUG & 0x1)
  322. printf("mpc5xxx_fec_init... Done \n");
  323. #endif
  324. return 1;
  325. }
  326. /********************************************************************/
  327. static int mpc5xxx_fec_init_phy(struct eth_device *dev, bd_t * bis)
  328. {
  329. mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
  330. const uint8 phyAddr = CONFIG_PHY_ADDR; /* Only one PHY */
  331. static int initialized = 0;
  332. if(initialized)
  333. return 0;
  334. initialized = 1;
  335. #if (DEBUG & 0x1)
  336. printf ("mpc5xxx_fec_init_phy... Begin\n");
  337. #endif
  338. /*
  339. * Initialize GPIO pins
  340. */
  341. if (fec->xcv_type == SEVENWIRE) {
  342. /* 10MBit with 7-wire operation */
  343. #if defined(CONFIG_TOTAL5200)
  344. /* 7-wire and USB2 on Ethernet */
  345. *(vu_long *)MPC5XXX_GPS_PORT_CONFIG |= 0x00030000;
  346. #else /* !CONFIG_TOTAL5200 */
  347. /* 7-wire only */
  348. *(vu_long *)MPC5XXX_GPS_PORT_CONFIG |= 0x00020000;
  349. #endif /* CONFIG_TOTAL5200 */
  350. } else {
  351. /* 100MBit with MD operation */
  352. *(vu_long *)MPC5XXX_GPS_PORT_CONFIG |= 0x00050000;
  353. }
  354. /*
  355. * Clear FEC-Lite interrupt event register(IEVENT)
  356. */
  357. fec->eth->ievent = 0xffffffff;
  358. /*
  359. * Set interrupt mask register
  360. */
  361. fec->eth->imask = 0x00000000;
  362. /*
  363. * In original Promess-provided code PHY initialization is disabled with the
  364. * following comment: "Phy initialization is DISABLED for now. There was a
  365. * problem with running 100 Mbps on PRO board". Thus we temporarily disable
  366. * PHY initialization for the Motion-PRO board, until a proper fix is found.
  367. */
  368. if (fec->xcv_type != SEVENWIRE) {
  369. /*
  370. * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
  371. * and do not drop the Preamble.
  372. */
  373. fec->eth->mii_speed = (((gd->ipb_clk >> 20) / 5) << 1); /* No MII for 7-wire mode */
  374. }
  375. if (fec->xcv_type != SEVENWIRE) {
  376. /*
  377. * Initialize PHY(LXT971A):
  378. *
  379. * Generally, on power up, the LXT971A reads its configuration
  380. * pins to check for forced operation, If not cofigured for
  381. * forced operation, it uses auto-negotiation/parallel detection
  382. * to automatically determine line operating conditions.
  383. * If the PHY device on the other side of the link supports
  384. * auto-negotiation, the LXT971A auto-negotiates with it
  385. * using Fast Link Pulse(FLP) Bursts. If the PHY partner does not
  386. * support auto-negotiation, the LXT971A automatically detects
  387. * the presence of either link pulses(10Mbps PHY) or Idle
  388. * symbols(100Mbps) and sets its operating conditions accordingly.
  389. *
  390. * When auto-negotiation is controlled by software, the following
  391. * steps are recommended.
  392. *
  393. * Note:
  394. * The physical address is dependent on hardware configuration.
  395. *
  396. */
  397. int timeout = 1;
  398. uint16 phyStatus;
  399. /*
  400. * Reset PHY, then delay 300ns
  401. */
  402. miiphy_write(dev->name, phyAddr, 0x0, 0x8000);
  403. udelay(1000);
  404. #if defined(CONFIG_UC101) || defined(CONFIG_MUCMC52)
  405. /* Set the LED configuration Register for the UC101
  406. and MUCMC52 Board */
  407. miiphy_write(dev->name, phyAddr, 0x14, 0x4122);
  408. #endif
  409. if (fec->xcv_type == MII10) {
  410. /*
  411. * Force 10Base-T, FDX operation
  412. */
  413. #if (DEBUG & 0x2)
  414. printf("Forcing 10 Mbps ethernet link... ");
  415. #endif
  416. miiphy_read(dev->name, phyAddr, 0x1, &phyStatus);
  417. /*
  418. miiphy_write(dev->name, fec, phyAddr, 0x0, 0x0100);
  419. */
  420. miiphy_write(dev->name, phyAddr, 0x0, 0x0180);
  421. timeout = 20;
  422. do { /* wait for link status to go down */
  423. udelay(10000);
  424. if ((timeout--) == 0) {
  425. #if (DEBUG & 0x2)
  426. printf("hmmm, should not have waited...");
  427. #endif
  428. break;
  429. }
  430. miiphy_read(dev->name, phyAddr, 0x1, &phyStatus);
  431. #if (DEBUG & 0x2)
  432. printf("=");
  433. #endif
  434. } while ((phyStatus & 0x0004)); /* !link up */
  435. timeout = 1000;
  436. do { /* wait for link status to come back up */
  437. udelay(10000);
  438. if ((timeout--) == 0) {
  439. printf("failed. Link is down.\n");
  440. break;
  441. }
  442. miiphy_read(dev->name, phyAddr, 0x1, &phyStatus);
  443. #if (DEBUG & 0x2)
  444. printf("+");
  445. #endif
  446. } while (!(phyStatus & 0x0004)); /* !link up */
  447. #if (DEBUG & 0x2)
  448. printf ("done.\n");
  449. #endif
  450. } else { /* MII100 */
  451. /*
  452. * Set the auto-negotiation advertisement register bits
  453. */
  454. miiphy_write(dev->name, phyAddr, 0x4, 0x01e1);
  455. /*
  456. * Set MDIO bit 0.12 = 1(&& bit 0.9=1?) to enable auto-negotiation
  457. */
  458. miiphy_write(dev->name, phyAddr, 0x0, 0x1200);
  459. /*
  460. * Wait for AN completion
  461. */
  462. timeout = 5000;
  463. do {
  464. udelay(1000);
  465. if ((timeout--) == 0) {
  466. #if (DEBUG & 0x2)
  467. printf("PHY auto neg 0 failed...\n");
  468. #endif
  469. return -1;
  470. }
  471. if (miiphy_read(dev->name, phyAddr, 0x1, &phyStatus) != 0) {
  472. #if (DEBUG & 0x2)
  473. printf("PHY auto neg 1 failed 0x%04x...\n", phyStatus);
  474. #endif
  475. return -1;
  476. }
  477. } while (!(phyStatus & 0x0004));
  478. #if (DEBUG & 0x2)
  479. printf("PHY auto neg complete! \n");
  480. #endif
  481. }
  482. }
  483. #if (DEBUG & 0x2)
  484. if (fec->xcv_type != SEVENWIRE)
  485. mpc5xxx_fec_phydump (dev->name);
  486. #endif
  487. #if (DEBUG & 0x1)
  488. printf("mpc5xxx_fec_init_phy... Done \n");
  489. #endif
  490. return 1;
  491. }
  492. /********************************************************************/
  493. static void mpc5xxx_fec_halt(struct eth_device *dev)
  494. {
  495. struct mpc5xxx_sdma *sdma = (struct mpc5xxx_sdma *)MPC5XXX_SDMA;
  496. mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
  497. int counter = 0xffff;
  498. #if (DEBUG & 0x2)
  499. if (fec->xcv_type != SEVENWIRE)
  500. mpc5xxx_fec_phydump (dev->name);
  501. #endif
  502. /*
  503. * mask FEC chip interrupts
  504. */
  505. fec->eth->imask = 0;
  506. /*
  507. * issue graceful stop command to the FEC transmitter if necessary
  508. */
  509. fec->eth->x_cntrl |= 0x00000001;
  510. /*
  511. * wait for graceful stop to register
  512. */
  513. while ((counter--) && (!(fec->eth->ievent & 0x10000000))) ;
  514. /*
  515. * Disable SmartDMA tasks
  516. */
  517. SDMA_TASK_DISABLE (FEC_XMIT_TASK_NO);
  518. SDMA_TASK_DISABLE (FEC_RECV_TASK_NO);
  519. /*
  520. * Turn on COMM bus prefetch in the MPC5200 BestComm after we're
  521. * done. It doesn't work w/ the current receive task.
  522. */
  523. sdma->PtdCntrl &= ~0x00000001;
  524. /*
  525. * Disable the Ethernet Controller
  526. */
  527. fec->eth->ecntrl &= 0xfffffffd;
  528. /*
  529. * Clear FIFO status registers
  530. */
  531. fec->eth->rfifo_status &= 0x00700000;
  532. fec->eth->tfifo_status &= 0x00700000;
  533. fec->eth->reset_cntrl = 0x01000000;
  534. /*
  535. * Issue a reset command to the FEC chip
  536. */
  537. fec->eth->ecntrl |= 0x1;
  538. /*
  539. * wait at least 16 clock cycles
  540. */
  541. udelay(10);
  542. /* don't leave the MII speed set to zero */
  543. if (fec->xcv_type != SEVENWIRE) {
  544. /*
  545. * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
  546. * and do not drop the Preamble.
  547. */
  548. fec->eth->mii_speed = (((gd->ipb_clk >> 20) / 5) << 1); /* No MII for 7-wire mode */
  549. }
  550. #if (DEBUG & 0x3)
  551. printf("Ethernet task stopped\n");
  552. #endif
  553. }
  554. #if (DEBUG & 0x60)
  555. /********************************************************************/
  556. static void tfifo_print(char *devname, mpc5xxx_fec_priv *fec)
  557. {
  558. uint16 phyAddr = CONFIG_PHY_ADDR;
  559. uint16 phyStatus;
  560. if ((fec->eth->tfifo_lrf_ptr != fec->eth->tfifo_lwf_ptr)
  561. || (fec->eth->tfifo_rdptr != fec->eth->tfifo_wrptr)) {
  562. miiphy_read(devname, phyAddr, 0x1, &phyStatus);
  563. printf("\nphyStatus: 0x%04x\n", phyStatus);
  564. printf("ecntrl: 0x%08x\n", fec->eth->ecntrl);
  565. printf("ievent: 0x%08x\n", fec->eth->ievent);
  566. printf("x_status: 0x%08x\n", fec->eth->x_status);
  567. printf("tfifo: status 0x%08x\n", fec->eth->tfifo_status);
  568. printf(" control 0x%08x\n", fec->eth->tfifo_cntrl);
  569. printf(" lrfp 0x%08x\n", fec->eth->tfifo_lrf_ptr);
  570. printf(" lwfp 0x%08x\n", fec->eth->tfifo_lwf_ptr);
  571. printf(" alarm 0x%08x\n", fec->eth->tfifo_alarm);
  572. printf(" readptr 0x%08x\n", fec->eth->tfifo_rdptr);
  573. printf(" writptr 0x%08x\n", fec->eth->tfifo_wrptr);
  574. }
  575. }
  576. static void rfifo_print(char *devname, mpc5xxx_fec_priv *fec)
  577. {
  578. uint16 phyAddr = CONFIG_PHY_ADDR;
  579. uint16 phyStatus;
  580. if ((fec->eth->rfifo_lrf_ptr != fec->eth->rfifo_lwf_ptr)
  581. || (fec->eth->rfifo_rdptr != fec->eth->rfifo_wrptr)) {
  582. miiphy_read(devname, phyAddr, 0x1, &phyStatus);
  583. printf("\nphyStatus: 0x%04x\n", phyStatus);
  584. printf("ecntrl: 0x%08x\n", fec->eth->ecntrl);
  585. printf("ievent: 0x%08x\n", fec->eth->ievent);
  586. printf("x_status: 0x%08x\n", fec->eth->x_status);
  587. printf("rfifo: status 0x%08x\n", fec->eth->rfifo_status);
  588. printf(" control 0x%08x\n", fec->eth->rfifo_cntrl);
  589. printf(" lrfp 0x%08x\n", fec->eth->rfifo_lrf_ptr);
  590. printf(" lwfp 0x%08x\n", fec->eth->rfifo_lwf_ptr);
  591. printf(" alarm 0x%08x\n", fec->eth->rfifo_alarm);
  592. printf(" readptr 0x%08x\n", fec->eth->rfifo_rdptr);
  593. printf(" writptr 0x%08x\n", fec->eth->rfifo_wrptr);
  594. }
  595. }
  596. #endif /* DEBUG */
  597. /********************************************************************/
  598. static int mpc5xxx_fec_send(struct eth_device *dev, volatile void *eth_data,
  599. int data_length)
  600. {
  601. /*
  602. * This routine transmits one frame. This routine only accepts
  603. * 6-byte Ethernet addresses.
  604. */
  605. mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
  606. volatile FEC_TBD *pTbd;
  607. #if (DEBUG & 0x20)
  608. printf("tbd status: 0x%04x\n", fec->tbdBase[0].status);
  609. tfifo_print(dev->name, fec);
  610. #endif
  611. /*
  612. * Clear Tx BD ring at first
  613. */
  614. mpc5xxx_fec_tbd_scrub(fec);
  615. /*
  616. * Check for valid length of data.
  617. */
  618. if ((data_length > 1500) || (data_length <= 0)) {
  619. return -1;
  620. }
  621. /*
  622. * Check the number of vacant TxBDs.
  623. */
  624. if (fec->cleanTbdNum < 1) {
  625. #if (DEBUG & 0x20)
  626. printf("No available TxBDs ...\n");
  627. #endif
  628. return -1;
  629. }
  630. /*
  631. * Get the first TxBD to send the mac header
  632. */
  633. pTbd = &fec->tbdBase[fec->tbdIndex];
  634. pTbd->dataLength = data_length;
  635. pTbd->dataPointer = (uint32)eth_data;
  636. pTbd->status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY;
  637. fec->tbdIndex = (fec->tbdIndex + 1) % FEC_TBD_NUM;
  638. #if (DEBUG & 0x100)
  639. printf("SDMA_TASK_ENABLE, fec->tbdIndex = %d \n", fec->tbdIndex);
  640. #endif
  641. /*
  642. * Kick the MII i/f
  643. */
  644. if (fec->xcv_type != SEVENWIRE) {
  645. uint16 phyStatus;
  646. miiphy_read(dev->name, 0, 0x1, &phyStatus);
  647. }
  648. /*
  649. * Enable SmartDMA transmit task
  650. */
  651. #if (DEBUG & 0x20)
  652. tfifo_print(dev->name, fec);
  653. #endif
  654. SDMA_TASK_ENABLE (FEC_XMIT_TASK_NO);
  655. #if (DEBUG & 0x20)
  656. tfifo_print(dev->name, fec);
  657. #endif
  658. #if (DEBUG & 0x8)
  659. printf( "+" );
  660. #endif
  661. fec->cleanTbdNum -= 1;
  662. #if (DEBUG & 0x129) && (DEBUG & 0x80000000)
  663. printf ("smartDMA ethernet Tx task enabled\n");
  664. #endif
  665. /*
  666. * wait until frame is sent .
  667. */
  668. while (pTbd->status & FEC_TBD_READY) {
  669. udelay(10);
  670. #if (DEBUG & 0x8)
  671. printf ("TDB status = %04x\n", pTbd->status);
  672. #endif
  673. }
  674. return 0;
  675. }
  676. /********************************************************************/
  677. static int mpc5xxx_fec_recv(struct eth_device *dev)
  678. {
  679. /*
  680. * This command pulls one frame from the card
  681. */
  682. mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
  683. volatile FEC_RBD *pRbd = &fec->rbdBase[fec->rbdIndex];
  684. unsigned long ievent;
  685. int frame_length, len = 0;
  686. NBUF *frame;
  687. uchar buff[FEC_MAX_PKT_SIZE];
  688. #if (DEBUG & 0x1)
  689. printf ("mpc5xxx_fec_recv %d Start...\n", fec->rbdIndex);
  690. #endif
  691. #if (DEBUG & 0x8)
  692. printf( "-" );
  693. #endif
  694. /*
  695. * Check if any critical events have happened
  696. */
  697. ievent = fec->eth->ievent;
  698. fec->eth->ievent = ievent;
  699. if (ievent & 0x20060000) {
  700. /* BABT, Rx/Tx FIFO errors */
  701. mpc5xxx_fec_halt(dev);
  702. mpc5xxx_fec_init(dev, NULL);
  703. return 0;
  704. }
  705. if (ievent & 0x80000000) {
  706. /* Heartbeat error */
  707. fec->eth->x_cntrl |= 0x00000001;
  708. }
  709. if (ievent & 0x10000000) {
  710. /* Graceful stop complete */
  711. if (fec->eth->x_cntrl & 0x00000001) {
  712. mpc5xxx_fec_halt(dev);
  713. fec->eth->x_cntrl &= ~0x00000001;
  714. mpc5xxx_fec_init(dev, NULL);
  715. }
  716. }
  717. if (!(pRbd->status & FEC_RBD_EMPTY)) {
  718. if ((pRbd->status & FEC_RBD_LAST) && !(pRbd->status & FEC_RBD_ERR) &&
  719. ((pRbd->dataLength - 4) > 14)) {
  720. /*
  721. * Get buffer address and size
  722. */
  723. frame = (NBUF *)pRbd->dataPointer;
  724. frame_length = pRbd->dataLength - 4;
  725. #if (DEBUG & 0x20)
  726. {
  727. int i;
  728. printf("recv data hdr:");
  729. for (i = 0; i < 14; i++)
  730. printf("%x ", *(frame->head + i));
  731. printf("\n");
  732. }
  733. #endif
  734. /*
  735. * Fill the buffer and pass it to upper layers
  736. */
  737. memcpy(buff, frame->head, 14);
  738. memcpy(buff + 14, frame->data, frame_length);
  739. NetReceive(buff, frame_length);
  740. len = frame_length;
  741. }
  742. /*
  743. * Reset buffer descriptor as empty
  744. */
  745. mpc5xxx_fec_rbd_clean(fec, pRbd);
  746. }
  747. SDMA_CLEAR_IEVENT (FEC_RECV_TASK_NO);
  748. return len;
  749. }
  750. /********************************************************************/
  751. int mpc5xxx_fec_initialize(bd_t * bis)
  752. {
  753. mpc5xxx_fec_priv *fec;
  754. struct eth_device *dev;
  755. char *tmp, *end;
  756. char env_enetaddr[6];
  757. int i;
  758. fec = (mpc5xxx_fec_priv *)malloc(sizeof(*fec));
  759. dev = (struct eth_device *)malloc(sizeof(*dev));
  760. memset(dev, 0, sizeof *dev);
  761. fec->eth = (ethernet_regs *)MPC5XXX_FEC;
  762. fec->tbdBase = (FEC_TBD *)FEC_BD_BASE;
  763. fec->rbdBase = (FEC_RBD *)(FEC_BD_BASE + FEC_TBD_NUM * sizeof(FEC_TBD));
  764. #if defined(CONFIG_MPC5xxx_FEC_MII100)
  765. fec->xcv_type = MII100;
  766. #elif defined(CONFIG_MPC5xxx_FEC_MII10)
  767. fec->xcv_type = MII10;
  768. #elif defined(CONFIG_MPC5xxx_FEC_SEVENWIRE)
  769. fec->xcv_type = SEVENWIRE;
  770. #else
  771. #error fec->xcv_type not initialized.
  772. #endif
  773. if (fec->xcv_type != SEVENWIRE) {
  774. /*
  775. * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
  776. * and do not drop the Preamble.
  777. */
  778. fec->eth->mii_speed = (((gd->ipb_clk >> 20) / 5) << 1); /* No MII for 7-wire mode */
  779. }
  780. dev->priv = (void *)fec;
  781. dev->iobase = MPC5XXX_FEC;
  782. dev->init = mpc5xxx_fec_init;
  783. dev->halt = mpc5xxx_fec_halt;
  784. dev->send = mpc5xxx_fec_send;
  785. dev->recv = mpc5xxx_fec_recv;
  786. sprintf(dev->name, "FEC");
  787. eth_register(dev);
  788. #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
  789. miiphy_register (dev->name,
  790. fec5xxx_miiphy_read, fec5xxx_miiphy_write);
  791. #endif
  792. /*
  793. * Try to set the mac address now. The fec mac address is
  794. * a garbage after reset. When not using fec for booting
  795. * the Linux fec driver will try to work with this garbage.
  796. */
  797. tmp = getenv("ethaddr");
  798. if (tmp) {
  799. for (i=0; i<6; i++) {
  800. env_enetaddr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0;
  801. if (tmp)
  802. tmp = (*end) ? end+1 : end;
  803. }
  804. mpc5xxx_fec_set_hwaddr(fec, env_enetaddr);
  805. }
  806. return 1;
  807. }
  808. /* MII-interface related functions */
  809. /********************************************************************/
  810. int fec5xxx_miiphy_read(const char *devname, uint8 phyAddr, uint8 regAddr, uint16 * retVal)
  811. {
  812. ethernet_regs *eth = (ethernet_regs *)MPC5XXX_FEC;
  813. uint32 reg; /* convenient holder for the PHY register */
  814. uint32 phy; /* convenient holder for the PHY */
  815. int timeout = 0xffff;
  816. /*
  817. * reading from any PHY's register is done by properly
  818. * programming the FEC's MII data register.
  819. */
  820. reg = regAddr << FEC_MII_DATA_RA_SHIFT;
  821. phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
  822. eth->mii_data = (FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA | phy | reg);
  823. /*
  824. * wait for the related interrupt
  825. */
  826. while ((timeout--) && (!(eth->ievent & 0x00800000))) ;
  827. if (timeout == 0) {
  828. #if (DEBUG & 0x2)
  829. printf ("Read MDIO failed...\n");
  830. #endif
  831. return -1;
  832. }
  833. /*
  834. * clear mii interrupt bit
  835. */
  836. eth->ievent = 0x00800000;
  837. /*
  838. * it's now safe to read the PHY's register
  839. */
  840. *retVal = (uint16) eth->mii_data;
  841. return 0;
  842. }
  843. /********************************************************************/
  844. int fec5xxx_miiphy_write(const char *devname, uint8 phyAddr, uint8 regAddr, uint16 data)
  845. {
  846. ethernet_regs *eth = (ethernet_regs *)MPC5XXX_FEC;
  847. uint32 reg; /* convenient holder for the PHY register */
  848. uint32 phy; /* convenient holder for the PHY */
  849. int timeout = 0xffff;
  850. reg = regAddr << FEC_MII_DATA_RA_SHIFT;
  851. phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
  852. eth->mii_data = (FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR |
  853. FEC_MII_DATA_TA | phy | reg | data);
  854. /*
  855. * wait for the MII interrupt
  856. */
  857. while ((timeout--) && (!(eth->ievent & 0x00800000))) ;
  858. if (timeout == 0) {
  859. #if (DEBUG & 0x2)
  860. printf ("Write MDIO failed...\n");
  861. #endif
  862. return -1;
  863. }
  864. /*
  865. * clear MII interrupt bit
  866. */
  867. eth->ievent = 0x00800000;
  868. return 0;
  869. }