system.h 9.1 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348
  1. #ifndef __ASM_ARM_SYSTEM_H
  2. #define __ASM_ARM_SYSTEM_H
  3. #include <common.h>
  4. #include <linux/compiler.h>
  5. #ifdef CONFIG_ARM64
  6. /*
  7. * SCTLR_EL1/SCTLR_EL2/SCTLR_EL3 bits definitions
  8. */
  9. #define CR_M (1 << 0) /* MMU enable */
  10. #define CR_A (1 << 1) /* Alignment abort enable */
  11. #define CR_C (1 << 2) /* Dcache enable */
  12. #define CR_SA (1 << 3) /* Stack Alignment Check Enable */
  13. #define CR_I (1 << 12) /* Icache enable */
  14. #define CR_WXN (1 << 19) /* Write Permision Imply XN */
  15. #define CR_EE (1 << 25) /* Exception (Big) Endian */
  16. /* 2MB granularity */
  17. #define MMU_SECTION_SHIFT 21
  18. #define MMU_SECTION_SIZE (1 << MMU_SECTION_SHIFT)
  19. #ifndef __ASSEMBLY__
  20. #ifndef CONFIG_SYS_FULL_VA
  21. #define PGTABLE_SIZE (0x10000)
  22. #else
  23. u64 get_page_table_size(void);
  24. #define PGTABLE_SIZE get_page_table_size()
  25. #endif
  26. enum dcache_option {
  27. DCACHE_OFF = 0x3,
  28. };
  29. #define isb() \
  30. ({asm volatile( \
  31. "isb" : : : "memory"); \
  32. })
  33. #define wfi() \
  34. ({asm volatile( \
  35. "wfi" : : : "memory"); \
  36. })
  37. static inline unsigned int current_el(void)
  38. {
  39. unsigned int el;
  40. asm volatile("mrs %0, CurrentEL" : "=r" (el) : : "cc");
  41. return el >> 2;
  42. }
  43. static inline unsigned int get_sctlr(void)
  44. {
  45. unsigned int el, val;
  46. el = current_el();
  47. if (el == 1)
  48. asm volatile("mrs %0, sctlr_el1" : "=r" (val) : : "cc");
  49. else if (el == 2)
  50. asm volatile("mrs %0, sctlr_el2" : "=r" (val) : : "cc");
  51. else
  52. asm volatile("mrs %0, sctlr_el3" : "=r" (val) : : "cc");
  53. return val;
  54. }
  55. static inline void set_sctlr(unsigned int val)
  56. {
  57. unsigned int el;
  58. el = current_el();
  59. if (el == 1)
  60. asm volatile("msr sctlr_el1, %0" : : "r" (val) : "cc");
  61. else if (el == 2)
  62. asm volatile("msr sctlr_el2, %0" : : "r" (val) : "cc");
  63. else
  64. asm volatile("msr sctlr_el3, %0" : : "r" (val) : "cc");
  65. asm volatile("isb");
  66. }
  67. static inline unsigned long read_mpidr(void)
  68. {
  69. unsigned long val;
  70. asm volatile("mrs %0, mpidr_el1" : "=r" (val));
  71. return val;
  72. }
  73. #define BSP_COREID 0
  74. void __asm_flush_dcache_all(void);
  75. void __asm_invalidate_dcache_all(void);
  76. void __asm_flush_dcache_range(u64 start, u64 end);
  77. void __asm_invalidate_tlb_all(void);
  78. void __asm_invalidate_icache_all(void);
  79. int __asm_flush_l3_cache(void);
  80. void __asm_switch_ttbr(u64 new_ttbr);
  81. void armv8_switch_to_el2(void);
  82. void armv8_switch_to_el1(void);
  83. void gic_init(void);
  84. void gic_send_sgi(unsigned long sgino);
  85. void wait_for_wakeup(void);
  86. void protect_secure_region(void);
  87. void smp_kick_all_cpus(void);
  88. void flush_l3_cache(void);
  89. /*
  90. *Issue a hypervisor call in accordance with ARM "SMC Calling convention",
  91. * DEN0028A
  92. *
  93. * @args: input and output arguments
  94. *
  95. */
  96. void hvc_call(struct pt_regs *args);
  97. /*
  98. *Issue a secure monitor call in accordance with ARM "SMC Calling convention",
  99. * DEN0028A
  100. *
  101. * @args: input and output arguments
  102. *
  103. */
  104. void smc_call(struct pt_regs *args);
  105. #endif /* __ASSEMBLY__ */
  106. #else /* CONFIG_ARM64 */
  107. #ifdef __KERNEL__
  108. #define CPU_ARCH_UNKNOWN 0
  109. #define CPU_ARCH_ARMv3 1
  110. #define CPU_ARCH_ARMv4 2
  111. #define CPU_ARCH_ARMv4T 3
  112. #define CPU_ARCH_ARMv5 4
  113. #define CPU_ARCH_ARMv5T 5
  114. #define CPU_ARCH_ARMv5TE 6
  115. #define CPU_ARCH_ARMv5TEJ 7
  116. #define CPU_ARCH_ARMv6 8
  117. #define CPU_ARCH_ARMv7 9
  118. /*
  119. * CR1 bits (CP#15 CR1)
  120. */
  121. #define CR_M (1 << 0) /* MMU enable */
  122. #define CR_A (1 << 1) /* Alignment abort enable */
  123. #define CR_C (1 << 2) /* Dcache enable */
  124. #define CR_W (1 << 3) /* Write buffer enable */
  125. #define CR_P (1 << 4) /* 32-bit exception handler */
  126. #define CR_D (1 << 5) /* 32-bit data address range */
  127. #define CR_L (1 << 6) /* Implementation defined */
  128. #define CR_B (1 << 7) /* Big endian */
  129. #define CR_S (1 << 8) /* System MMU protection */
  130. #define CR_R (1 << 9) /* ROM MMU protection */
  131. #define CR_F (1 << 10) /* Implementation defined */
  132. #define CR_Z (1 << 11) /* Implementation defined */
  133. #define CR_I (1 << 12) /* Icache enable */
  134. #define CR_V (1 << 13) /* Vectors relocated to 0xffff0000 */
  135. #define CR_RR (1 << 14) /* Round Robin cache replacement */
  136. #define CR_L4 (1 << 15) /* LDR pc can set T bit */
  137. #define CR_DT (1 << 16)
  138. #define CR_IT (1 << 18)
  139. #define CR_ST (1 << 19)
  140. #define CR_FI (1 << 21) /* Fast interrupt (lower latency mode) */
  141. #define CR_U (1 << 22) /* Unaligned access operation */
  142. #define CR_XP (1 << 23) /* Extended page tables */
  143. #define CR_VE (1 << 24) /* Vectored interrupts */
  144. #define CR_EE (1 << 25) /* Exception (Big) Endian */
  145. #define CR_TRE (1 << 28) /* TEX remap enable */
  146. #define CR_AFE (1 << 29) /* Access flag enable */
  147. #define CR_TE (1 << 30) /* Thumb exception enable */
  148. #ifndef PGTABLE_SIZE
  149. #define PGTABLE_SIZE (4096 * 4)
  150. #endif
  151. /*
  152. * This is used to ensure the compiler did actually allocate the register we
  153. * asked it for some inline assembly sequences. Apparently we can't trust
  154. * the compiler from one version to another so a bit of paranoia won't hurt.
  155. * This string is meant to be concatenated with the inline asm string and
  156. * will cause compilation to stop on mismatch.
  157. * (for details, see gcc PR 15089)
  158. */
  159. #define __asmeq(x, y) ".ifnc " x "," y " ; .err ; .endif\n\t"
  160. #ifndef __ASSEMBLY__
  161. /**
  162. * save_boot_params() - Save boot parameters before starting reset sequence
  163. *
  164. * If you provide this function it will be called immediately U-Boot starts,
  165. * both for SPL and U-Boot proper.
  166. *
  167. * All registers are unchanged from U-Boot entry. No registers need be
  168. * preserved.
  169. *
  170. * This is not a normal C function. There is no stack. Return by branching to
  171. * save_boot_params_ret.
  172. *
  173. * void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3);
  174. */
  175. /**
  176. * save_boot_params_ret() - Return from save_boot_params()
  177. *
  178. * If you provide save_boot_params(), then you should jump back to this
  179. * function when done. Try to preserve all registers.
  180. *
  181. * If your implementation of save_boot_params() is in C then it is acceptable
  182. * to simply call save_boot_params_ret() at the end of your function. Since
  183. * there is no link register set up, you cannot just exit the function. U-Boot
  184. * will return to the (initialised) value of lr, and likely crash/hang.
  185. *
  186. * If your implementation of save_boot_params() is in assembler then you
  187. * should use 'b' or 'bx' to return to save_boot_params_ret.
  188. */
  189. void save_boot_params_ret(void);
  190. #define isb() __asm__ __volatile__ ("" : : : "memory")
  191. #define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");
  192. #ifdef __ARM_ARCH_7A__
  193. #define wfi() __asm__ __volatile__ ("wfi" : : : "memory")
  194. #else
  195. #define wfi()
  196. #endif
  197. static inline unsigned int get_cr(void)
  198. {
  199. unsigned int val;
  200. asm volatile("mrc p15, 0, %0, c1, c0, 0 @ get CR" : "=r" (val) : : "cc");
  201. return val;
  202. }
  203. static inline void set_cr(unsigned int val)
  204. {
  205. asm volatile("mcr p15, 0, %0, c1, c0, 0 @ set CR"
  206. : : "r" (val) : "cc");
  207. isb();
  208. }
  209. static inline unsigned int get_dacr(void)
  210. {
  211. unsigned int val;
  212. asm("mrc p15, 0, %0, c3, c0, 0 @ get DACR" : "=r" (val) : : "cc");
  213. return val;
  214. }
  215. static inline void set_dacr(unsigned int val)
  216. {
  217. asm volatile("mcr p15, 0, %0, c3, c0, 0 @ set DACR"
  218. : : "r" (val) : "cc");
  219. isb();
  220. }
  221. #ifdef CONFIG_CPU_V7
  222. /* Short-Descriptor Translation Table Level 1 Bits */
  223. #define TTB_SECT_NS_MASK (1 << 19)
  224. #define TTB_SECT_NG_MASK (1 << 17)
  225. #define TTB_SECT_S_MASK (1 << 16)
  226. /* Note: TTB AP bits are set elsewhere */
  227. #define TTB_SECT_TEX(x) ((x & 0x7) << 12)
  228. #define TTB_SECT_DOMAIN(x) ((x & 0xf) << 5)
  229. #define TTB_SECT_XN_MASK (1 << 4)
  230. #define TTB_SECT_C_MASK (1 << 3)
  231. #define TTB_SECT_B_MASK (1 << 2)
  232. #define TTB_SECT (2 << 0)
  233. /* options available for data cache on each page */
  234. enum dcache_option {
  235. DCACHE_OFF = TTB_SECT_DOMAIN(0) | TTB_SECT_XN_MASK | TTB_SECT,
  236. DCACHE_WRITETHROUGH = DCACHE_OFF | TTB_SECT_C_MASK,
  237. DCACHE_WRITEBACK = DCACHE_WRITETHROUGH | TTB_SECT_B_MASK,
  238. DCACHE_WRITEALLOC = DCACHE_WRITEBACK | TTB_SECT_TEX(1),
  239. };
  240. #else
  241. /* options available for data cache on each page */
  242. enum dcache_option {
  243. DCACHE_OFF = 0x12,
  244. DCACHE_WRITETHROUGH = 0x1a,
  245. DCACHE_WRITEBACK = 0x1e,
  246. DCACHE_WRITEALLOC = 0x16,
  247. };
  248. #endif
  249. /* Size of an MMU section */
  250. enum {
  251. MMU_SECTION_SHIFT = 20,
  252. MMU_SECTION_SIZE = 1 << MMU_SECTION_SHIFT,
  253. };
  254. #ifdef CONFIG_CPU_V7
  255. /* TTBR0 bits */
  256. #define TTBR0_BASE_ADDR_MASK 0xFFFFC000
  257. #define TTBR0_RGN_NC (0 << 3)
  258. #define TTBR0_RGN_WBWA (1 << 3)
  259. #define TTBR0_RGN_WT (2 << 3)
  260. #define TTBR0_RGN_WB (3 << 3)
  261. /* TTBR0[6] is IRGN[0] and TTBR[0] is IRGN[1] */
  262. #define TTBR0_IRGN_NC (0 << 0 | 0 << 6)
  263. #define TTBR0_IRGN_WBWA (0 << 0 | 1 << 6)
  264. #define TTBR0_IRGN_WT (1 << 0 | 0 << 6)
  265. #define TTBR0_IRGN_WB (1 << 0 | 1 << 6)
  266. #endif
  267. /**
  268. * Register an update to the page tables, and flush the TLB
  269. *
  270. * \param start start address of update in page table
  271. * \param stop stop address of update in page table
  272. */
  273. void mmu_page_table_flush(unsigned long start, unsigned long stop);
  274. #endif /* __ASSEMBLY__ */
  275. #define arch_align_stack(x) (x)
  276. #endif /* __KERNEL__ */
  277. #endif /* CONFIG_ARM64 */
  278. #ifndef __ASSEMBLY__
  279. /**
  280. * Change the cache settings for a region.
  281. *
  282. * \param start start address of memory region to change
  283. * \param size size of memory region to change
  284. * \param option dcache option to select
  285. */
  286. void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
  287. enum dcache_option option);
  288. #ifdef CONFIG_SYS_NONCACHED_MEMORY
  289. void noncached_init(void);
  290. phys_addr_t noncached_alloc(size_t size, size_t align);
  291. #endif /* CONFIG_SYS_NONCACHED_MEMORY */
  292. #endif /* __ASSEMBLY__ */
  293. #endif