ddr.c 2.0 KB

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  1. /*
  2. * Copyright 2009 Freescale Semiconductor, Inc.
  3. *
  4. * This program is free software; you can redistribute it and/or
  5. * modify it under the terms of the GNU General Public License
  6. * Version 2 as published by the Free Software Foundation.
  7. */
  8. #include <common.h>
  9. #include <i2c.h>
  10. #include <asm/fsl_ddr_sdram.h>
  11. #include <asm/fsl_ddr_dimm_params.h>
  12. static void
  13. get_spd(ddr3_spd_eeprom_t *spd, unsigned char i2c_address)
  14. {
  15. i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr3_spd_eeprom_t));
  16. }
  17. void fsl_ddr_get_spd(ddr3_spd_eeprom_t *ctrl_dimms_spd,
  18. unsigned int ctrl_num)
  19. {
  20. unsigned int i;
  21. unsigned int i2c_address = 0;
  22. for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
  23. if (ctrl_num == 0 && i == 0)
  24. i2c_address = SPD_EEPROM_ADDRESS1;
  25. if (ctrl_num == 0 && i == 1)
  26. i2c_address = SPD_EEPROM_ADDRESS2;
  27. get_spd(&(ctrl_dimms_spd[i]), i2c_address);
  28. }
  29. }
  30. void fsl_ddr_board_options(memctl_options_t *popts,
  31. dimm_params_t *pdimm,
  32. unsigned int ctrl_num)
  33. {
  34. /*
  35. * Factors to consider for clock adjust:
  36. * - number of chips on bus
  37. * - position of slot
  38. * - DDR1 vs. DDR2?
  39. * - ???
  40. *
  41. * This needs to be determined on a board-by-board basis.
  42. * 0110 3/4 cycle late
  43. * 0111 7/8 cycle late
  44. */
  45. popts->clk_adjust = 4;
  46. /*
  47. * Factors to consider for CPO:
  48. * - frequency
  49. * - ddr1 vs. ddr2
  50. */
  51. popts->cpo_override = 0xff;
  52. /*
  53. * Factors to consider for write data delay:
  54. * - number of DIMMs
  55. *
  56. * 1 = 1/4 clock delay
  57. * 2 = 1/2 clock delay
  58. * 3 = 3/4 clock delay
  59. * 4 = 1 clock delay
  60. * 5 = 5/4 clock delay
  61. * 6 = 3/2 clock delay
  62. */
  63. popts->write_data_delay = 2;
  64. /*
  65. * Enable half drive strength
  66. */
  67. popts->half_strength_driver_enable = 1;
  68. /* Write leveling override */
  69. popts->wrlvl_en = 1;
  70. popts->wrlvl_override = 1;
  71. popts->wrlvl_sample = 0xa;
  72. popts->wrlvl_start = 0x4;
  73. /* Rtt and Rtt_W override */
  74. popts->rtt_override = 1;
  75. popts->rtt_override_value = DDR3_RTT_60_OHM;
  76. popts->rtt_wr_override_value = 0; /* Rtt_WR= dynamic ODT off */
  77. }