config.h 2.3 KB

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  1. /*
  2. * Copyright 2009-2011 Freescale Semiconductor, Inc.
  3. *
  4. * This program is free software; you can redistribute it and/or
  5. * modify it under the terms of the GNU General Public License as
  6. * published by the Free Software Foundation; either version 2 of
  7. * the License, or (at your option) any later version.
  8. *
  9. * This program is distributed in the hope that it will be useful,
  10. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. * GNU General Public License for more details.
  13. *
  14. * You should have received a copy of the GNU General Public License
  15. * along with this program; if not, write to the Free Software
  16. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  17. * MA 02111-1307 USA
  18. *
  19. */
  20. #ifndef _ASM_CONFIG_H_
  21. #define _ASM_CONFIG_H_
  22. #ifdef CONFIG_MPC85xx
  23. #include <asm/config_mpc85xx.h>
  24. #endif
  25. #ifdef CONFIG_MPC86xx
  26. #include <asm/config_mpc86xx.h>
  27. #endif
  28. #define CONFIG_LMB
  29. #define CONFIG_SYS_BOOT_RAMDISK_HIGH
  30. #define CONFIG_SYS_BOOT_GET_CMDLINE
  31. #define CONFIG_SYS_BOOT_GET_KBD
  32. #ifndef CONFIG_MAX_MEM_MAPPED
  33. #if defined(CONFIG_4xx) || defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
  34. #define CONFIG_MAX_MEM_MAPPED ((phys_size_t)2 << 30)
  35. #else
  36. #define CONFIG_MAX_MEM_MAPPED (256 << 20)
  37. #endif
  38. #endif
  39. /* Check if boards need to enable FSL DMA engine for SDRAM init */
  40. #if !defined(CONFIG_FSL_DMA) && defined(CONFIG_DDR_ECC)
  41. #if (defined(CONFIG_MPC83xx) && defined(CONFIG_DDR_ECC_INIT_VIA_DMA)) || \
  42. ((defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)) && \
  43. !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER))
  44. #define CONFIG_FSL_DMA
  45. #endif
  46. #endif
  47. #ifndef CONFIG_MAX_CPUS
  48. #define CONFIG_MAX_CPUS 1
  49. #endif
  50. /*
  51. * Provide a default boot page translation virtual address that lines up with
  52. * Freescale's default e500 reset page.
  53. */
  54. #if (defined(CONFIG_E500) && defined(CONFIG_MP))
  55. #ifndef CONFIG_BPTR_VIRT_ADDR
  56. #define CONFIG_BPTR_VIRT_ADDR 0xfffff000
  57. #endif
  58. #endif
  59. /*
  60. * SEC (crypto unit) major compatible version determination
  61. */
  62. #if defined(CONFIG_MPC83xx)
  63. #define CONFIG_SYS_FSL_SEC_COMPAT 2
  64. #endif
  65. /* Since so many PPC SOCs have a semi-common LBC, define this here */
  66. #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) || \
  67. defined(CONFIG_MPC83xx)
  68. #define CONFIG_FSL_LBC
  69. #endif
  70. /* All PPC boards must swap IDE bytes */
  71. #define CONFIG_IDE_SWAP_IO
  72. #endif /* _ASM_CONFIG_H_ */