sdram_arria10.c 21 KB

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  1. /*
  2. * Copyright (C) 2017 Intel Corporation <www.intel.com>
  3. *
  4. * SPDX-License-Identifier: GPL-2.0
  5. */
  6. #include <common.h>
  7. #include <errno.h>
  8. #include <fdtdec.h>
  9. #include <malloc.h>
  10. #include <wait_bit.h>
  11. #include <watchdog.h>
  12. #include <asm/io.h>
  13. #include <asm/arch/fpga_manager.h>
  14. #include <asm/arch/misc.h>
  15. #include <asm/arch/reset_manager.h>
  16. #include <asm/arch/sdram.h>
  17. #include <linux/kernel.h>
  18. DECLARE_GLOBAL_DATA_PTR;
  19. static void sdram_mmr_init(void);
  20. static u64 sdram_size_calc(void);
  21. /* FAWBANK - Number of Bank of a given device involved in the FAW period. */
  22. #define ARRIA10_SDR_ACTIVATE_FAWBANK (0x1)
  23. #define ARRIA_DDR_CONFIG(A, B, C, R) \
  24. (((A) << 24) | ((B) << 16) | ((C) << 8) | (R))
  25. #define DDR_CONFIG_ELEMENTS ARRAY_SIZE(ddr_config)
  26. #define DDR_REG_SEQ2CORE 0xFFD0507C
  27. #define DDR_REG_CORE2SEQ 0xFFD05078
  28. #define DDR_READ_LATENCY_DELAY 40
  29. #define DDR_SIZE_2GB_HEX 0x80000000
  30. #define DDR_MAX_TRIES 0x00100000
  31. #define IO48_MMR_DRAMSTS 0xFFCFA0EC
  32. #define IO48_MMR_NIOS2_RESERVE0 0xFFCFA110
  33. #define IO48_MMR_NIOS2_RESERVE1 0xFFCFA114
  34. #define IO48_MMR_NIOS2_RESERVE2 0xFFCFA118
  35. #define SEQ2CORE_MASK 0xF
  36. #define CORE2SEQ_INT_REQ 0xF
  37. #define SEQ2CORE_INT_RESP_BIT 3
  38. static const struct socfpga_ecc_hmc *socfpga_ecc_hmc_base =
  39. (void *)SOCFPGA_SDR_ADDRESS;
  40. static const struct socfpga_noc_ddr_scheduler *socfpga_noc_ddr_scheduler_base =
  41. (void *)SOCFPGA_SDR_SCHEDULER_ADDRESS;
  42. static const struct socfpga_noc_fw_ddr_mpu_fpga2sdram
  43. *socfpga_noc_fw_ddr_mpu_fpga2sdram_base =
  44. (void *)SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS;
  45. static const struct socfpga_noc_fw_ddr_l3 *socfpga_noc_fw_ddr_l3_base =
  46. (void *)SOCFPGA_SDR_FIREWALL_L3_ADDRESS;
  47. static const struct socfpga_io48_mmr *socfpga_io48_mmr_base =
  48. (void *)SOCFPGA_HMC_MMR_IO48_ADDRESS;
  49. /* The following are the supported configurations */
  50. static u32 ddr_config[] = {
  51. /* Chip - Row - Bank - Column Style */
  52. /* All Types */
  53. ARRIA_DDR_CONFIG(0, 3, 10, 12),
  54. ARRIA_DDR_CONFIG(0, 3, 10, 13),
  55. ARRIA_DDR_CONFIG(0, 3, 10, 14),
  56. ARRIA_DDR_CONFIG(0, 3, 10, 15),
  57. ARRIA_DDR_CONFIG(0, 3, 10, 16),
  58. ARRIA_DDR_CONFIG(0, 3, 10, 17),
  59. /* LPDDR x16 */
  60. ARRIA_DDR_CONFIG(0, 3, 11, 14),
  61. ARRIA_DDR_CONFIG(0, 3, 11, 15),
  62. ARRIA_DDR_CONFIG(0, 3, 11, 16),
  63. ARRIA_DDR_CONFIG(0, 3, 12, 15),
  64. /* DDR4 Only */
  65. ARRIA_DDR_CONFIG(0, 4, 10, 14),
  66. ARRIA_DDR_CONFIG(0, 4, 10, 15),
  67. ARRIA_DDR_CONFIG(0, 4, 10, 16),
  68. ARRIA_DDR_CONFIG(0, 4, 10, 17), /* 14 */
  69. /* Chip - Bank - Row - Column Style */
  70. ARRIA_DDR_CONFIG(1, 3, 10, 12),
  71. ARRIA_DDR_CONFIG(1, 3, 10, 13),
  72. ARRIA_DDR_CONFIG(1, 3, 10, 14),
  73. ARRIA_DDR_CONFIG(1, 3, 10, 15),
  74. ARRIA_DDR_CONFIG(1, 3, 10, 16),
  75. ARRIA_DDR_CONFIG(1, 3, 10, 17),
  76. ARRIA_DDR_CONFIG(1, 3, 11, 14),
  77. ARRIA_DDR_CONFIG(1, 3, 11, 15),
  78. ARRIA_DDR_CONFIG(1, 3, 11, 16),
  79. ARRIA_DDR_CONFIG(1, 3, 12, 15),
  80. /* DDR4 Only */
  81. ARRIA_DDR_CONFIG(1, 4, 10, 14),
  82. ARRIA_DDR_CONFIG(1, 4, 10, 15),
  83. ARRIA_DDR_CONFIG(1, 4, 10, 16),
  84. ARRIA_DDR_CONFIG(1, 4, 10, 17),
  85. };
  86. static int match_ddr_conf(u32 ddr_conf)
  87. {
  88. int i;
  89. for (i = 0; i < DDR_CONFIG_ELEMENTS; i++) {
  90. if (ddr_conf == ddr_config[i])
  91. return i;
  92. }
  93. return 0;
  94. }
  95. /* Check whether SDRAM is successfully Calibrated */
  96. static int is_sdram_cal_success(void)
  97. {
  98. return readl(&socfpga_ecc_hmc_base->ddrcalstat);
  99. }
  100. static unsigned char ddr_get_bit(u32 ereg, unsigned char bit)
  101. {
  102. u32 reg = readl(ereg);
  103. return (reg & BIT(bit)) ? 1 : 0;
  104. }
  105. static unsigned char ddr_wait_bit(u32 ereg, u32 bit,
  106. u32 expected, u32 timeout_usec)
  107. {
  108. u32 tmr;
  109. for (tmr = 0; tmr < timeout_usec; tmr += 100) {
  110. udelay(100);
  111. WATCHDOG_RESET();
  112. if (ddr_get_bit(ereg, bit) == expected)
  113. return 0;
  114. }
  115. return 1;
  116. }
  117. static int emif_clear(void)
  118. {
  119. u32 i = DDR_MAX_TRIES;
  120. u8 ret = 0;
  121. writel(0, DDR_REG_CORE2SEQ);
  122. do {
  123. ret = !wait_for_bit_le32((u32 *)DDR_REG_SEQ2CORE,
  124. SEQ2CORE_MASK, 1, 50, 0);
  125. } while (ret && (--i > 0));
  126. return !i;
  127. }
  128. static int emif_reset(void)
  129. {
  130. u32 c2s, s2c;
  131. c2s = readl(DDR_REG_CORE2SEQ);
  132. s2c = readl(DDR_REG_SEQ2CORE);
  133. debug("c2s=%08x s2c=%08x nr0=%08x nr1=%08x nr2=%08x dst=%08x\n",
  134. c2s, s2c, readl(IO48_MMR_NIOS2_RESERVE0),
  135. readl(IO48_MMR_NIOS2_RESERVE1),
  136. readl(IO48_MMR_NIOS2_RESERVE2),
  137. readl(IO48_MMR_DRAMSTS));
  138. if ((s2c & SEQ2CORE_MASK) && emif_clear()) {
  139. debug("failed emif_clear()\n");
  140. return -EPERM;
  141. }
  142. writel(CORE2SEQ_INT_REQ, DDR_REG_CORE2SEQ);
  143. if (ddr_wait_bit(DDR_REG_SEQ2CORE, SEQ2CORE_INT_RESP_BIT, 0, 1000000)) {
  144. debug("emif_reset failed to see interrupt acknowledge\n");
  145. return -EPERM;
  146. } else {
  147. debug("emif_reset interrupt acknowledged\n");
  148. }
  149. if (emif_clear()) {
  150. debug("emif_clear() failed\n");
  151. return -EPERM;
  152. }
  153. debug("emif_reset interrupt cleared\n");
  154. debug("nr0=%08x nr1=%08x nr2=%08x\n",
  155. readl(IO48_MMR_NIOS2_RESERVE0),
  156. readl(IO48_MMR_NIOS2_RESERVE1),
  157. readl(IO48_MMR_NIOS2_RESERVE2));
  158. return 0;
  159. }
  160. static int ddr_setup(void)
  161. {
  162. int i, j, ddr_setup_complete = 0;
  163. /* Try 3 times to do a calibration */
  164. for (i = 0; (i < 3) && !ddr_setup_complete; i++) {
  165. WATCHDOG_RESET();
  166. /* A delay to wait for calibration bit to set */
  167. for (j = 0; (j < 10) && !ddr_setup_complete; j++) {
  168. mdelay(500);
  169. ddr_setup_complete = is_sdram_cal_success();
  170. }
  171. if (!ddr_setup_complete)
  172. if (emif_reset())
  173. puts("Error: Failed to reset EMIF\n");
  174. }
  175. /* After 3 times trying calibration */
  176. if (!ddr_setup_complete) {
  177. puts("Error: Could Not Calibrate SDRAM\n");
  178. return -EPERM;
  179. }
  180. return 0;
  181. }
  182. /* Function to startup the SDRAM*/
  183. static int sdram_startup(void)
  184. {
  185. /* Release NOC ddr scheduler from reset */
  186. socfpga_reset_deassert_noc_ddr_scheduler();
  187. /* Bringup the DDR (calibration and configuration) */
  188. return ddr_setup();
  189. }
  190. static u64 sdram_size_calc(void)
  191. {
  192. u32 dramaddrw = readl(&socfpga_io48_mmr_base->dramaddrw);
  193. u64 size = BIT(((dramaddrw &
  194. IO48_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH_MASK) >>
  195. IO48_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH_SHIFT) +
  196. ((dramaddrw &
  197. IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_MASK) >>
  198. IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_SHIFT) +
  199. ((dramaddrw &
  200. IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_MASK) >>
  201. IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_SHIFT) +
  202. ((dramaddrw &
  203. IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_MASK) >>
  204. IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_SHIFT) +
  205. (dramaddrw & IO48_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH_MASK));
  206. size *= (2 << (readl(&socfpga_ecc_hmc_base->ddrioctrl) &
  207. ALT_ECC_HMC_OCP_DDRIOCTRL_IO_SIZE_MSK));
  208. debug("SDRAM size=%llu", size);
  209. return size;
  210. }
  211. /* Function to initialize SDRAM MMR and NOC DDR scheduler*/
  212. static void sdram_mmr_init(void)
  213. {
  214. u32 update_value, io48_value;
  215. u32 ctrlcfg0 = readl(&socfpga_io48_mmr_base->ctrlcfg0);
  216. u32 ctrlcfg1 = readl(&socfpga_io48_mmr_base->ctrlcfg1);
  217. u32 dramaddrw = readl(&socfpga_io48_mmr_base->dramaddrw);
  218. u32 caltim0 = readl(&socfpga_io48_mmr_base->caltiming0);
  219. u32 caltim1 = readl(&socfpga_io48_mmr_base->caltiming1);
  220. u32 caltim2 = readl(&socfpga_io48_mmr_base->caltiming2);
  221. u32 caltim3 = readl(&socfpga_io48_mmr_base->caltiming3);
  222. u32 caltim4 = readl(&socfpga_io48_mmr_base->caltiming4);
  223. u32 caltim9 = readl(&socfpga_io48_mmr_base->caltiming9);
  224. u32 ddrioctl;
  225. /*
  226. * Configure the DDR IO size [0xFFCFB008]
  227. * niosreserve0: Used to indicate DDR width &
  228. * bit[7:0] = Number of data bits (0x20 for 32bit)
  229. * bit[8] = 1 if user-mode OCT is present
  230. * bit[9] = 1 if warm reset compiled into EMIF Cal Code
  231. * bit[10] = 1 if warm reset is on during generation in EMIF Cal
  232. * niosreserve1: IP ADCDS version encoded as 16 bit value
  233. * bit[2:0] = Variant (0=not special,1=FAE beta, 2=Customer beta,
  234. * 3=EAP, 4-6 are reserved)
  235. * bit[5:3] = Service Pack # (e.g. 1)
  236. * bit[9:6] = Minor Release #
  237. * bit[14:10] = Major Release #
  238. */
  239. if ((socfpga_io48_mmr_base->niosreserve1 >> 6) & 0x1FF) {
  240. update_value = readl(&socfpga_io48_mmr_base->niosreserve0);
  241. writel(((update_value & 0xFF) >> 5),
  242. &socfpga_ecc_hmc_base->ddrioctrl);
  243. }
  244. ddrioctl = readl(&socfpga_ecc_hmc_base->ddrioctrl);
  245. /* Set the DDR Configuration [0xFFD12400] */
  246. io48_value = ARRIA_DDR_CONFIG(
  247. ((ctrlcfg1 &
  248. IO48_MMR_CTRLCFG1_ADDR_ORDER_MASK) >>
  249. IO48_MMR_CTRLCFG1_ADDR_ORDER_SHIFT),
  250. ((dramaddrw &
  251. IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_MASK) >>
  252. IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_SHIFT) +
  253. ((dramaddrw &
  254. IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_MASK) >>
  255. IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_SHIFT),
  256. (dramaddrw &
  257. IO48_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH_MASK),
  258. ((dramaddrw &
  259. IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_MASK) >>
  260. IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_SHIFT));
  261. update_value = match_ddr_conf(io48_value);
  262. if (update_value)
  263. writel(update_value,
  264. &socfpga_noc_ddr_scheduler_base->ddr_t_main_scheduler_ddrconf);
  265. /*
  266. * Configure DDR timing [0xFFD1240C]
  267. * RDTOMISS = tRTP + tRP + tRCD - BL/2
  268. * WRTOMISS = WL + tWR + tRP + tRCD and
  269. * WL = RL + BL/2 + 2 - rd-to-wr ; tWR = 15ns so...
  270. * First part of equation is in memory clock units so divide by 2
  271. * for HMC clock units. 1066MHz is close to 1ns so use 15 directly.
  272. * WRTOMISS = ((RL + BL/2 + 2 + tWR) >> 1)- rd-to-wr + tRP + tRCD
  273. */
  274. u32 ctrlcfg0_cfg_ctrl_burst_len =
  275. (ctrlcfg0 & IO48_MMR_CTRLCFG0_CTRL_BURST_LENGTH_MASK) >>
  276. IO48_MMR_CTRLCFG0_CTRL_BURST_LENGTH_SHIFT;
  277. u32 caltim0_cfg_act_to_rdwr = caltim0 &
  278. IO48_MMR_CALTIMING0_CFG_ACT_TO_RDWR_MASK;
  279. u32 caltim0_cfg_act_to_act =
  280. (caltim0 & IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_MASK) >>
  281. IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_SHIFT;
  282. u32 caltim0_cfg_act_to_act_db =
  283. (caltim0 &
  284. IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_DIFF_BANK_MASK) >>
  285. IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_DIFF_BANK_SHIFT;
  286. u32 caltim1_cfg_rd_to_wr =
  287. (caltim1 & IO48_MMR_CALTIMING1_CFG_RD_TO_WR_MASK) >>
  288. IO48_MMR_CALTIMING1_CFG_RD_TO_WR_SHIFT;
  289. u32 caltim1_cfg_rd_to_rd_dc =
  290. (caltim1 & IO48_MMR_CALTIMING1_CFG_RD_TO_RD_DC_MASK) >>
  291. IO48_MMR_CALTIMING1_CFG_RD_TO_RD_DC_SHIFT;
  292. u32 caltim1_cfg_rd_to_wr_dc =
  293. (caltim1 & IO48_MMR_CALTIMING1_CFG_RD_TO_WR_DIFF_CHIP_MASK) >>
  294. IO48_MMR_CALTIMING1_CFG_RD_TO_WR_DIFF_CHIP_SHIFT;
  295. u32 caltim2_cfg_rd_to_pch =
  296. (caltim2 & IO48_MMR_CALTIMING2_CFG_RD_TO_PCH_MASK) >>
  297. IO48_MMR_CALTIMING2_CFG_RD_TO_PCH_SHIFT;
  298. u32 caltim3_cfg_wr_to_rd =
  299. (caltim3 & IO48_MMR_CALTIMING3_CFG_WR_TO_RD_MASK) >>
  300. IO48_MMR_CALTIMING3_CFG_WR_TO_RD_SHIFT;
  301. u32 caltim3_cfg_wr_to_rd_dc =
  302. (caltim3 & IO48_MMR_CALTIMING3_CFG_WR_TO_RD_DIFF_CHIP_MASK) >>
  303. IO48_MMR_CALTIMING3_CFG_WR_TO_RD_DIFF_CHIP_SHIFT;
  304. u32 caltim4_cfg_pch_to_valid =
  305. (caltim4 & IO48_MMR_CALTIMING4_CFG_PCH_TO_VALID_MASK) >>
  306. IO48_MMR_CALTIMING4_CFG_PCH_TO_VALID_SHIFT;
  307. u32 caltim9_cfg_4_act_to_act = caltim9 &
  308. IO48_MMR_CALTIMING9_CFG_WR_4_ACT_TO_ACT_MASK;
  309. update_value = (caltim2_cfg_rd_to_pch + caltim4_cfg_pch_to_valid +
  310. caltim0_cfg_act_to_rdwr -
  311. (ctrlcfg0_cfg_ctrl_burst_len >> 2));
  312. io48_value = ((((socfpga_io48_mmr_base->dramtiming0 &
  313. ALT_IO48_DRAMTIME_MEM_READ_LATENCY_MASK) + 2 + 15 +
  314. (ctrlcfg0_cfg_ctrl_burst_len >> 1)) >> 1) -
  315. /* Up to here was in memory cycles so divide by 2 */
  316. caltim1_cfg_rd_to_wr + caltim0_cfg_act_to_rdwr +
  317. caltim4_cfg_pch_to_valid);
  318. writel(((caltim0_cfg_act_to_act <<
  319. ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_ACTTOACT_LSB) |
  320. (update_value <<
  321. ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOMISS_LSB) |
  322. (io48_value <<
  323. ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTOMISS_LSB) |
  324. ((ctrlcfg0_cfg_ctrl_burst_len >> 2) <<
  325. ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BURSTLEN_LSB) |
  326. (caltim1_cfg_rd_to_wr <<
  327. ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOWR_LSB) |
  328. (caltim3_cfg_wr_to_rd <<
  329. ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTORD_LSB) |
  330. (((ddrioctl == 1) ? 1 : 0) <<
  331. ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BWRATIO_LSB)),
  332. &socfpga_noc_ddr_scheduler_base->
  333. ddr_t_main_scheduler_ddrtiming);
  334. /* Configure DDR mode [0xFFD12410] [precharge = 0] */
  335. writel(((ddrioctl ? 0 : 1) <<
  336. ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_BWRATIOEXTENDED_LSB),
  337. &socfpga_noc_ddr_scheduler_base->ddr_t_main_scheduler_ddrmode);
  338. /* Configure the read latency [0xFFD12414] */
  339. writel(((socfpga_io48_mmr_base->dramtiming0 &
  340. ALT_IO48_DRAMTIME_MEM_READ_LATENCY_MASK) >> 1) +
  341. DDR_READ_LATENCY_DELAY,
  342. &socfpga_noc_ddr_scheduler_base->
  343. ddr_t_main_scheduler_readlatency);
  344. /*
  345. * Configuring timing values concerning activate commands
  346. * [0xFFD12438] [FAWBANK alway 1 because always 4 bank DDR]
  347. */
  348. writel(((caltim0_cfg_act_to_act_db <<
  349. ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_RRD_LSB) |
  350. (caltim9_cfg_4_act_to_act <<
  351. ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAW_LSB) |
  352. (ARRIA10_SDR_ACTIVATE_FAWBANK <<
  353. ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAWBANK_LSB)),
  354. &socfpga_noc_ddr_scheduler_base->ddr_t_main_scheduler_activate);
  355. /*
  356. * Configuring timing values concerning device to device data bus
  357. * ownership change [0xFFD1243C]
  358. */
  359. writel(((caltim1_cfg_rd_to_rd_dc <<
  360. ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTORD_LSB) |
  361. (caltim1_cfg_rd_to_wr_dc <<
  362. ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTOWR_LSB) |
  363. (caltim3_cfg_wr_to_rd_dc <<
  364. ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSWRTORD_LSB)),
  365. &socfpga_noc_ddr_scheduler_base->ddr_t_main_scheduler_devtodev);
  366. /* Enable or disable the SDRAM ECC */
  367. if (ctrlcfg1 & IO48_MMR_CTRLCFG1_CTRL_ENABLE_ECC) {
  368. setbits_le32(&socfpga_ecc_hmc_base->eccctrl,
  369. (ALT_ECC_HMC_OCP_ECCCTL_AWB_CNT_RST_SET_MSK |
  370. ALT_ECC_HMC_OCP_ECCCTL_CNT_RST_SET_MSK |
  371. ALT_ECC_HMC_OCP_ECCCTL_ECC_EN_SET_MSK));
  372. clrbits_le32(&socfpga_ecc_hmc_base->eccctrl,
  373. (ALT_ECC_HMC_OCP_ECCCTL_AWB_CNT_RST_SET_MSK |
  374. ALT_ECC_HMC_OCP_ECCCTL_CNT_RST_SET_MSK));
  375. setbits_le32(&socfpga_ecc_hmc_base->eccctrl2,
  376. (ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN_SET_MSK |
  377. ALT_ECC_HMC_OCP_ECCCTL2_AWB_EN_SET_MSK));
  378. } else {
  379. clrbits_le32(&socfpga_ecc_hmc_base->eccctrl,
  380. (ALT_ECC_HMC_OCP_ECCCTL_AWB_CNT_RST_SET_MSK |
  381. ALT_ECC_HMC_OCP_ECCCTL_CNT_RST_SET_MSK |
  382. ALT_ECC_HMC_OCP_ECCCTL_ECC_EN_SET_MSK));
  383. clrbits_le32(&socfpga_ecc_hmc_base->eccctrl2,
  384. (ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN_SET_MSK |
  385. ALT_ECC_HMC_OCP_ECCCTL2_AWB_EN_SET_MSK));
  386. }
  387. }
  388. struct firewall_entry {
  389. const char *prop_name;
  390. const u32 cfg_addr;
  391. const u32 en_addr;
  392. const u32 en_bit;
  393. };
  394. #define FW_MPU_FPGA_ADDRESS \
  395. ((const struct socfpga_noc_fw_ddr_mpu_fpga2sdram *)\
  396. SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS)
  397. #define SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(ADDR) \
  398. (SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS + \
  399. offsetof(struct socfpga_noc_fw_ddr_mpu_fpga2sdram, ADDR))
  400. #define SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(ADDR) \
  401. (SOCFPGA_SDR_FIREWALL_L3_ADDRESS + \
  402. offsetof(struct socfpga_noc_fw_ddr_l3, ADDR))
  403. const struct firewall_entry firewall_table[] = {
  404. {
  405. "mpu0",
  406. SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(mpuregion0addr),
  407. SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
  408. ALT_NOC_FW_DDR_SCR_EN_MPUREG0EN_SET_MSK
  409. },
  410. {
  411. "mpu1",
  412. SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS +
  413. SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(mpuregion1addr),
  414. SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
  415. ALT_NOC_FW_DDR_SCR_EN_MPUREG1EN_SET_MSK
  416. },
  417. {
  418. "mpu2",
  419. SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(mpuregion2addr),
  420. SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
  421. ALT_NOC_FW_DDR_SCR_EN_MPUREG2EN_SET_MSK
  422. },
  423. {
  424. "mpu3",
  425. SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(mpuregion3addr),
  426. SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
  427. ALT_NOC_FW_DDR_SCR_EN_MPUREG3EN_SET_MSK
  428. },
  429. {
  430. "l3-0",
  431. SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion0addr),
  432. SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
  433. ALT_NOC_FW_DDR_SCR_EN_HPSREG0EN_SET_MSK
  434. },
  435. {
  436. "l3-1",
  437. SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion1addr),
  438. SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
  439. ALT_NOC_FW_DDR_SCR_EN_HPSREG1EN_SET_MSK
  440. },
  441. {
  442. "l3-2",
  443. SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion2addr),
  444. SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
  445. ALT_NOC_FW_DDR_SCR_EN_HPSREG2EN_SET_MSK
  446. },
  447. {
  448. "l3-3",
  449. SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion3addr),
  450. SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
  451. ALT_NOC_FW_DDR_SCR_EN_HPSREG3EN_SET_MSK
  452. },
  453. {
  454. "l3-4",
  455. SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion4addr),
  456. SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
  457. ALT_NOC_FW_DDR_SCR_EN_HPSREG4EN_SET_MSK
  458. },
  459. {
  460. "l3-5",
  461. SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion5addr),
  462. SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
  463. ALT_NOC_FW_DDR_SCR_EN_HPSREG5EN_SET_MSK
  464. },
  465. {
  466. "l3-6",
  467. SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion6addr),
  468. SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
  469. ALT_NOC_FW_DDR_SCR_EN_HPSREG6EN_SET_MSK
  470. },
  471. {
  472. "l3-7",
  473. SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion7addr),
  474. SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
  475. ALT_NOC_FW_DDR_SCR_EN_HPSREG7EN_SET_MSK
  476. },
  477. {
  478. "fpga2sdram0-0",
  479. SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
  480. (fpga2sdram0region0addr),
  481. SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
  482. ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG0EN_SET_MSK
  483. },
  484. {
  485. "fpga2sdram0-1",
  486. SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
  487. (fpga2sdram0region1addr),
  488. SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
  489. ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG1EN_SET_MSK
  490. },
  491. {
  492. "fpga2sdram0-2",
  493. SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
  494. (fpga2sdram0region2addr),
  495. SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
  496. ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG2EN_SET_MSK
  497. },
  498. {
  499. "fpga2sdram0-3",
  500. SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
  501. (fpga2sdram0region3addr),
  502. SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
  503. ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG3EN_SET_MSK
  504. },
  505. {
  506. "fpga2sdram1-0",
  507. SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
  508. (fpga2sdram1region0addr),
  509. SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
  510. ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG0EN_SET_MSK
  511. },
  512. {
  513. "fpga2sdram1-1",
  514. SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
  515. (fpga2sdram1region1addr),
  516. SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
  517. ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG1EN_SET_MSK
  518. },
  519. {
  520. "fpga2sdram1-2",
  521. SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
  522. (fpga2sdram1region2addr),
  523. SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
  524. ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG2EN_SET_MSK
  525. },
  526. {
  527. "fpga2sdram1-3",
  528. SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
  529. (fpga2sdram1region3addr),
  530. SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
  531. ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG3EN_SET_MSK
  532. },
  533. {
  534. "fpga2sdram2-0",
  535. SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
  536. (fpga2sdram2region0addr),
  537. SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
  538. ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG0EN_SET_MSK
  539. },
  540. {
  541. "fpga2sdram2-1",
  542. SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
  543. (fpga2sdram2region1addr),
  544. SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
  545. ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG1EN_SET_MSK
  546. },
  547. {
  548. "fpga2sdram2-2",
  549. SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
  550. (fpga2sdram2region2addr),
  551. SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
  552. ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG2EN_SET_MSK
  553. },
  554. {
  555. "fpga2sdram2-3",
  556. SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
  557. (fpga2sdram2region3addr),
  558. SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
  559. ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG3EN_SET_MSK
  560. },
  561. };
  562. static int of_sdram_firewall_setup(const void *blob)
  563. {
  564. int child, i, node, ret;
  565. u32 start_end[2];
  566. char name[32];
  567. node = fdtdec_next_compatible(blob, 0, COMPAT_ALTERA_SOCFPGA_NOC);
  568. if (node < 0)
  569. return -ENXIO;
  570. child = fdt_first_subnode(blob, node);
  571. if (child < 0)
  572. return -ENXIO;
  573. /* set to default state */
  574. writel(0, &socfpga_noc_fw_ddr_mpu_fpga2sdram_base->enable);
  575. writel(0, &socfpga_noc_fw_ddr_l3_base->enable);
  576. for (i = 0; i < ARRAY_SIZE(firewall_table); i++) {
  577. sprintf(name, "%s", firewall_table[i].prop_name);
  578. ret = fdtdec_get_int_array(blob, child, name,
  579. start_end, 2);
  580. if (ret) {
  581. sprintf(name, "altr,%s", firewall_table[i].prop_name);
  582. ret = fdtdec_get_int_array(blob, child, name,
  583. start_end, 2);
  584. if (ret)
  585. continue;
  586. }
  587. writel((start_end[0] & ALT_NOC_FW_DDR_ADDR_MASK) |
  588. (start_end[1] << ALT_NOC_FW_DDR_END_ADDR_LSB),
  589. firewall_table[i].cfg_addr);
  590. setbits_le32(firewall_table[i].en_addr,
  591. firewall_table[i].en_bit);
  592. }
  593. return 0;
  594. }
  595. int ddr_calibration_sequence(void)
  596. {
  597. WATCHDOG_RESET();
  598. /* Check to see if SDRAM cal was success */
  599. if (sdram_startup()) {
  600. puts("DDRCAL: Failed\n");
  601. return -EPERM;
  602. }
  603. puts("DDRCAL: Success\n");
  604. WATCHDOG_RESET();
  605. /* initialize the MMR register */
  606. sdram_mmr_init();
  607. /* assigning the SDRAM size */
  608. u64 size = sdram_size_calc();
  609. /*
  610. * If size is less than zero, this is invalid/weird value from
  611. * calculation, use default Config size.
  612. * Up to 2GB is supported, 2GB would be used if more than that.
  613. */
  614. if (size <= 0)
  615. gd->ram_size = PHYS_SDRAM_1_SIZE;
  616. else if (DDR_SIZE_2GB_HEX <= size)
  617. gd->ram_size = DDR_SIZE_2GB_HEX;
  618. else
  619. gd->ram_size = (u32)size;
  620. /* setup the dram info within bd */
  621. dram_init_banksize();
  622. if (of_sdram_firewall_setup(gd->fdt_blob))
  623. puts("FW: Error Configuring Firewall\n");
  624. return 0;
  625. }
  626. void dram_bank_mmu_setup(int bank)
  627. {
  628. bd_t *bd = gd->bd;
  629. int i;
  630. debug("%s: bank: %d\n", __func__, bank);
  631. for (i = bd->bi_dram[bank].start >> 20;
  632. i < (bd->bi_dram[bank].start + bd->bi_dram[bank].size) >> 20;
  633. i++) {
  634. #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
  635. set_section_dcache(i, DCACHE_WRITETHROUGH);
  636. #else
  637. set_section_dcache(i, DCACHE_WRITEBACK);
  638. #endif
  639. }
  640. /* same as above but just that we would want cacheable for ocram too */
  641. i = CONFIG_SYS_INIT_RAM_ADDR >> 20;
  642. #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
  643. set_section_dcache(i, DCACHE_WRITETHROUGH);
  644. #else
  645. set_section_dcache(i, DCACHE_WRITEBACK);
  646. #endif
  647. }