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u-boot
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arch
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arm
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include
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asm
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arch-mxs
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sys_proto.h

sys_proto.h 2.6 KB
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  1. /*
    2. 

  2.  * Freescale i.MX23/i.MX28 specific functions
    3. 

  3.  *
    4. 

  4.  * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
    5. 

  5.  * on behalf of DENX Software Engineering GmbH
    6. 

  6.  *
    7. 

  7.  * SPDX-License-Identifier:	GPL-2.0+
    8. 

  8.  */
    9. 

  9. 

  10. #ifndef __MXS_SYS_PROTO_H__
    11. 

  11. #define __MXS_SYS_PROTO_H__
    12. 

  12. 

  13. #include <asm/mach-imx/sys_proto.h>
    14. 

  14. 

  15. int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int), int (*cd)(int));
    16. 

  16. 

  17. #ifdef CONFIG_SPL_BUILD
    18. 

  18. 

  19. #if defined(CONFIG_MX23)
    20. 

  20. #include <asm/arch/iomux-mx23.h>
    21. 

  21. #elif defined(CONFIG_MX28)
    22. 

  22. #include <asm/arch/iomux-mx28.h>
    23. 

  23. #endif
    24. 

  24. 

  25. void mxs_common_spl_init(const uint32_t arg, const uint32_t *resptr,
    26. 

  26. 			 const iomux_cfg_t *iomux_setup,
    27. 

  27. 			 const unsigned int iomux_size);
    28. 

  28. 

  29. void mxs_power_switch_dcdc_clocksource(uint32_t freqsel);
    30. 

  30. #endif
    31. 

  31. 

  32. struct mxs_pair {
    33. 

  33. 	uint8_t	boot_pads;
    34. 

  34. 	uint8_t boot_mask;
    35. 

  35. 	const char *mode;
    36. 

  36. };
    37. 

  37. 

  38. static const struct mxs_pair mxs_boot_modes[] = {
    39. 

  39. #if defined(CONFIG_MX23)
    40. 

  40. 	{ 0x00, 0x0f, "USB" },
    41. 

  41. 	{ 0x01, 0x1f, "I2C, master" },
    42. 

  42. 	{ 0x02, 0x1f, "SSP SPI #1, master, NOR" },
    43. 

  43. 	{ 0x03, 0x1f, "SSP SPI #2, master, NOR" },
    44. 

  44. 	{ 0x04, 0x1f, "NAND" },
    45. 

  45. 	{ 0x06, 0x1f, "JTAG" },
    46. 

  46. 	{ 0x08, 0x1f, "SSP SPI #3, master, EEPROM" },
    47. 

  47. 	{ 0x09, 0x1f, "SSP SD/MMC #0" },
    48. 

  48. 	{ 0x0a, 0x1f, "SSP SD/MMC #1" },
    49. 

  49. 	{ 0x00, 0x00, "Reserved/Unknown/Wrong" },
    50. 

  50. #elif defined(CONFIG_MX28)
    51. 

  51. 	{ 0x00, 0x0f, "USB #0" },
    52. 

  52. 	{ 0x01, 0x1f, "I2C #0, master, 3V3" },
    53. 

  53. 	{ 0x11, 0x1f, "I2C #0, master, 1V8" },
    54. 

  54. 	{ 0x02, 0x1f, "SSP SPI #2, master, 3V3 NOR" },
    55. 

  55. 	{ 0x12, 0x1f, "SSP SPI #2, master, 1V8 NOR" },
    56. 

  56. 	{ 0x03, 0x1f, "SSP SPI #3, master, 3V3 NOR" },
    57. 

  57. 	{ 0x13, 0x1f, "SSP SPI #3, master, 1V8 NOR" },
    58. 

  58. 	{ 0x04, 0x1f, "NAND, 3V3" },
    59. 

  59. 	{ 0x14, 0x1f, "NAND, 1V8" },
    60. 

  60. 	{ 0x06, 0x1f, "JTAG" },
    61. 

  61. 	{ 0x08, 0x1f, "SSP SPI #3, master, 3V3 EEPROM" },
    62. 

  62. 	{ 0x18, 0x1f, "SSP SPI #3, master, 1V8 EEPROM" },
    63. 

  63. 	{ 0x09, 0x1f, "SSP SD/MMC #0, 3V3" },
    64. 

  64. 	{ 0x19, 0x1f, "SSP SD/MMC #0, 1V8" },
    65. 

  65. 	{ 0x0a, 0x1f, "SSP SD/MMC #1, 3V3" },
    66. 

  66. 	{ 0x1a, 0x1f, "SSP SD/MMC #1, 1V8" },
    67. 

  67. 	{ 0x00, 0x00, "Reserved/Unknown/Wrong" },
    68. 

  68. #endif
    69. 

  69. };
    70. 

  70. 

  71. #define MXS_BM_USB			0x00
    72. 

  72. #define MXS_BM_I2C_MASTER_3V3		0x01
    73. 

  73. #define MXS_BM_I2C_MASTER_1V8		0x11
    74. 

  74. #define MXS_BM_SPI2_MASTER_3V3_NOR	0x02
    75. 

  75. #define MXS_BM_SPI2_MASTER_1V8_NOR	0x12
    76. 

  76. #define MXS_BM_SPI3_MASTER_3V3_NOR	0x03
    77. 

  77. #define MXS_BM_SPI3_MASTER_1V8_NOR	0x13
    78. 

  78. #define MXS_BM_NAND_3V3			0x04
    79. 

  79. #define MXS_BM_NAND_1V8			0x14
    80. 

  80. #define MXS_BM_JTAG			0x06
    81. 

  81. #define MXS_BM_SPI3_MASTER_3V3_EEPROM	0x08
    82. 

  82. #define MXS_BM_SPI3_MASTER_1V8_EEPROM	0x18
    83. 

  83. #define MXS_BM_SDMMC0_3V3		0x09
    84. 

  84. #define MXS_BM_SDMMC0_1V8		0x19
    85. 

  85. #define MXS_BM_SDMMC1_3V3		0x0a
    86. 

  86. #define MXS_BM_SDMMC1_1V8		0x1a
    87. 

  87. 

  88. struct mxs_spl_data {
    89. 

  89. 	uint8_t		boot_mode_idx;
    90. 

  90. 	uint32_t	mem_dram_size;
    91. 

  91. };
    92. 

  92. 

  93. int mxs_dram_init(void);
    94. 

  94. 

  95. #endif	/* __SYS_PROTO_H__ */
    96.