gpio.h 2.8 KB

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  1. /*
  2. * Copyright (c) 2012, Google Inc. All rights reserved.
  3. * SPDX-License-Identifier: GPL-2.0
  4. */
  5. #ifndef _X86_GPIO_H_
  6. #define _X86_GPIO_H_
  7. #include <linux/compiler.h>
  8. #include <asm/arch/gpio.h>
  9. #include <asm-generic/gpio.h>
  10. struct ich6_bank_platdata {
  11. uint16_t base_addr;
  12. const char *bank_name;
  13. };
  14. #define GPIO_MODE_NATIVE 0
  15. #define GPIO_MODE_GPIO 1
  16. #define GPIO_MODE_NONE 1
  17. #define GPIO_DIR_OUTPUT 0
  18. #define GPIO_DIR_INPUT 1
  19. #define GPIO_NO_INVERT 0
  20. #define GPIO_INVERT 1
  21. #define GPIO_LEVEL_LOW 0
  22. #define GPIO_LEVEL_HIGH 1
  23. #define GPIO_NO_BLINK 0
  24. #define GPIO_BLINK 1
  25. #define GPIO_RESET_PWROK 0
  26. #define GPIO_RESET_RSMRST 1
  27. struct pch_gpio_set1 {
  28. u32 gpio0:1;
  29. u32 gpio1:1;
  30. u32 gpio2:1;
  31. u32 gpio3:1;
  32. u32 gpio4:1;
  33. u32 gpio5:1;
  34. u32 gpio6:1;
  35. u32 gpio7:1;
  36. u32 gpio8:1;
  37. u32 gpio9:1;
  38. u32 gpio10:1;
  39. u32 gpio11:1;
  40. u32 gpio12:1;
  41. u32 gpio13:1;
  42. u32 gpio14:1;
  43. u32 gpio15:1;
  44. u32 gpio16:1;
  45. u32 gpio17:1;
  46. u32 gpio18:1;
  47. u32 gpio19:1;
  48. u32 gpio20:1;
  49. u32 gpio21:1;
  50. u32 gpio22:1;
  51. u32 gpio23:1;
  52. u32 gpio24:1;
  53. u32 gpio25:1;
  54. u32 gpio26:1;
  55. u32 gpio27:1;
  56. u32 gpio28:1;
  57. u32 gpio29:1;
  58. u32 gpio30:1;
  59. u32 gpio31:1;
  60. } __packed;
  61. struct pch_gpio_set2 {
  62. u32 gpio32:1;
  63. u32 gpio33:1;
  64. u32 gpio34:1;
  65. u32 gpio35:1;
  66. u32 gpio36:1;
  67. u32 gpio37:1;
  68. u32 gpio38:1;
  69. u32 gpio39:1;
  70. u32 gpio40:1;
  71. u32 gpio41:1;
  72. u32 gpio42:1;
  73. u32 gpio43:1;
  74. u32 gpio44:1;
  75. u32 gpio45:1;
  76. u32 gpio46:1;
  77. u32 gpio47:1;
  78. u32 gpio48:1;
  79. u32 gpio49:1;
  80. u32 gpio50:1;
  81. u32 gpio51:1;
  82. u32 gpio52:1;
  83. u32 gpio53:1;
  84. u32 gpio54:1;
  85. u32 gpio55:1;
  86. u32 gpio56:1;
  87. u32 gpio57:1;
  88. u32 gpio58:1;
  89. u32 gpio59:1;
  90. u32 gpio60:1;
  91. u32 gpio61:1;
  92. u32 gpio62:1;
  93. u32 gpio63:1;
  94. } __packed;
  95. struct pch_gpio_set3 {
  96. u32 gpio64:1;
  97. u32 gpio65:1;
  98. u32 gpio66:1;
  99. u32 gpio67:1;
  100. u32 gpio68:1;
  101. u32 gpio69:1;
  102. u32 gpio70:1;
  103. u32 gpio71:1;
  104. u32 gpio72:1;
  105. u32 gpio73:1;
  106. u32 gpio74:1;
  107. u32 gpio75:1;
  108. } __packed;
  109. /*
  110. * This hilariously complex structure came from Coreboot. The
  111. * setup_pch_gpios() function uses it. It could be move to device tree, or
  112. * adjust to use masks instead of bitfields.
  113. */
  114. struct pch_gpio_map {
  115. struct {
  116. const struct pch_gpio_set1 *mode;
  117. const struct pch_gpio_set1 *direction;
  118. const struct pch_gpio_set1 *level;
  119. const struct pch_gpio_set1 *reset;
  120. const struct pch_gpio_set1 *invert;
  121. const struct pch_gpio_set1 *blink;
  122. } set1;
  123. struct {
  124. const struct pch_gpio_set2 *mode;
  125. const struct pch_gpio_set2 *direction;
  126. const struct pch_gpio_set2 *level;
  127. const struct pch_gpio_set2 *reset;
  128. } set2;
  129. struct {
  130. const struct pch_gpio_set3 *mode;
  131. const struct pch_gpio_set3 *direction;
  132. const struct pch_gpio_set3 *level;
  133. const struct pch_gpio_set3 *reset;
  134. } set3;
  135. };
  136. int gpio_ich6_pinctrl_init(void);
  137. void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio);
  138. void ich_gpio_set_gpio_map(const struct pch_gpio_map *map);
  139. #endif /* _X86_GPIO_H_ */