serial_sh.c 4.4 KB

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  1. /*
  2. * SuperH SCIF device driver.
  3. * Copyright (C) 2013 Renesas Electronics Corporation
  4. * Copyright (C) 2007,2008,2010 Nobuhiro Iwamatsu
  5. * Copyright (C) 2002 - 2008 Paul Mundt
  6. *
  7. * SPDX-License-Identifier: GPL-2.0+
  8. */
  9. #include <common.h>
  10. #include <asm/io.h>
  11. #include <asm/processor.h>
  12. #include "serial_sh.h"
  13. #include <serial.h>
  14. #include <linux/compiler.h>
  15. #if defined(CONFIG_CONS_SCIF0)
  16. # define SCIF_BASE SCIF0_BASE
  17. #elif defined(CONFIG_CONS_SCIF1)
  18. # define SCIF_BASE SCIF1_BASE
  19. #elif defined(CONFIG_CONS_SCIF2)
  20. # define SCIF_BASE SCIF2_BASE
  21. #elif defined(CONFIG_CONS_SCIF3)
  22. # define SCIF_BASE SCIF3_BASE
  23. #elif defined(CONFIG_CONS_SCIF4)
  24. # define SCIF_BASE SCIF4_BASE
  25. #elif defined(CONFIG_CONS_SCIF5)
  26. # define SCIF_BASE SCIF5_BASE
  27. #elif defined(CONFIG_CONS_SCIF6)
  28. # define SCIF_BASE SCIF6_BASE
  29. #elif defined(CONFIG_CONS_SCIF7)
  30. # define SCIF_BASE SCIF7_BASE
  31. #else
  32. # error "Default SCIF doesn't set....."
  33. #endif
  34. #if defined(CONFIG_SCIF_A)
  35. #define SCIF_BASE_PORT PORT_SCIFA
  36. #else
  37. #define SCIF_BASE_PORT PORT_SCIF
  38. #endif
  39. static struct uart_port sh_sci = {
  40. .membase = (unsigned char*)SCIF_BASE,
  41. .mapbase = SCIF_BASE,
  42. .type = SCIF_BASE_PORT,
  43. };
  44. static void sh_serial_setbrg(void)
  45. {
  46. DECLARE_GLOBAL_DATA_PTR;
  47. #ifdef CONFIG_SCIF_USE_EXT_CLK
  48. unsigned short dl = DL_VALUE(gd->baudrate, CONFIG_SH_SCIF_CLK_FREQ);
  49. sci_out(&sh_sci, DL, dl);
  50. /* Need wait: Clock * 1/dl $B!_(B 1/16 */
  51. udelay((1000000 * dl * 16 / CONFIG_SYS_CLK_FREQ) * 1000 + 1);
  52. #else
  53. sci_out(&sh_sci, SCBRR,
  54. SCBRR_VALUE(gd->baudrate, CONFIG_SH_SCIF_CLK_FREQ));
  55. #endif
  56. }
  57. static int sh_serial_init(void)
  58. {
  59. sci_out(&sh_sci, SCSCR , SCSCR_INIT(&sh_sci));
  60. sci_out(&sh_sci, SCSCR , SCSCR_INIT(&sh_sci));
  61. sci_out(&sh_sci, SCSMR, 0);
  62. sci_out(&sh_sci, SCSMR, 0);
  63. sci_out(&sh_sci, SCFCR, SCFCR_RFRST|SCFCR_TFRST);
  64. sci_in(&sh_sci, SCFCR);
  65. sci_out(&sh_sci, SCFCR, 0);
  66. serial_setbrg();
  67. return 0;
  68. }
  69. #if defined(CONFIG_CPU_SH7760) || \
  70. defined(CONFIG_CPU_SH7780) || \
  71. defined(CONFIG_CPU_SH7785) || \
  72. defined(CONFIG_CPU_SH7786)
  73. static int scif_rxfill(struct uart_port *port)
  74. {
  75. return sci_in(port, SCRFDR) & 0xff;
  76. }
  77. #elif defined(CONFIG_CPU_SH7763)
  78. static int scif_rxfill(struct uart_port *port)
  79. {
  80. if ((port->mapbase == 0xffe00000) ||
  81. (port->mapbase == 0xffe08000)) {
  82. /* SCIF0/1*/
  83. return sci_in(port, SCRFDR) & 0xff;
  84. } else {
  85. /* SCIF2 */
  86. return sci_in(port, SCFDR) & SCIF2_RFDC_MASK;
  87. }
  88. }
  89. #elif defined(CONFIG_ARCH_SH7372)
  90. static int scif_rxfill(struct uart_port *port)
  91. {
  92. if (port->type == PORT_SCIFA)
  93. return sci_in(port, SCFDR) & SCIF_RFDC_MASK;
  94. else
  95. return sci_in(port, SCRFDR);
  96. }
  97. #else
  98. static int scif_rxfill(struct uart_port *port)
  99. {
  100. return sci_in(port, SCFDR) & SCIF_RFDC_MASK;
  101. }
  102. #endif
  103. static int serial_rx_fifo_level(void)
  104. {
  105. return scif_rxfill(&sh_sci);
  106. }
  107. static void handle_error(void)
  108. {
  109. sci_in(&sh_sci, SCxSR);
  110. sci_out(&sh_sci, SCxSR, SCxSR_ERROR_CLEAR(&sh_sci));
  111. sci_in(&sh_sci, SCLSR);
  112. sci_out(&sh_sci, SCLSR, 0x00);
  113. }
  114. void serial_raw_putc(const char c)
  115. {
  116. while (1) {
  117. /* Tx fifo is empty */
  118. if (sci_in(&sh_sci, SCxSR) & SCxSR_TEND(&sh_sci))
  119. break;
  120. }
  121. sci_out(&sh_sci, SCxTDR, c);
  122. sci_out(&sh_sci, SCxSR, sci_in(&sh_sci, SCxSR) & ~SCxSR_TEND(&sh_sci));
  123. }
  124. static void sh_serial_putc(const char c)
  125. {
  126. if (c == '\n')
  127. serial_raw_putc('\r');
  128. serial_raw_putc(c);
  129. }
  130. static int sh_serial_tstc(void)
  131. {
  132. if (sci_in(&sh_sci, SCxSR) & SCIF_ERRORS) {
  133. handle_error();
  134. return 0;
  135. }
  136. return serial_rx_fifo_level() ? 1 : 0;
  137. }
  138. int serial_getc_check(void)
  139. {
  140. unsigned short status;
  141. status = sci_in(&sh_sci, SCxSR);
  142. if (status & SCIF_ERRORS)
  143. handle_error();
  144. if (sci_in(&sh_sci, SCLSR) & SCxSR_ORER(&sh_sci))
  145. handle_error();
  146. return status & (SCIF_DR | SCxSR_RDxF(&sh_sci));
  147. }
  148. static int sh_serial_getc(void)
  149. {
  150. unsigned short status;
  151. char ch;
  152. while (!serial_getc_check())
  153. ;
  154. ch = sci_in(&sh_sci, SCxRDR);
  155. status = sci_in(&sh_sci, SCxSR);
  156. sci_out(&sh_sci, SCxSR, SCxSR_RDxF_CLEAR(&sh_sci));
  157. if (status & SCIF_ERRORS)
  158. handle_error();
  159. if (sci_in(&sh_sci, SCLSR) & SCxSR_ORER(&sh_sci))
  160. handle_error();
  161. return ch;
  162. }
  163. static struct serial_device sh_serial_drv = {
  164. .name = "sh_serial",
  165. .start = sh_serial_init,
  166. .stop = NULL,
  167. .setbrg = sh_serial_setbrg,
  168. .putc = sh_serial_putc,
  169. .puts = default_serial_puts,
  170. .getc = sh_serial_getc,
  171. .tstc = sh_serial_tstc,
  172. };
  173. void sh_serial_initialize(void)
  174. {
  175. serial_register(&sh_serial_drv);
  176. }
  177. __weak struct serial_device *default_serial_console(void)
  178. {
  179. return &sh_serial_drv;
  180. }