rk_spi.c 12 KB

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  1. /*
  2. * spi driver for rockchip
  3. *
  4. * (C) Copyright 2015 Google, Inc
  5. *
  6. * (C) Copyright 2008-2013 Rockchip Electronics
  7. * Peter, Software Engineering, <superpeter.cai@gmail.com>.
  8. *
  9. * SPDX-License-Identifier: GPL-2.0+
  10. */
  11. #include <common.h>
  12. #include <clk.h>
  13. #include <dm.h>
  14. #include <dt-structs.h>
  15. #include <errno.h>
  16. #include <spi.h>
  17. #include <linux/errno.h>
  18. #include <asm/io.h>
  19. #include <asm/arch/clock.h>
  20. #include <asm/arch/periph.h>
  21. #include <dm/pinctrl.h>
  22. #include "rk_spi.h"
  23. DECLARE_GLOBAL_DATA_PTR;
  24. /* Change to 1 to output registers at the start of each transaction */
  25. #define DEBUG_RK_SPI 0
  26. struct rockchip_spi_platdata {
  27. #if CONFIG_IS_ENABLED(OF_PLATDATA)
  28. struct dtd_rockchip_rk3288_spi of_plat;
  29. #endif
  30. s32 frequency; /* Default clock frequency, -1 for none */
  31. fdt_addr_t base;
  32. uint deactivate_delay_us; /* Delay to wait after deactivate */
  33. uint activate_delay_us; /* Delay to wait after activate */
  34. };
  35. struct rockchip_spi_priv {
  36. struct rockchip_spi *regs;
  37. struct clk clk;
  38. unsigned int max_freq;
  39. unsigned int mode;
  40. ulong last_transaction_us; /* Time of last transaction end */
  41. u8 bits_per_word; /* max 16 bits per word */
  42. u8 n_bytes;
  43. unsigned int speed_hz;
  44. unsigned int last_speed_hz;
  45. unsigned int tmode;
  46. uint input_rate;
  47. };
  48. #define SPI_FIFO_DEPTH 32
  49. static void rkspi_dump_regs(struct rockchip_spi *regs)
  50. {
  51. debug("ctrl0: \t\t0x%08x\n", readl(&regs->ctrlr0));
  52. debug("ctrl1: \t\t0x%08x\n", readl(&regs->ctrlr1));
  53. debug("ssienr: \t\t0x%08x\n", readl(&regs->enr));
  54. debug("ser: \t\t0x%08x\n", readl(&regs->ser));
  55. debug("baudr: \t\t0x%08x\n", readl(&regs->baudr));
  56. debug("txftlr: \t\t0x%08x\n", readl(&regs->txftlr));
  57. debug("rxftlr: \t\t0x%08x\n", readl(&regs->rxftlr));
  58. debug("txflr: \t\t0x%08x\n", readl(&regs->txflr));
  59. debug("rxflr: \t\t0x%08x\n", readl(&regs->rxflr));
  60. debug("sr: \t\t0x%08x\n", readl(&regs->sr));
  61. debug("imr: \t\t0x%08x\n", readl(&regs->imr));
  62. debug("isr: \t\t0x%08x\n", readl(&regs->isr));
  63. debug("dmacr: \t\t0x%08x\n", readl(&regs->dmacr));
  64. debug("dmatdlr: \t0x%08x\n", readl(&regs->dmatdlr));
  65. debug("dmardlr: \t0x%08x\n", readl(&regs->dmardlr));
  66. }
  67. static void rkspi_enable_chip(struct rockchip_spi *regs, bool enable)
  68. {
  69. writel(enable ? 1 : 0, &regs->enr);
  70. }
  71. static void rkspi_set_clk(struct rockchip_spi_priv *priv, uint speed)
  72. {
  73. /*
  74. * We should try not to exceed the speed requested by the caller:
  75. * when selecting a divider, we need to make sure we round up.
  76. */
  77. uint clk_div = DIV_ROUND_UP(priv->input_rate, speed);
  78. /* The baudrate register (BAUDR) is defined as a 32bit register where
  79. * the upper 16bit are reserved and having 'Fsclk_out' in the lower
  80. * 16bits with 'Fsclk_out' defined as follows:
  81. *
  82. * Fsclk_out = Fspi_clk/ SCKDV
  83. * Where SCKDV is any even value between 2 and 65534.
  84. */
  85. if (clk_div > 0xfffe) {
  86. clk_div = 0xfffe;
  87. debug("%s: can't divide down to %d hz (actual will be %d hz)\n",
  88. __func__, speed, priv->input_rate / clk_div);
  89. }
  90. /* Round up to the next even 16bit number */
  91. clk_div = (clk_div + 1) & 0xfffe;
  92. debug("spi speed %u, div %u\n", speed, clk_div);
  93. clrsetbits_le32(&priv->regs->baudr, 0xffff, clk_div);
  94. priv->last_speed_hz = speed;
  95. }
  96. static int rkspi_wait_till_not_busy(struct rockchip_spi *regs)
  97. {
  98. unsigned long start;
  99. start = get_timer(0);
  100. while (readl(&regs->sr) & SR_BUSY) {
  101. if (get_timer(start) > ROCKCHIP_SPI_TIMEOUT_MS) {
  102. debug("RK SPI: Status keeps busy for 1000us after a read/write!\n");
  103. return -ETIMEDOUT;
  104. }
  105. }
  106. return 0;
  107. }
  108. static void spi_cs_activate(struct udevice *dev, uint cs)
  109. {
  110. struct udevice *bus = dev->parent;
  111. struct rockchip_spi_platdata *plat = bus->platdata;
  112. struct rockchip_spi_priv *priv = dev_get_priv(bus);
  113. struct rockchip_spi *regs = priv->regs;
  114. /* If it's too soon to do another transaction, wait */
  115. if (plat->deactivate_delay_us && priv->last_transaction_us) {
  116. ulong delay_us; /* The delay completed so far */
  117. delay_us = timer_get_us() - priv->last_transaction_us;
  118. if (delay_us < plat->deactivate_delay_us)
  119. udelay(plat->deactivate_delay_us - delay_us);
  120. }
  121. debug("activate cs%u\n", cs);
  122. writel(1 << cs, &regs->ser);
  123. if (plat->activate_delay_us)
  124. udelay(plat->activate_delay_us);
  125. }
  126. static void spi_cs_deactivate(struct udevice *dev, uint cs)
  127. {
  128. struct udevice *bus = dev->parent;
  129. struct rockchip_spi_platdata *plat = bus->platdata;
  130. struct rockchip_spi_priv *priv = dev_get_priv(bus);
  131. struct rockchip_spi *regs = priv->regs;
  132. debug("deactivate cs%u\n", cs);
  133. writel(0, &regs->ser);
  134. /* Remember time of this transaction so we can honour the bus delay */
  135. if (plat->deactivate_delay_us)
  136. priv->last_transaction_us = timer_get_us();
  137. }
  138. #if CONFIG_IS_ENABLED(OF_PLATDATA)
  139. static int conv_of_platdata(struct udevice *dev)
  140. {
  141. struct rockchip_spi_platdata *plat = dev->platdata;
  142. struct dtd_rockchip_rk3288_spi *dtplat = &plat->of_plat;
  143. struct rockchip_spi_priv *priv = dev_get_priv(dev);
  144. int ret;
  145. plat->base = dtplat->reg[0];
  146. plat->frequency = 20000000;
  147. ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &priv->clk);
  148. if (ret < 0)
  149. return ret;
  150. dev->req_seq = 0;
  151. return 0;
  152. }
  153. #endif
  154. static int rockchip_spi_ofdata_to_platdata(struct udevice *bus)
  155. {
  156. #if !CONFIG_IS_ENABLED(OF_PLATDATA)
  157. struct rockchip_spi_platdata *plat = dev_get_platdata(bus);
  158. struct rockchip_spi_priv *priv = dev_get_priv(bus);
  159. int ret;
  160. plat->base = devfdt_get_addr(bus);
  161. ret = clk_get_by_index(bus, 0, &priv->clk);
  162. if (ret < 0) {
  163. debug("%s: Could not get clock for %s: %d\n", __func__,
  164. bus->name, ret);
  165. return ret;
  166. }
  167. plat->frequency =
  168. dev_read_u32_default(bus, "spi-max-frequency", 50000000);
  169. plat->deactivate_delay_us =
  170. dev_read_u32_default(bus, "spi-deactivate-delay", 0);
  171. plat->activate_delay_us =
  172. dev_read_u32_default(bus, "spi-activate-delay", 0);
  173. debug("%s: base=%x, max-frequency=%d, deactivate_delay=%d\n",
  174. __func__, (uint)plat->base, plat->frequency,
  175. plat->deactivate_delay_us);
  176. #endif
  177. return 0;
  178. }
  179. static int rockchip_spi_calc_modclk(ulong max_freq)
  180. {
  181. unsigned div;
  182. const unsigned long gpll_hz = 594000000UL;
  183. /*
  184. * We need to find an input clock that provides at least twice
  185. * the maximum frequency and can be generated from the assumed
  186. * speed of GPLL (594MHz) using an integer divider.
  187. *
  188. * To give us more achievable bitrates at higher speeds (these
  189. * are generated by dividing by an even 16-bit integer from
  190. * this frequency), we try to have an input frequency of at
  191. * least 4x our max_freq.
  192. */
  193. div = DIV_ROUND_UP(gpll_hz, max_freq * 4);
  194. return gpll_hz / div;
  195. }
  196. static int rockchip_spi_probe(struct udevice *bus)
  197. {
  198. struct rockchip_spi_platdata *plat = dev_get_platdata(bus);
  199. struct rockchip_spi_priv *priv = dev_get_priv(bus);
  200. int ret;
  201. debug("%s: probe\n", __func__);
  202. #if CONFIG_IS_ENABLED(OF_PLATDATA)
  203. ret = conv_of_platdata(bus);
  204. if (ret)
  205. return ret;
  206. #endif
  207. priv->regs = (struct rockchip_spi *)plat->base;
  208. priv->last_transaction_us = timer_get_us();
  209. priv->max_freq = plat->frequency;
  210. /* Clamp the value from the DTS against any hardware limits */
  211. if (priv->max_freq > ROCKCHIP_SPI_MAX_RATE)
  212. priv->max_freq = ROCKCHIP_SPI_MAX_RATE;
  213. /* Find a module-input clock that fits with the max_freq setting */
  214. ret = clk_set_rate(&priv->clk,
  215. rockchip_spi_calc_modclk(priv->max_freq));
  216. if (ret < 0) {
  217. debug("%s: Failed to set clock: %d\n", __func__, ret);
  218. return ret;
  219. }
  220. priv->input_rate = ret;
  221. debug("%s: rate = %u\n", __func__, priv->input_rate);
  222. priv->bits_per_word = 8;
  223. priv->tmode = TMOD_TR; /* Tx & Rx */
  224. return 0;
  225. }
  226. static int rockchip_spi_claim_bus(struct udevice *dev)
  227. {
  228. struct udevice *bus = dev->parent;
  229. struct rockchip_spi_priv *priv = dev_get_priv(bus);
  230. struct rockchip_spi *regs = priv->regs;
  231. u8 spi_dfs, spi_tf;
  232. uint ctrlr0;
  233. /* Disable the SPI hardware */
  234. rkspi_enable_chip(regs, 0);
  235. switch (priv->bits_per_word) {
  236. case 8:
  237. priv->n_bytes = 1;
  238. spi_dfs = DFS_8BIT;
  239. spi_tf = HALF_WORD_OFF;
  240. break;
  241. case 16:
  242. priv->n_bytes = 2;
  243. spi_dfs = DFS_16BIT;
  244. spi_tf = HALF_WORD_ON;
  245. break;
  246. default:
  247. debug("%s: unsupported bits: %dbits\n", __func__,
  248. priv->bits_per_word);
  249. return -EPROTONOSUPPORT;
  250. }
  251. if (priv->speed_hz != priv->last_speed_hz)
  252. rkspi_set_clk(priv, priv->speed_hz);
  253. /* Operation Mode */
  254. ctrlr0 = OMOD_MASTER << OMOD_SHIFT;
  255. /* Data Frame Size */
  256. ctrlr0 |= spi_dfs << DFS_SHIFT;
  257. /* set SPI mode 0..3 */
  258. if (priv->mode & SPI_CPOL)
  259. ctrlr0 |= SCOL_HIGH << SCOL_SHIFT;
  260. if (priv->mode & SPI_CPHA)
  261. ctrlr0 |= SCPH_TOGSTA << SCPH_SHIFT;
  262. /* Chip Select Mode */
  263. ctrlr0 |= CSM_KEEP << CSM_SHIFT;
  264. /* SSN to Sclk_out delay */
  265. ctrlr0 |= SSN_DELAY_ONE << SSN_DELAY_SHIFT;
  266. /* Serial Endian Mode */
  267. ctrlr0 |= SEM_LITTLE << SEM_SHIFT;
  268. /* First Bit Mode */
  269. ctrlr0 |= FBM_MSB << FBM_SHIFT;
  270. /* Byte and Halfword Transform */
  271. ctrlr0 |= spi_tf << HALF_WORD_TX_SHIFT;
  272. /* Rxd Sample Delay */
  273. ctrlr0 |= 0 << RXDSD_SHIFT;
  274. /* Frame Format */
  275. ctrlr0 |= FRF_SPI << FRF_SHIFT;
  276. /* Tx and Rx mode */
  277. ctrlr0 |= (priv->tmode & TMOD_MASK) << TMOD_SHIFT;
  278. writel(ctrlr0, &regs->ctrlr0);
  279. return 0;
  280. }
  281. static int rockchip_spi_release_bus(struct udevice *dev)
  282. {
  283. struct udevice *bus = dev->parent;
  284. struct rockchip_spi_priv *priv = dev_get_priv(bus);
  285. rkspi_enable_chip(priv->regs, false);
  286. return 0;
  287. }
  288. static int rockchip_spi_xfer(struct udevice *dev, unsigned int bitlen,
  289. const void *dout, void *din, unsigned long flags)
  290. {
  291. struct udevice *bus = dev->parent;
  292. struct rockchip_spi_priv *priv = dev_get_priv(bus);
  293. struct rockchip_spi *regs = priv->regs;
  294. struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
  295. int len = bitlen >> 3;
  296. const u8 *out = dout;
  297. u8 *in = din;
  298. int toread, towrite;
  299. int ret;
  300. debug("%s: dout=%p, din=%p, len=%x, flags=%lx\n", __func__, dout, din,
  301. len, flags);
  302. if (DEBUG_RK_SPI)
  303. rkspi_dump_regs(regs);
  304. /* Assert CS before transfer */
  305. if (flags & SPI_XFER_BEGIN)
  306. spi_cs_activate(dev, slave_plat->cs);
  307. while (len > 0) {
  308. int todo = min(len, 0xffff);
  309. rkspi_enable_chip(regs, false);
  310. writel(todo - 1, &regs->ctrlr1);
  311. rkspi_enable_chip(regs, true);
  312. toread = todo;
  313. towrite = todo;
  314. while (toread || towrite) {
  315. u32 status = readl(&regs->sr);
  316. if (towrite && !(status & SR_TF_FULL)) {
  317. writel(out ? *out++ : 0, regs->txdr);
  318. towrite--;
  319. }
  320. if (toread && !(status & SR_RF_EMPT)) {
  321. u32 byte = readl(regs->rxdr);
  322. if (in)
  323. *in++ = byte;
  324. toread--;
  325. }
  326. }
  327. ret = rkspi_wait_till_not_busy(regs);
  328. if (ret)
  329. break;
  330. len -= todo;
  331. }
  332. /* Deassert CS after transfer */
  333. if (flags & SPI_XFER_END)
  334. spi_cs_deactivate(dev, slave_plat->cs);
  335. rkspi_enable_chip(regs, false);
  336. return ret;
  337. }
  338. static int rockchip_spi_set_speed(struct udevice *bus, uint speed)
  339. {
  340. struct rockchip_spi_priv *priv = dev_get_priv(bus);
  341. /* Clamp to the maximum frequency specified in the DTS */
  342. if (speed > priv->max_freq)
  343. speed = priv->max_freq;
  344. priv->speed_hz = speed;
  345. return 0;
  346. }
  347. static int rockchip_spi_set_mode(struct udevice *bus, uint mode)
  348. {
  349. struct rockchip_spi_priv *priv = dev_get_priv(bus);
  350. priv->mode = mode;
  351. return 0;
  352. }
  353. static const struct dm_spi_ops rockchip_spi_ops = {
  354. .claim_bus = rockchip_spi_claim_bus,
  355. .release_bus = rockchip_spi_release_bus,
  356. .xfer = rockchip_spi_xfer,
  357. .set_speed = rockchip_spi_set_speed,
  358. .set_mode = rockchip_spi_set_mode,
  359. /*
  360. * cs_info is not needed, since we require all chip selects to be
  361. * in the device tree explicitly
  362. */
  363. };
  364. static const struct udevice_id rockchip_spi_ids[] = {
  365. { .compatible = "rockchip,rk3288-spi" },
  366. { .compatible = "rockchip,rk3399-spi" },
  367. { }
  368. };
  369. U_BOOT_DRIVER(rockchip_spi) = {
  370. #if CONFIG_IS_ENABLED(OF_PLATDATA)
  371. .name = "rockchip_rk3288_spi",
  372. #else
  373. .name = "rockchip_spi",
  374. #endif
  375. .id = UCLASS_SPI,
  376. .of_match = rockchip_spi_ids,
  377. .ops = &rockchip_spi_ops,
  378. .ofdata_to_platdata = rockchip_spi_ofdata_to_platdata,
  379. .platdata_auto_alloc_size = sizeof(struct rockchip_spi_platdata),
  380. .priv_auto_alloc_size = sizeof(struct rockchip_spi_priv),
  381. .probe = rockchip_spi_probe,
  382. };