ast_i2c.c 8.0 KB

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  1. /*
  2. * Copyright (C) 2012-2020 ASPEED Technology Inc.
  3. * Copyright 2016 IBM Corporation
  4. * Copyright 2017 Google, Inc.
  5. *
  6. * SPDX-License-Identifier: GPL-2.0+
  7. */
  8. #include <common.h>
  9. #include <clk.h>
  10. #include <dm.h>
  11. #include <errno.h>
  12. #include <fdtdec.h>
  13. #include <i2c.h>
  14. #include <asm/io.h>
  15. #include <asm/arch/scu_ast2500.h>
  16. #include "ast_i2c.h"
  17. #define I2C_TIMEOUT_US 100000
  18. #define I2C_SLEEP_STEP_US 20
  19. #define HIGHSPEED_TTIMEOUT 3
  20. DECLARE_GLOBAL_DATA_PTR;
  21. /*
  22. * Device private data
  23. */
  24. struct ast_i2c_priv {
  25. /* This device's clock */
  26. struct clk clk;
  27. /* Device registers */
  28. struct ast_i2c_regs *regs;
  29. /* I2C speed in Hz */
  30. int speed;
  31. };
  32. /*
  33. * Given desired divider ratio, return the value that needs to be set
  34. * in Clock and AC Timing Control register
  35. */
  36. static u32 get_clk_reg_val(ulong divider_ratio)
  37. {
  38. ulong inc = 0, div;
  39. ulong scl_low, scl_high, data;
  40. for (div = 0; divider_ratio >= 16; div++) {
  41. inc |= (divider_ratio & 1);
  42. divider_ratio >>= 1;
  43. }
  44. divider_ratio += inc;
  45. scl_low = (divider_ratio >> 1) - 1;
  46. scl_high = divider_ratio - scl_low - 2;
  47. data = I2CD_CACTC_BASE
  48. | (scl_high << I2CD_TCKHIGH_SHIFT)
  49. | (scl_low << I2CD_TCKLOW_SHIFT)
  50. | (div << I2CD_BASE_DIV_SHIFT);
  51. return data;
  52. }
  53. static void ast_i2c_clear_interrupts(struct udevice *dev)
  54. {
  55. struct ast_i2c_priv *priv = dev_get_priv(dev);
  56. writel(~0, &priv->regs->isr);
  57. }
  58. static void ast_i2c_init_bus(struct udevice *dev)
  59. {
  60. struct ast_i2c_priv *priv = dev_get_priv(dev);
  61. /* Reset device */
  62. writel(0, &priv->regs->fcr);
  63. /* Enable Master Mode. Assuming single-master */
  64. writel(I2CD_MASTER_EN
  65. | I2CD_M_SDA_LOCK_EN
  66. | I2CD_MULTI_MASTER_DIS | I2CD_M_SCL_DRIVE_EN,
  67. &priv->regs->fcr);
  68. /* Enable Interrupts */
  69. writel(I2CD_INTR_TX_ACK
  70. | I2CD_INTR_TX_NAK
  71. | I2CD_INTR_RX_DONE
  72. | I2CD_INTR_BUS_RECOVER_DONE
  73. | I2CD_INTR_NORMAL_STOP
  74. | I2CD_INTR_ABNORMAL, &priv->regs->icr);
  75. }
  76. static int ast_i2c_ofdata_to_platdata(struct udevice *dev)
  77. {
  78. struct ast_i2c_priv *priv = dev_get_priv(dev);
  79. int ret;
  80. priv->regs = dev_get_addr_ptr(dev);
  81. if (IS_ERR(priv->regs))
  82. return PTR_ERR(priv->regs);
  83. ret = clk_get_by_index(dev, 0, &priv->clk);
  84. if (ret < 0) {
  85. debug("%s: Can't get clock for %s: %d\n", __func__, dev->name,
  86. ret);
  87. return ret;
  88. }
  89. return 0;
  90. }
  91. static int ast_i2c_probe(struct udevice *dev)
  92. {
  93. struct ast2500_scu *scu;
  94. debug("Enabling I2C%u\n", dev->seq);
  95. /*
  96. * Get all I2C devices out of Reset.
  97. * Only needs to be done once, but doing it for every
  98. * device does not hurt.
  99. */
  100. scu = ast_get_scu();
  101. ast_scu_unlock(scu);
  102. clrbits_le32(&scu->sysreset_ctrl1, SCU_SYSRESET_I2C);
  103. ast_scu_lock(scu);
  104. ast_i2c_init_bus(dev);
  105. return 0;
  106. }
  107. static int ast_i2c_wait_isr(struct udevice *dev, u32 flag)
  108. {
  109. struct ast_i2c_priv *priv = dev_get_priv(dev);
  110. int timeout = I2C_TIMEOUT_US;
  111. while (!(readl(&priv->regs->isr) & flag) && timeout > 0) {
  112. udelay(I2C_SLEEP_STEP_US);
  113. timeout -= I2C_SLEEP_STEP_US;
  114. }
  115. ast_i2c_clear_interrupts(dev);
  116. if (timeout <= 0)
  117. return -ETIMEDOUT;
  118. return 0;
  119. }
  120. static int ast_i2c_send_stop(struct udevice *dev)
  121. {
  122. struct ast_i2c_priv *priv = dev_get_priv(dev);
  123. writel(I2CD_M_STOP_CMD, &priv->regs->csr);
  124. return ast_i2c_wait_isr(dev, I2CD_INTR_NORMAL_STOP);
  125. }
  126. static int ast_i2c_wait_tx(struct udevice *dev)
  127. {
  128. struct ast_i2c_priv *priv = dev_get_priv(dev);
  129. int timeout = I2C_TIMEOUT_US;
  130. u32 flag = I2CD_INTR_TX_ACK | I2CD_INTR_TX_NAK;
  131. u32 status = readl(&priv->regs->isr) & flag;
  132. int ret = 0;
  133. while (!status && timeout > 0) {
  134. status = readl(&priv->regs->isr) & flag;
  135. udelay(I2C_SLEEP_STEP_US);
  136. timeout -= I2C_SLEEP_STEP_US;
  137. }
  138. if (status == I2CD_INTR_TX_NAK)
  139. ret = -EREMOTEIO;
  140. if (timeout <= 0)
  141. ret = -ETIMEDOUT;
  142. ast_i2c_clear_interrupts(dev);
  143. return ret;
  144. }
  145. static int ast_i2c_start_txn(struct udevice *dev, uint devaddr)
  146. {
  147. struct ast_i2c_priv *priv = dev_get_priv(dev);
  148. /* Start and Send Device Address */
  149. writel(devaddr, &priv->regs->trbbr);
  150. writel(I2CD_M_START_CMD | I2CD_M_TX_CMD, &priv->regs->csr);
  151. return ast_i2c_wait_tx(dev);
  152. }
  153. static int ast_i2c_read_data(struct udevice *dev, u8 chip_addr, u8 *buffer,
  154. size_t len, bool send_stop)
  155. {
  156. struct ast_i2c_priv *priv = dev_get_priv(dev);
  157. u32 i2c_cmd = I2CD_M_RX_CMD;
  158. int ret;
  159. ret = ast_i2c_start_txn(dev, (chip_addr << 1) | I2C_M_RD);
  160. if (ret < 0)
  161. return ret;
  162. for (; len > 0; len--, buffer++) {
  163. if (len == 1)
  164. i2c_cmd |= I2CD_M_S_RX_CMD_LAST;
  165. writel(i2c_cmd, &priv->regs->csr);
  166. ret = ast_i2c_wait_isr(dev, I2CD_INTR_RX_DONE);
  167. if (ret < 0)
  168. return ret;
  169. *buffer = (readl(&priv->regs->trbbr) & I2CD_RX_DATA_MASK)
  170. >> I2CD_RX_DATA_SHIFT;
  171. }
  172. ast_i2c_clear_interrupts(dev);
  173. if (send_stop)
  174. return ast_i2c_send_stop(dev);
  175. return 0;
  176. }
  177. static int ast_i2c_write_data(struct udevice *dev, u8 chip_addr, u8
  178. *buffer, size_t len, bool send_stop)
  179. {
  180. struct ast_i2c_priv *priv = dev_get_priv(dev);
  181. int ret;
  182. ret = ast_i2c_start_txn(dev, (chip_addr << 1));
  183. if (ret < 0)
  184. return ret;
  185. for (; len > 0; len--, buffer++) {
  186. writel(*buffer, &priv->regs->trbbr);
  187. writel(I2CD_M_TX_CMD, &priv->regs->csr);
  188. ret = ast_i2c_wait_tx(dev);
  189. if (ret < 0)
  190. return ret;
  191. }
  192. if (send_stop)
  193. return ast_i2c_send_stop(dev);
  194. return 0;
  195. }
  196. static int ast_i2c_deblock(struct udevice *dev)
  197. {
  198. struct ast_i2c_priv *priv = dev_get_priv(dev);
  199. struct ast_i2c_regs *regs = priv->regs;
  200. u32 csr = readl(&regs->csr);
  201. bool sda_high = csr & I2CD_SDA_LINE_STS;
  202. bool scl_high = csr & I2CD_SCL_LINE_STS;
  203. int ret = 0;
  204. if (sda_high && scl_high) {
  205. /* Bus is idle, no deblocking needed. */
  206. return 0;
  207. } else if (sda_high) {
  208. /* Send stop command */
  209. debug("Unterminated TXN in (%x), sending stop\n", csr);
  210. ret = ast_i2c_send_stop(dev);
  211. } else if (scl_high) {
  212. /* Possibly stuck slave */
  213. debug("Bus stuck (%x), attempting recovery\n", csr);
  214. writel(I2CD_BUS_RECOVER_CMD, &regs->csr);
  215. ret = ast_i2c_wait_isr(dev, I2CD_INTR_BUS_RECOVER_DONE);
  216. } else {
  217. /* Just try to reinit the device. */
  218. ast_i2c_init_bus(dev);
  219. }
  220. return ret;
  221. }
  222. static int ast_i2c_xfer(struct udevice *dev, struct i2c_msg *msg, int nmsgs)
  223. {
  224. int ret;
  225. ret = ast_i2c_deblock(dev);
  226. if (ret < 0)
  227. return ret;
  228. debug("i2c_xfer: %d messages\n", nmsgs);
  229. for (; nmsgs > 0; nmsgs--, msg++) {
  230. if (msg->flags & I2C_M_RD) {
  231. debug("i2c_read: chip=0x%x, len=0x%x, flags=0x%x\n",
  232. msg->addr, msg->len, msg->flags);
  233. ret = ast_i2c_read_data(dev, msg->addr, msg->buf,
  234. msg->len, (nmsgs == 1));
  235. } else {
  236. debug("i2c_write: chip=0x%x, len=0x%x, flags=0x%x\n",
  237. msg->addr, msg->len, msg->flags);
  238. ret = ast_i2c_write_data(dev, msg->addr, msg->buf,
  239. msg->len, (nmsgs == 1));
  240. }
  241. if (ret) {
  242. debug("%s: error (%d)\n", __func__, ret);
  243. return -EREMOTEIO;
  244. }
  245. }
  246. return 0;
  247. }
  248. static int ast_i2c_set_speed(struct udevice *dev, unsigned int speed)
  249. {
  250. struct ast_i2c_priv *priv = dev_get_priv(dev);
  251. struct ast_i2c_regs *regs = priv->regs;
  252. ulong i2c_rate, divider;
  253. debug("Setting speed for I2C%d to <%u>\n", dev->seq, speed);
  254. if (!speed) {
  255. debug("No valid speed specified\n");
  256. return -EINVAL;
  257. }
  258. i2c_rate = clk_get_rate(&priv->clk);
  259. divider = i2c_rate / speed;
  260. priv->speed = speed;
  261. if (speed > I2C_HIGHSPEED_RATE) {
  262. debug("Enable High Speed\n");
  263. setbits_le32(&regs->fcr, I2CD_M_HIGH_SPEED_EN
  264. | I2CD_M_SDA_DRIVE_1T_EN
  265. | I2CD_SDA_DRIVE_1T_EN);
  266. writel(HIGHSPEED_TTIMEOUT, &regs->cactcr2);
  267. } else {
  268. debug("Enabling Normal Speed\n");
  269. writel(I2CD_NO_TIMEOUT_CTRL, &regs->cactcr2);
  270. }
  271. writel(get_clk_reg_val(divider), &regs->cactcr1);
  272. ast_i2c_clear_interrupts(dev);
  273. return 0;
  274. }
  275. static const struct dm_i2c_ops ast_i2c_ops = {
  276. .xfer = ast_i2c_xfer,
  277. .set_bus_speed = ast_i2c_set_speed,
  278. .deblock = ast_i2c_deblock,
  279. };
  280. static const struct udevice_id ast_i2c_ids[] = {
  281. { .compatible = "aspeed,ast2400-i2c-bus" },
  282. { .compatible = "aspeed,ast2500-i2c-bus" },
  283. { },
  284. };
  285. U_BOOT_DRIVER(ast_i2c) = {
  286. .name = "ast_i2c",
  287. .id = UCLASS_I2C,
  288. .of_match = ast_i2c_ids,
  289. .probe = ast_i2c_probe,
  290. .ofdata_to_platdata = ast_i2c_ofdata_to_platdata,
  291. .priv_auto_alloc_size = sizeof(struct ast_i2c_priv),
  292. .ops = &ast_i2c_ops,
  293. };