.. |
base_addr_a10.h
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5a7152e4fd
ARM: socfpga: arria10: add base address map for Arria10
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9 years ago |
base_addr_ac5.h
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871c24bc50
ARM: socfpga: rename the cyclone5 and arria5 base address file
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9 years ago |
boot0.h
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4c0f3e7f7b
ARM: socfpga: boot0 hook: remove macro from boot0 header file
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8 years ago |
clock_manager.h
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a45526aaa0
arm: socfpga: set the mpuclk divider in the Altera group register
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8 years ago |
fpga_manager.h
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30088b0997
ARM: socfpga: move SoC headers to mach-socfpga/include/mach
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10 years ago |
freeze_controller.h
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30088b0997
ARM: socfpga: move SoC headers to mach-socfpga/include/mach
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10 years ago |
gpio.h
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30088b0997
ARM: socfpga: move SoC headers to mach-socfpga/include/mach
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10 years ago |
nic301.h
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30088b0997
ARM: socfpga: move SoC headers to mach-socfpga/include/mach
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10 years ago |
reset_manager.h
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f2f3782ead
arm: socfpga: Define NAND reset bit
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9 years ago |
scan_manager.h
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bd0f5a91f3
arm: socfpga: scan: Add code to get FPGA ID
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9 years ago |
scu.h
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30088b0997
ARM: socfpga: move SoC headers to mach-socfpga/include/mach
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10 years ago |
sdram.h
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89a54abf1b
ddr: altera: Configuring SDRAM extra cycles timing parameters
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8 years ago |
system_manager.h
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a1684b6105
arm: socfpga: fix up a questionable macro for SDMMC
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9 years ago |
timer.h
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30088b0997
ARM: socfpga: move SoC headers to mach-socfpga/include/mach
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10 years ago |