spd_sdram.c 34 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334
  1. /*
  2. * Copyright 2004 Freescale Semiconductor.
  3. * (C) Copyright 2003 Motorola Inc.
  4. * Xianghua Xiao (X.Xiao@motorola.com)
  5. *
  6. * See file CREDITS for list of people who contributed to this
  7. * project.
  8. *
  9. * This program is free software; you can redistribute it and/or
  10. * modify it under the terms of the GNU General Public License as
  11. * published by the Free Software Foundation; either version 2 of
  12. * the License, or (at your option) any later version.
  13. *
  14. * This program is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * You should have received a copy of the GNU General Public License
  20. * along with this program; if not, write to the Free Software
  21. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22. * MA 02111-1307 USA
  23. */
  24. #include <common.h>
  25. #include <asm/processor.h>
  26. #include <i2c.h>
  27. #include <spd.h>
  28. #include <asm/mmu.h>
  29. #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
  30. extern void dma_init(void);
  31. extern uint dma_check(void);
  32. extern int dma_xfer(void *dest, uint count, void *src);
  33. #endif
  34. #ifdef CONFIG_SPD_EEPROM
  35. #ifndef CFG_READ_SPD
  36. #define CFG_READ_SPD i2c_read
  37. #endif
  38. /*
  39. * Only one of the following three should be 1; others should be 0
  40. * By default the cache line interleaving is selected if
  41. * the CONFIG_DDR_INTERLEAVE flag is defined
  42. */
  43. #define CFG_PAGE_INTERLEAVING 0
  44. #define CFG_BANK_INTERLEAVING 0
  45. #define CFG_SUPER_BANK_INTERLEAVING 0
  46. /*
  47. * Convert picoseconds into clock cycles (rounding up if needed).
  48. */
  49. int
  50. picos_to_clk(int picos)
  51. {
  52. int clks;
  53. clks = picos / (2000000000 / (get_bus_freq(0) / 1000));
  54. if (picos % (2000000000 / (get_bus_freq(0) / 1000)) != 0) {
  55. clks++;
  56. }
  57. return clks;
  58. }
  59. /*
  60. * Calculate the Density of each Physical Rank.
  61. * Returned size is in bytes.
  62. *
  63. * Study these table from Byte 31 of JEDEC SPD Spec.
  64. *
  65. * DDR I DDR II
  66. * Bit Size Size
  67. * --- ----- ------
  68. * 7 high 512MB 512MB
  69. * 6 256MB 256MB
  70. * 5 128MB 128MB
  71. * 4 64MB 16GB
  72. * 3 32MB 8GB
  73. * 2 16MB 4GB
  74. * 1 2GB 2GB
  75. * 0 low 1GB 1GB
  76. *
  77. * Reorder Table to be linear by stripping the bottom
  78. * 2 or 5 bits off and shifting them up to the top.
  79. */
  80. unsigned int
  81. compute_banksize(unsigned int mem_type, unsigned char row_dens)
  82. {
  83. unsigned int bsize;
  84. if (mem_type == SPD_MEMTYPE_DDR) {
  85. /* Bottom 2 bits up to the top. */
  86. bsize = ((row_dens >> 2) | ((row_dens & 3) << 6)) << 24;
  87. debug("DDR: DDR I rank density = 0x%08x\n", bsize);
  88. } else {
  89. /* Bottom 5 bits up to the top. */
  90. bsize = ((row_dens >> 5) | ((row_dens & 31) << 3)) << 27;
  91. debug("DDR: DDR II rank density = 0x%08x\n", bsize);
  92. }
  93. return bsize;
  94. }
  95. /*
  96. * Convert a two-nibble BCD value into a cycle time.
  97. * While the spec calls for nano-seconds, picos are returned.
  98. *
  99. * This implements the tables for bytes 9, 23 and 25 for both
  100. * DDR I and II. No allowance for distinguishing the invalid
  101. * fields absent for DDR I yet present in DDR II is made.
  102. * (That is, cycle times of .25, .33, .66 and .75 ns are
  103. * allowed for both DDR II and I.)
  104. */
  105. unsigned int
  106. convert_bcd_tenths_to_cycle_time_ps(unsigned int spd_val)
  107. {
  108. /*
  109. * Table look up the lower nibble, allow DDR I & II.
  110. */
  111. unsigned int tenths_ps[16] = {
  112. 0,
  113. 100,
  114. 200,
  115. 300,
  116. 400,
  117. 500,
  118. 600,
  119. 700,
  120. 800,
  121. 900,
  122. 250,
  123. 330,
  124. 660,
  125. 750,
  126. 0, /* undefined */
  127. 0 /* undefined */
  128. };
  129. unsigned int whole_ns = (spd_val & 0xF0) >> 4;
  130. unsigned int tenth_ns = spd_val & 0x0F;
  131. unsigned int ps = whole_ns * 1000 + tenths_ps[tenth_ns];
  132. return ps;
  133. }
  134. long int
  135. spd_init(unsigned char i2c_address, unsigned int ddr_num,
  136. unsigned int dimm_num, unsigned int start_addr)
  137. {
  138. volatile immap_t *immap = (immap_t *)CFG_IMMR;
  139. volatile ccsr_ddr_t *ddr;
  140. volatile ccsr_gur_t *gur = &immap->im_gur;
  141. spd_eeprom_t spd;
  142. unsigned int n_ranks;
  143. unsigned int rank_density;
  144. unsigned int odt_rd_cfg, odt_wr_cfg;
  145. unsigned int odt_cfg, mode_odt_enable;
  146. unsigned int dqs_cfg;
  147. unsigned char twr_clk, twtr_clk, twr_auto_clk;
  148. unsigned int tCKmin_ps, tCKmax_ps;
  149. unsigned int max_data_rate;
  150. unsigned int busfreq;
  151. unsigned sdram_cfg_1;
  152. unsigned int memsize;
  153. unsigned char caslat, caslat_ctrl;
  154. unsigned int trfc, trfc_clk, trfc_low, trfc_high;
  155. unsigned int trcd_clk;
  156. unsigned int trtp_clk;
  157. unsigned char cke_min_clk;
  158. unsigned char add_lat;
  159. unsigned char wr_lat;
  160. unsigned char wr_data_delay;
  161. unsigned char four_act;
  162. unsigned char cpo;
  163. unsigned char burst_len;
  164. unsigned int mode_caslat;
  165. unsigned char sdram_type;
  166. unsigned char d_init;
  167. unsigned int law_size;
  168. volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm;
  169. unsigned int tCycle_ps, modfreq;
  170. if (ddr_num == 1)
  171. ddr = &immap->im_ddr1;
  172. else
  173. ddr = &immap->im_ddr2;
  174. /*
  175. * Read SPD information.
  176. */
  177. debug("Performing SPD read at I2C address 0x%02lx\n",i2c_address);
  178. memset((void *)&spd, 0, sizeof(spd));
  179. CFG_READ_SPD(i2c_address, 0, 1, (uchar *) &spd, sizeof(spd));
  180. /*
  181. * Check for supported memory module types.
  182. */
  183. if (spd.mem_type != SPD_MEMTYPE_DDR &&
  184. spd.mem_type != SPD_MEMTYPE_DDR2) {
  185. debug("Warning: Unable to locate DDR I or DDR II module for DIMM %d of DDR controller %d.\n"
  186. " Fundamental memory type is 0x%0x\n",
  187. dimm_num,
  188. ddr_num,
  189. spd.mem_type);
  190. return 0;
  191. }
  192. debug("\nFound memory of type 0x%02lx ", spd.mem_type);
  193. if (spd.mem_type == SPD_MEMTYPE_DDR)
  194. debug("DDR I\n");
  195. else
  196. debug("DDR II\n");
  197. /*
  198. * These test gloss over DDR I and II differences in interpretation
  199. * of bytes 3 and 4, but irrelevantly. Multiple asymmetric banks
  200. * are not supported on DDR I; and not encoded on DDR II.
  201. *
  202. * Also note that the 8548 controller can support:
  203. * 12 <= nrow <= 16
  204. * and
  205. * 8 <= ncol <= 11 (still, for DDR)
  206. * 6 <= ncol <= 9 (for FCRAM)
  207. */
  208. if (spd.nrow_addr < 12 || spd.nrow_addr > 14) {
  209. printf("DDR: Unsupported number of Row Addr lines: %d.\n",
  210. spd.nrow_addr);
  211. return 0;
  212. }
  213. if (spd.ncol_addr < 8 || spd.ncol_addr > 11) {
  214. printf("DDR: Unsupported number of Column Addr lines: %d.\n",
  215. spd.ncol_addr);
  216. return 0;
  217. }
  218. /*
  219. * Determine the number of physical banks controlled by
  220. * different Chip Select signals. This is not quite the
  221. * same as the number of DIMM modules on the board. Feh.
  222. */
  223. if (spd.mem_type == SPD_MEMTYPE_DDR) {
  224. n_ranks = spd.nrows;
  225. } else {
  226. n_ranks = (spd.nrows & 0x7) + 1;
  227. }
  228. debug("DDR: number of ranks = %d\n", n_ranks);
  229. if (n_ranks > 2) {
  230. printf("DDR: Only 2 chip selects are supported: %d\n",
  231. n_ranks);
  232. return 0;
  233. }
  234. /*
  235. * Adjust DDR II IO voltage biasing. It just makes it work.
  236. */
  237. if (spd.mem_type == SPD_MEMTYPE_DDR2) {
  238. gur->ddrioovcr = (0
  239. | 0x80000000 /* Enable */
  240. | 0x10000000 /* VSEL to 1.8V */
  241. );
  242. }
  243. /*
  244. * Determine the size of each Rank in bytes.
  245. */
  246. rank_density = compute_banksize(spd.mem_type, spd.row_dens);
  247. debug("Start address for this controller is 0x%08lx\n", start_addr);
  248. /*
  249. * ODT configuration recommendation from DDR Controller Chapter.
  250. */
  251. odt_rd_cfg = 0; /* Never assert ODT */
  252. odt_wr_cfg = 0; /* Never assert ODT */
  253. if (spd.mem_type == SPD_MEMTYPE_DDR2) {
  254. odt_wr_cfg = 1; /* Assert ODT on writes to CS0 */
  255. }
  256. #ifdef CONFIG_DDR_INTERLEAVE
  257. if (dimm_num != 1) {
  258. printf("For interleaving memory on HPCN, need to use DIMM 1 for DDR Controller %d !\n", ddr_num);
  259. return 0;
  260. } else {
  261. /*
  262. * Since interleaved memory only uses CS0, the
  263. * memory sticks have to be identical in size and quantity
  264. * of ranks. That essentially gives double the size on
  265. * one rank, i.e on CS0 for both controllers put together.
  266. * Confirm this???
  267. */
  268. rank_density *= 2;
  269. /*
  270. * Eg: Bounds: 0x0000_0000 to 0x0f000_0000 first 256 Meg
  271. */
  272. start_addr = 0;
  273. ddr->cs0_bnds = (start_addr >> 8)
  274. | (((start_addr + rank_density - 1) >> 24));
  275. /*
  276. * Default interleaving mode to cache-line interleaving.
  277. */
  278. ddr->cs0_config = ( 1 << 31
  279. #if (CFG_PAGE_INTERLEAVING == 1)
  280. | (PAGE_INTERLEAVING)
  281. #elif (CFG_BANK_INTERLEAVING == 1)
  282. | (BANK_INTERLEAVING)
  283. #elif (CFG_SUPER_BANK_INTERLEAVING == 1)
  284. | (SUPER_BANK_INTERLEAVING)
  285. #else
  286. | (CACHE_LINE_INTERLEAVING)
  287. #endif
  288. | (odt_rd_cfg << 20)
  289. | (odt_wr_cfg << 16)
  290. | (spd.nrow_addr - 12) << 8
  291. | (spd.ncol_addr - 8) );
  292. debug("DDR: cs0_bnds = 0x%08x\n", ddr->cs0_bnds);
  293. debug("DDR: cs0_config = 0x%08x\n", ddr->cs0_config);
  294. /*
  295. * Adjustment for dual rank memory to get correct memory
  296. * size (return value of this function).
  297. */
  298. if (n_ranks == 2) {
  299. n_ranks = 1;
  300. rank_density /= 2;
  301. } else {
  302. rank_density /= 2;
  303. }
  304. }
  305. #else /* CONFIG_DDR_INTERLEAVE */
  306. if (dimm_num == 1) {
  307. /*
  308. * Eg: Bounds: 0x0000_0000 to 0x0f000_0000 first 256 Meg
  309. */
  310. ddr->cs0_bnds = (start_addr >> 8)
  311. | (((start_addr + rank_density - 1) >> 24));
  312. ddr->cs0_config = ( 1 << 31
  313. | (odt_rd_cfg << 20)
  314. | (odt_wr_cfg << 16)
  315. | (spd.nrow_addr - 12) << 8
  316. | (spd.ncol_addr - 8) );
  317. debug("DDR: cs0_bnds = 0x%08x\n", ddr->cs0_bnds);
  318. debug("DDR: cs0_config = 0x%08x\n", ddr->cs0_config);
  319. if (n_ranks == 2) {
  320. /*
  321. * Eg: Bounds: 0x1000_0000 to 0x1f00_0000,
  322. * second 256 Meg
  323. */
  324. ddr->cs1_bnds = (((start_addr + rank_density) >> 8)
  325. | (( start_addr + 2*rank_density - 1)
  326. >> 24));
  327. ddr->cs1_config = ( 1<<31
  328. | (odt_rd_cfg << 20)
  329. | (odt_wr_cfg << 16)
  330. | (spd.nrow_addr - 12) << 8
  331. | (spd.ncol_addr - 8) );
  332. debug("DDR: cs1_bnds = 0x%08x\n", ddr->cs1_bnds);
  333. debug("DDR: cs1_config = 0x%08x\n", ddr->cs1_config);
  334. }
  335. } else {
  336. /*
  337. * This is the 2nd DIMM slot for this controller
  338. */
  339. /*
  340. * Eg: Bounds: 0x0000_0000 to 0x0f000_0000 first 256 Meg
  341. */
  342. ddr->cs2_bnds = (start_addr >> 8)
  343. | (((start_addr + rank_density - 1) >> 24));
  344. ddr->cs2_config = ( 1 << 31
  345. | (odt_rd_cfg << 20)
  346. | (odt_wr_cfg << 16)
  347. | (spd.nrow_addr - 12) << 8
  348. | (spd.ncol_addr - 8) );
  349. debug("DDR: cs2_bnds = 0x%08x\n", ddr->cs2_bnds);
  350. debug("DDR: cs2_config = 0x%08x\n", ddr->cs2_config);
  351. if (n_ranks == 2) {
  352. /*
  353. * Eg: Bounds: 0x1000_0000 to 0x1f00_0000,
  354. * second 256 Meg
  355. */
  356. ddr->cs3_bnds = (((start_addr + rank_density) >> 8)
  357. | (( start_addr + 2*rank_density - 1)
  358. >> 24));
  359. ddr->cs3_config = ( 1<<31
  360. | (odt_rd_cfg << 20)
  361. | (odt_wr_cfg << 16)
  362. | (spd.nrow_addr - 12) << 8
  363. | (spd.ncol_addr - 8) );
  364. debug("DDR: cs3_bnds = 0x%08x\n", ddr->cs3_bnds);
  365. debug("DDR: cs3_config = 0x%08x\n", ddr->cs3_config);
  366. }
  367. }
  368. #endif /* CONFIG_DDR_INTERLEAVE */
  369. /*
  370. * Find the largest CAS by locating the highest 1 bit
  371. * in the spd.cas_lat field. Translate it to a DDR
  372. * controller field value:
  373. *
  374. * CAS Lat DDR I DDR II Ctrl
  375. * Clocks SPD Bit SPD Bit Value
  376. * ------- ------- ------- -----
  377. * 1.0 0 0001
  378. * 1.5 1 0010
  379. * 2.0 2 2 0011
  380. * 2.5 3 0100
  381. * 3.0 4 3 0101
  382. * 3.5 5 0110
  383. * 4.0 4 0111
  384. * 4.5 1000
  385. * 5.0 5 1001
  386. */
  387. caslat = __ilog2(spd.cas_lat);
  388. if ((spd.mem_type == SPD_MEMTYPE_DDR)
  389. && (caslat > 5)) {
  390. printf("DDR I: Invalid SPD CAS Latency: 0x%x.\n", spd.cas_lat);
  391. return 0;
  392. } else if (spd.mem_type == SPD_MEMTYPE_DDR2
  393. && (caslat < 2 || caslat > 5)) {
  394. printf("DDR II: Invalid SPD CAS Latency: 0x%x.\n",
  395. spd.cas_lat);
  396. return 0;
  397. }
  398. debug("DDR: caslat SPD bit is %d\n", caslat);
  399. /*
  400. * Calculate the Maximum Data Rate based on the Minimum Cycle time.
  401. * The SPD clk_cycle field (tCKmin) is measured in tenths of
  402. * nanoseconds and represented as BCD.
  403. */
  404. tCKmin_ps = convert_bcd_tenths_to_cycle_time_ps(spd.clk_cycle);
  405. debug("DDR: tCKmin = %d ps\n", tCKmin_ps);
  406. /*
  407. * Double-data rate, scaled 1000 to picoseconds, and back down to MHz.
  408. */
  409. max_data_rate = 2 * 1000 * 1000 / tCKmin_ps;
  410. debug("DDR: Module max data rate = %d Mhz\n", max_data_rate);
  411. /*
  412. * Adjust the CAS Latency to allow for bus speeds that
  413. * are slower than the DDR module.
  414. */
  415. busfreq = get_bus_freq(0) / 1000000; /* MHz */
  416. tCycle_ps = convert_bcd_tenths_to_cycle_time_ps(spd.clk_cycle3);
  417. modfreq = 2 * 1000 * 1000 / tCycle_ps;
  418. if ((spd.mem_type == SPD_MEMTYPE_DDR2) && (busfreq < 266)) {
  419. printf("DDR: platform frequency too low for correct DDR2 controller operation\n");
  420. return 0;
  421. } else if (busfreq < 90) {
  422. printf("DDR: platform frequency too low for correct DDR1 operation\n");
  423. return 0;
  424. }
  425. if ((busfreq <= modfreq) && (spd.cas_lat & (1 << (caslat - 2)))) {
  426. caslat -= 2;
  427. } else {
  428. tCycle_ps = convert_bcd_tenths_to_cycle_time_ps(spd.clk_cycle2);
  429. modfreq = 2 * 1000 * 1000 / tCycle_ps;
  430. if ((busfreq <= modfreq) && (spd.cas_lat & (1 << (caslat - 1))))
  431. caslat -= 1;
  432. else if (busfreq > max_data_rate) {
  433. printf("DDR: Bus freq %d MHz is not fit for DDR rate %d MHz\n",
  434. busfreq, max_data_rate);
  435. return 0;
  436. }
  437. }
  438. /*
  439. * Empirically set ~MCAS-to-preamble override for DDR 2.
  440. * Your milage will vary.
  441. */
  442. cpo = 0;
  443. if (spd.mem_type == SPD_MEMTYPE_DDR2) {
  444. if (busfreq <= 333) {
  445. cpo = 0x7;
  446. } else if (busfreq <= 400) {
  447. cpo = 0x9;
  448. } else {
  449. cpo = 0xa;
  450. }
  451. }
  452. /*
  453. * Convert caslat clocks to DDR controller value.
  454. * Force caslat_ctrl to be DDR Controller field-sized.
  455. */
  456. if (spd.mem_type == SPD_MEMTYPE_DDR) {
  457. caslat_ctrl = (caslat + 1) & 0x07;
  458. } else {
  459. caslat_ctrl = (2 * caslat - 1) & 0x0f;
  460. }
  461. debug("DDR: caslat SPD bit is %d, controller field is 0x%x\n",
  462. caslat, caslat_ctrl);
  463. /*
  464. * Timing Config 0.
  465. * Avoid writing for DDR I. The new PQ38 DDR controller
  466. * dreams up non-zero default values to be backwards compatible.
  467. */
  468. if (spd.mem_type == SPD_MEMTYPE_DDR2) {
  469. unsigned char taxpd_clk = 8; /* By the book. */
  470. unsigned char tmrd_clk = 2; /* By the book. */
  471. unsigned char act_pd_exit = 2; /* Empirical? */
  472. unsigned char pre_pd_exit = 6; /* Empirical? */
  473. ddr->timing_cfg_0 = (0
  474. | ((act_pd_exit & 0x7) << 20) /* ACT_PD_EXIT */
  475. | ((pre_pd_exit & 0x7) << 16) /* PRE_PD_EXIT */
  476. | ((taxpd_clk & 0xf) << 8) /* ODT_PD_EXIT */
  477. | ((tmrd_clk & 0xf) << 0) /* MRS_CYC */
  478. );
  479. debug("DDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0);
  480. }
  481. /*
  482. * Some Timing Config 1 values now.
  483. * Sneak Extended Refresh Recovery in here too.
  484. */
  485. /*
  486. * For DDR I, WRREC(Twr) and WRTORD(Twtr) are not in SPD,
  487. * use conservative value.
  488. * For DDR II, they are bytes 36 and 37, in quarter nanos.
  489. */
  490. if (spd.mem_type == SPD_MEMTYPE_DDR) {
  491. twr_clk = 3; /* Clocks */
  492. twtr_clk = 1; /* Clocks */
  493. } else {
  494. twr_clk = picos_to_clk(spd.twr * 250);
  495. twtr_clk = picos_to_clk(spd.twtr * 250);
  496. }
  497. /*
  498. * Calculate Trfc, in picos.
  499. * DDR I: Byte 42 straight up in ns.
  500. * DDR II: Byte 40 and 42 swizzled some, in ns.
  501. */
  502. if (spd.mem_type == SPD_MEMTYPE_DDR) {
  503. trfc = spd.trfc * 1000; /* up to ps */
  504. } else {
  505. unsigned int byte40_table_ps[8] = {
  506. 0,
  507. 250,
  508. 330,
  509. 500,
  510. 660,
  511. 750,
  512. 0,
  513. 0
  514. };
  515. trfc = (((spd.trctrfc_ext & 0x1) * 256) + spd.trfc) * 1000
  516. + byte40_table_ps[(spd.trctrfc_ext >> 1) & 0x7];
  517. }
  518. trfc_clk = picos_to_clk(trfc);
  519. /*
  520. * Trcd, Byte 29, from quarter nanos to ps and clocks.
  521. */
  522. trcd_clk = picos_to_clk(spd.trcd * 250) & 0x7;
  523. /*
  524. * Convert trfc_clk to DDR controller fields. DDR I should
  525. * fit in the REFREC field (16-19) of TIMING_CFG_1, but the
  526. * 8548 controller has an extended REFREC field of three bits.
  527. * The controller automatically adds 8 clocks to this value,
  528. * so preadjust it down 8 first before splitting it up.
  529. */
  530. trfc_low = (trfc_clk - 8) & 0xf;
  531. trfc_high = ((trfc_clk - 8) >> 4) & 0x3;
  532. /*
  533. * Sneak in some Extended Refresh Recovery.
  534. */
  535. ddr->ext_refrec = (trfc_high << 16);
  536. debug("DDR: ext_refrec = 0x%08x\n", ddr->ext_refrec);
  537. ddr->timing_cfg_1 =
  538. (0
  539. | ((picos_to_clk(spd.trp * 250) & 0x07) << 28) /* PRETOACT */
  540. | ((picos_to_clk(spd.tras * 1000) & 0x0f ) << 24) /* ACTTOPRE */
  541. | (trcd_clk << 20) /* ACTTORW */
  542. | (caslat_ctrl << 16) /* CASLAT */
  543. | (trfc_low << 12) /* REFEC */
  544. | ((twr_clk & 0x07) << 8) /* WRRREC */
  545. | ((picos_to_clk(spd.trrd * 250) & 0x07) << 4) /* ACTTOACT */
  546. | ((twtr_clk & 0x07) << 0) /* WRTORD */
  547. );
  548. debug("DDR: timing_cfg_1 = 0x%08x\n", ddr->timing_cfg_1);
  549. /*
  550. * Timing_Config_2
  551. * Was: 0x00000800;
  552. */
  553. /*
  554. * Additive Latency
  555. * For DDR I, 0.
  556. * For DDR II, with ODT enabled, use "a value" less than ACTTORW,
  557. * which comes from Trcd, and also note that:
  558. * add_lat + caslat must be >= 4
  559. */
  560. add_lat = 0;
  561. if (spd.mem_type == SPD_MEMTYPE_DDR2
  562. && (odt_wr_cfg || odt_rd_cfg)
  563. && (caslat < 4)) {
  564. add_lat = 4 - caslat;
  565. if (add_lat >= trcd_clk) {
  566. add_lat = trcd_clk - 1;
  567. }
  568. }
  569. /*
  570. * Write Data Delay
  571. * Historically 0x2 == 4/8 clock delay.
  572. * Empirically, 0x3 == 6/8 clock delay is suggested for DDR I 266.
  573. */
  574. wr_data_delay = 3;
  575. /*
  576. * Write Latency
  577. * Read to Precharge
  578. * Minimum CKE Pulse Width.
  579. * Four Activate Window
  580. */
  581. if (spd.mem_type == SPD_MEMTYPE_DDR) {
  582. /*
  583. * This is a lie. It should really be 1, but if it is
  584. * set to 1, bits overlap into the old controller's
  585. * otherwise unused ACSM field. If we leave it 0, then
  586. * the HW will magically treat it as 1 for DDR 1. Oh Yea.
  587. */
  588. wr_lat = 0;
  589. trtp_clk = 2; /* By the book. */
  590. cke_min_clk = 1; /* By the book. */
  591. four_act = 1; /* By the book. */
  592. } else {
  593. wr_lat = caslat - 1;
  594. /* Convert SPD value from quarter nanos to picos. */
  595. trtp_clk = picos_to_clk(spd.trtp * 250);
  596. cke_min_clk = 3; /* By the book. */
  597. four_act = picos_to_clk(37500); /* By the book. 1k pages? */
  598. }
  599. ddr->timing_cfg_2 = (0
  600. | ((add_lat & 0x7) << 28) /* ADD_LAT */
  601. | ((cpo & 0x1f) << 23) /* CPO */
  602. | ((wr_lat & 0x7) << 19) /* WR_LAT */
  603. | ((trtp_clk & 0x7) << 13) /* RD_TO_PRE */
  604. | ((wr_data_delay & 0x7) << 10) /* WR_DATA_DELAY */
  605. | ((cke_min_clk & 0x7) << 6) /* CKE_PLS */
  606. | ((four_act & 0x1f) << 0) /* FOUR_ACT */
  607. );
  608. debug("DDR: timing_cfg_2 = 0x%08x\n", ddr->timing_cfg_2);
  609. /*
  610. * Determine the Mode Register Set.
  611. *
  612. * This is nominally part specific, but it appears to be
  613. * consistent for all DDR I devices, and for all DDR II devices.
  614. *
  615. * caslat must be programmed
  616. * burst length is always 4
  617. * burst type is sequential
  618. *
  619. * For DDR I:
  620. * operating mode is "normal"
  621. *
  622. * For DDR II:
  623. * other stuff
  624. */
  625. mode_caslat = 0;
  626. /*
  627. * Table lookup from DDR I or II Device Operation Specs.
  628. */
  629. if (spd.mem_type == SPD_MEMTYPE_DDR) {
  630. if (1 <= caslat && caslat <= 4) {
  631. unsigned char mode_caslat_table[4] = {
  632. 0x5, /* 1.5 clocks */
  633. 0x2, /* 2.0 clocks */
  634. 0x6, /* 2.5 clocks */
  635. 0x3 /* 3.0 clocks */
  636. };
  637. mode_caslat = mode_caslat_table[caslat - 1];
  638. } else {
  639. puts("DDR I: Only CAS Latencies of 1.5, 2.0, "
  640. "2.5 and 3.0 clocks are supported.\n");
  641. return 0;
  642. }
  643. } else {
  644. if (2 <= caslat && caslat <= 5) {
  645. mode_caslat = caslat;
  646. } else {
  647. puts("DDR II: Only CAS Latencies of 2.0, 3.0, "
  648. "4.0 and 5.0 clocks are supported.\n");
  649. return 0;
  650. }
  651. }
  652. /*
  653. * Encoded Burst Length of 4.
  654. */
  655. burst_len = 2; /* Fiat. */
  656. if (spd.mem_type == SPD_MEMTYPE_DDR) {
  657. twr_auto_clk = 0; /* Historical */
  658. } else {
  659. /*
  660. * Determine tCK max in picos. Grab tWR and convert to picos.
  661. * Auto-precharge write recovery is:
  662. * WR = roundup(tWR_ns/tCKmax_ns).
  663. *
  664. * Ponder: Is twr_auto_clk different than twr_clk?
  665. */
  666. tCKmax_ps = convert_bcd_tenths_to_cycle_time_ps(spd.tckmax);
  667. twr_auto_clk = (spd.twr * 250 + tCKmax_ps - 1) / tCKmax_ps;
  668. }
  669. /*
  670. * Mode Reg in bits 16 ~ 31,
  671. * Extended Mode Reg 1 in bits 0 ~ 15.
  672. */
  673. mode_odt_enable = 0x0; /* Default disabled */
  674. if (odt_wr_cfg || odt_rd_cfg) {
  675. /*
  676. * Bits 6 and 2 in Extended MRS(1)
  677. * Bit 2 == 0x04 == 75 Ohm, with 2 DIMM modules.
  678. * Bit 6 == 0x40 == 150 Ohm, with 1 DIMM module.
  679. */
  680. mode_odt_enable = 0x40; /* 150 Ohm */
  681. }
  682. ddr->sdram_mode_1 =
  683. (0
  684. | (add_lat << (16 + 3)) /* Additive Latency in EMRS1 */
  685. | (mode_odt_enable << 16) /* ODT Enable in EMRS1 */
  686. | (twr_auto_clk << 9) /* Write Recovery Autopre */
  687. | (mode_caslat << 4) /* caslat */
  688. | (burst_len << 0) /* Burst length */
  689. );
  690. debug("DDR: sdram_mode = 0x%08x\n", ddr->sdram_mode_1);
  691. /*
  692. * Clear EMRS2 and EMRS3.
  693. */
  694. ddr->sdram_mode_2 = 0;
  695. debug("DDR: sdram_mode_2 = 0x%08x\n", ddr->sdram_mode_2);
  696. /*
  697. * Determine Refresh Rate. Ignore self refresh bit on DDR I.
  698. * Table from SPD Spec, Byte 12, converted to picoseconds and
  699. * filled in with "default" normal values.
  700. */
  701. {
  702. unsigned int refresh_clk;
  703. unsigned int refresh_time_ns[8] = {
  704. 15625000, /* 0 Normal 1.00x */
  705. 3900000, /* 1 Reduced .25x */
  706. 7800000, /* 2 Extended .50x */
  707. 31300000, /* 3 Extended 2.00x */
  708. 62500000, /* 4 Extended 4.00x */
  709. 125000000, /* 5 Extended 8.00x */
  710. 15625000, /* 6 Normal 1.00x filler */
  711. 15625000, /* 7 Normal 1.00x filler */
  712. };
  713. refresh_clk = picos_to_clk(refresh_time_ns[spd.refresh & 0x7]);
  714. /*
  715. * Set BSTOPRE to 0x100 for page mode
  716. * If auto-charge is used, set BSTOPRE = 0
  717. */
  718. ddr->sdram_interval =
  719. (0
  720. | (refresh_clk & 0x3fff) << 16
  721. | 0x100
  722. );
  723. debug("DDR: sdram_interval = 0x%08x\n", ddr->sdram_interval);
  724. }
  725. /*
  726. * Is this an ECC DDR chip?
  727. * But don't mess with it if the DDR controller will init mem.
  728. */
  729. #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
  730. if (spd.config == 0x02) {
  731. ddr->err_disable = 0x0000000d;
  732. ddr->err_sbe = 0x00ff0000;
  733. }
  734. debug("DDR: err_disable = 0x%08x\n", ddr->err_disable);
  735. debug("DDR: err_sbe = 0x%08x\n", ddr->err_sbe);
  736. #endif
  737. asm volatile("sync;isync");
  738. udelay(500);
  739. /*
  740. * SDRAM Cfg 2
  741. */
  742. /*
  743. * When ODT is enabled, Chap 9 suggests asserting ODT to
  744. * internal IOs only during reads.
  745. */
  746. odt_cfg = 0;
  747. if (odt_rd_cfg | odt_wr_cfg) {
  748. odt_cfg = 0x2; /* ODT to IOs during reads */
  749. }
  750. /*
  751. * Try to use differential DQS with DDR II.
  752. */
  753. if (spd.mem_type == SPD_MEMTYPE_DDR) {
  754. dqs_cfg = 0; /* No Differential DQS for DDR I */
  755. } else {
  756. dqs_cfg = 0x1; /* Differential DQS for DDR II */
  757. }
  758. #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
  759. /*
  760. * Use the DDR controller to auto initialize memory.
  761. */
  762. d_init = 1;
  763. ddr->sdram_data_init = CONFIG_MEM_INIT_VALUE;
  764. debug("DDR: ddr_data_init = 0x%08x\n", ddr->sdram_data_init);
  765. #else
  766. /*
  767. * Memory will be initialized via DMA, or not at all.
  768. */
  769. d_init = 0;
  770. #endif
  771. ddr->sdram_cfg_2 = (0
  772. | (dqs_cfg << 26) /* Differential DQS */
  773. | (odt_cfg << 21) /* ODT */
  774. | (d_init << 4) /* D_INIT auto init DDR */
  775. );
  776. debug("DDR: sdram_cfg_2 = 0x%08x\n", ddr->sdram_cfg_2);
  777. #ifdef MPC86xx_DDR_SDRAM_CLK_CNTL
  778. {
  779. unsigned char clk_adjust;
  780. /*
  781. * Setup the clock control.
  782. * SDRAM_CLK_CNTL[0] = Source synchronous enable == 1
  783. * SDRAM_CLK_CNTL[5-7] = Clock Adjust
  784. * 0110 3/4 cycle late
  785. * 0111 7/8 cycle late
  786. */
  787. if (spd.mem_type == SPD_MEMTYPE_DDR) {
  788. clk_adjust = 0x6;
  789. } else {
  790. clk_adjust = 0x7;
  791. }
  792. ddr->sdram_clk_cntl = (0
  793. | 0x80000000
  794. | (clk_adjust << 23)
  795. );
  796. debug("DDR: sdram_clk_cntl = 0x%08x\n", ddr->sdram_clk_cntl);
  797. }
  798. #endif
  799. /*
  800. * Figure out memory size in Megabytes.
  801. */
  802. debug("# ranks = %d, rank_density = 0x%08lx\n", n_ranks, rank_density);
  803. memsize = n_ranks * rank_density / 0x100000;
  804. return memsize;
  805. }
  806. unsigned int enable_ddr(unsigned int ddr_num)
  807. {
  808. volatile immap_t *immap = (immap_t *)CFG_IMMR;
  809. spd_eeprom_t spd1,spd2;
  810. volatile ccsr_ddr_t *ddr;
  811. unsigned sdram_cfg_1;
  812. unsigned char sdram_type, mem_type, config, mod_attr;
  813. unsigned char d_init;
  814. unsigned int no_dimm1=0, no_dimm2=0;
  815. /* Set up pointer to enable the current ddr controller */
  816. if (ddr_num == 1)
  817. ddr = &immap->im_ddr1;
  818. else
  819. ddr = &immap->im_ddr2;
  820. /*
  821. * Read both dimm slots and decide whether
  822. * or not to enable this controller.
  823. */
  824. memset((void *)&spd1,0,sizeof(spd1));
  825. memset((void *)&spd2,0,sizeof(spd2));
  826. if (ddr_num == 1) {
  827. CFG_READ_SPD(SPD_EEPROM_ADDRESS1,
  828. 0, 1, (uchar *) &spd1, sizeof(spd1));
  829. CFG_READ_SPD(SPD_EEPROM_ADDRESS2,
  830. 0, 1, (uchar *) &spd2, sizeof(spd2));
  831. } else {
  832. CFG_READ_SPD(SPD_EEPROM_ADDRESS3,
  833. 0, 1, (uchar *) &spd1, sizeof(spd1));
  834. CFG_READ_SPD(SPD_EEPROM_ADDRESS4,
  835. 0, 1, (uchar *) &spd2, sizeof(spd2));
  836. }
  837. /*
  838. * Check for supported memory module types.
  839. */
  840. if (spd1.mem_type != SPD_MEMTYPE_DDR
  841. && spd1.mem_type != SPD_MEMTYPE_DDR2) {
  842. no_dimm1 = 1;
  843. } else {
  844. debug("\nFound memory of type 0x%02lx ",spd1.mem_type );
  845. if (spd1.mem_type == SPD_MEMTYPE_DDR)
  846. debug("DDR I\n");
  847. else
  848. debug("DDR II\n");
  849. }
  850. if (spd2.mem_type != SPD_MEMTYPE_DDR &&
  851. spd2.mem_type != SPD_MEMTYPE_DDR2) {
  852. no_dimm2 = 1;
  853. } else {
  854. debug("\nFound memory of type 0x%02lx ",spd2.mem_type );
  855. if (spd2.mem_type == SPD_MEMTYPE_DDR)
  856. debug("DDR I\n");
  857. else
  858. debug("DDR II\n");
  859. }
  860. #ifdef CONFIG_DDR_INTERLEAVE
  861. if (no_dimm1) {
  862. printf("For interleaved operation memory modules need to be present in CS0 DIMM slots of both DDR controllers!\n");
  863. return 0;
  864. }
  865. #endif
  866. /*
  867. * Memory is not present in DIMM1 and DIMM2 - so do not enable DDRn
  868. */
  869. if (no_dimm1 && no_dimm2) {
  870. printf("No memory modules found for DDR controller %d!!\n", ddr_num);
  871. return 0;
  872. } else {
  873. mem_type = no_dimm2 ? spd1.mem_type : spd2.mem_type;
  874. /*
  875. * Figure out the settings for the sdram_cfg register.
  876. * Build up the entire register in 'sdram_cfg' before
  877. * writing since the write into the register will
  878. * actually enable the memory controller; all settings
  879. * must be done before enabling.
  880. *
  881. * sdram_cfg[0] = 1 (ddr sdram logic enable)
  882. * sdram_cfg[1] = 1 (self-refresh-enable)
  883. * sdram_cfg[5:7] = (SDRAM type = DDR SDRAM)
  884. * 010 DDR 1 SDRAM
  885. * 011 DDR 2 SDRAM
  886. */
  887. sdram_type = (mem_type == SPD_MEMTYPE_DDR) ? 2 : 3;
  888. sdram_cfg_1 = (0
  889. | (1 << 31) /* Enable */
  890. | (1 << 30) /* Self refresh */
  891. | (sdram_type << 24) /* SDRAM type */
  892. );
  893. /*
  894. * sdram_cfg[3] = RD_EN - registered DIMM enable
  895. * A value of 0x26 indicates micron registered
  896. * DIMMS (micron.com)
  897. */
  898. mod_attr = no_dimm2 ? spd1.mod_attr : spd2.mod_attr;
  899. if (mem_type == SPD_MEMTYPE_DDR && mod_attr == 0x26) {
  900. sdram_cfg_1 |= 0x10000000; /* RD_EN */
  901. }
  902. #if defined(CONFIG_DDR_ECC)
  903. config = no_dimm2 ? spd1.config : spd2.config;
  904. /*
  905. * If the user wanted ECC (enabled via sdram_cfg[2])
  906. */
  907. if (config == 0x02) {
  908. ddr->err_disable = 0x00000000;
  909. asm volatile("sync;isync;");
  910. ddr->err_sbe = 0x00ff0000;
  911. ddr->err_int_en = 0x0000000d;
  912. sdram_cfg_1 |= 0x20000000; /* ECC_EN */
  913. }
  914. #endif
  915. /*
  916. * Set 1T or 2T timing based on 1 or 2 modules
  917. */
  918. {
  919. if (!(no_dimm1 || no_dimm2)) {
  920. /*
  921. * 2T timing,because both DIMMS are present.
  922. * Enable 2T timing by setting sdram_cfg[16].
  923. */
  924. sdram_cfg_1 |= 0x8000; /* 2T_EN */
  925. }
  926. }
  927. /*
  928. * 200 painful micro-seconds must elapse between
  929. * the DDR clock setup and the DDR config enable.
  930. */
  931. udelay(200);
  932. /*
  933. * Go!
  934. */
  935. ddr->sdram_cfg_1 = sdram_cfg_1;
  936. asm volatile("sync;isync");
  937. udelay(500);
  938. debug("DDR: sdram_cfg = 0x%08x\n", ddr->sdram_cfg_1);
  939. #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
  940. d_init = 1;
  941. debug("DDR: memory initializing\n");
  942. /*
  943. * Poll until memory is initialized.
  944. * 512 Meg at 400 might hit this 200 times or so.
  945. */
  946. while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
  947. udelay(1000);
  948. }
  949. debug("DDR: memory initialized\n\n");
  950. #endif
  951. debug("Enabled DDR Controller %d\n", ddr_num);
  952. return 1;
  953. }
  954. }
  955. long int
  956. spd_sdram(void)
  957. {
  958. int memsize_ddr1_dimm1 = 0;
  959. int memsize_ddr1_dimm2 = 0;
  960. int memsize_ddr2_dimm1 = 0;
  961. int memsize_ddr2_dimm2 = 0;
  962. int memsize_total = 0;
  963. int memsize_ddr1 = 0;
  964. int memsize_ddr2 = 0;
  965. unsigned int ddr1_enabled = 0;
  966. unsigned int ddr2_enabled = 0;
  967. unsigned int law_size_ddr1;
  968. unsigned int law_size_ddr2;
  969. volatile immap_t *immap = (immap_t *)CFG_IMMR;
  970. volatile ccsr_ddr_t *ddr1 = &immap->im_ddr1;
  971. volatile ccsr_ddr_t *ddr2 = &immap->im_ddr2;
  972. volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm;
  973. #ifdef CONFIG_DDR_INTERLEAVE
  974. unsigned int law_size_interleaved;
  975. memsize_ddr1_dimm1 = spd_init(SPD_EEPROM_ADDRESS1,
  976. 1, 1,
  977. (unsigned int)memsize_total * 1024*1024);
  978. memsize_total += memsize_ddr1_dimm1;
  979. memsize_ddr2_dimm1 = spd_init(SPD_EEPROM_ADDRESS3,
  980. 2, 1,
  981. (unsigned int)memsize_total * 1024*1024);
  982. memsize_total += memsize_ddr2_dimm1;
  983. if (memsize_ddr1_dimm1 != memsize_ddr2_dimm1) {
  984. if (memsize_ddr1_dimm1 < memsize_ddr2_dimm1)
  985. memsize_total -= memsize_ddr1_dimm1;
  986. else
  987. memsize_total -= memsize_ddr2_dimm1;
  988. debug("Total memory available for interleaving 0x%08lx\n",
  989. memsize_total * 1024 * 1024);
  990. debug("Adjusting CS0_BNDS to account for unequal DIMM sizes in interleaved memory\n");
  991. ddr1->cs0_bnds = ((memsize_total * 1024 * 1024) - 1) >> 24;
  992. ddr2->cs0_bnds = ((memsize_total * 1024 * 1024) - 1) >> 24;
  993. debug("DDR1: cs0_bnds = 0x%08x\n", ddr1->cs0_bnds);
  994. debug("DDR2: cs0_bnds = 0x%08x\n", ddr2->cs0_bnds);
  995. }
  996. ddr1_enabled = enable_ddr(1);
  997. ddr2_enabled = enable_ddr(2);
  998. /*
  999. * Both controllers need to be enabled for interleaving.
  1000. */
  1001. if (ddr1_enabled && ddr2_enabled) {
  1002. law_size_interleaved = 19 + __ilog2(memsize_total);
  1003. /*
  1004. * Set up LAWBAR for DDR 1 space.
  1005. */
  1006. mcm->lawbar1 = ((CFG_DDR_SDRAM_BASE >> 12) & 0xfffff);
  1007. mcm->lawar1 = (LAWAR_EN
  1008. | LAWAR_TRGT_IF_DDR_INTERLEAVED
  1009. | (LAWAR_SIZE & law_size_interleaved));
  1010. debug("DDR: LAWBAR1=0x%08x\n", mcm->lawbar1);
  1011. debug("DDR: LAWAR1=0x%08x\n", mcm->lawar1);
  1012. debug("Interleaved memory size is 0x%08lx\n", memsize_total);
  1013. #ifdef CONFIG_DDR_INTERLEAVE
  1014. #if (CFG_PAGE_INTERLEAVING == 1)
  1015. printf("Page ");
  1016. #elif (CFG_BANK_INTERLEAVING == 1)
  1017. printf("Bank ");
  1018. #elif (CFG_SUPER_BANK_INTERLEAVING == 1)
  1019. printf("Super-bank ");
  1020. #else
  1021. printf("Cache-line ");
  1022. #endif
  1023. #endif
  1024. printf("Interleaved");
  1025. return memsize_total * 1024 * 1024;
  1026. } else {
  1027. printf("Interleaved memory not enabled - check CS0 DIMM slots for both controllers.\n");
  1028. return 0;
  1029. }
  1030. #else
  1031. /*
  1032. * Call spd_sdram() routine to init ddr1 - pass I2c address,
  1033. * controller number, dimm number, and starting address.
  1034. */
  1035. memsize_ddr1_dimm1 = spd_init(SPD_EEPROM_ADDRESS1,
  1036. 1, 1,
  1037. (unsigned int)memsize_total * 1024*1024);
  1038. memsize_total += memsize_ddr1_dimm1;
  1039. memsize_ddr1_dimm2 = spd_init(SPD_EEPROM_ADDRESS2,
  1040. 1, 2,
  1041. (unsigned int)memsize_total * 1024*1024);
  1042. memsize_total += memsize_ddr1_dimm2;
  1043. /*
  1044. * Enable the DDR controller - pass ddr controller number.
  1045. */
  1046. ddr1_enabled = enable_ddr(1);
  1047. /* Keep track of memory to be addressed by DDR1 */
  1048. memsize_ddr1 = memsize_ddr1_dimm1 + memsize_ddr1_dimm2;
  1049. /*
  1050. * First supported LAW size is 16M, at LAWAR_SIZE_16M == 23. Fnord.
  1051. */
  1052. if (ddr1_enabled) {
  1053. law_size_ddr1 = 19 + __ilog2(memsize_ddr1);
  1054. /*
  1055. * Set up LAWBAR for DDR 1 space.
  1056. */
  1057. mcm->lawbar1 = ((CFG_DDR_SDRAM_BASE >> 12) & 0xfffff);
  1058. mcm->lawar1 = (LAWAR_EN
  1059. | LAWAR_TRGT_IF_DDR1
  1060. | (LAWAR_SIZE & law_size_ddr1));
  1061. debug("DDR: LAWBAR1=0x%08x\n", mcm->lawbar1);
  1062. debug("DDR: LAWAR1=0x%08x\n", mcm->lawar1);
  1063. }
  1064. #if (CONFIG_NUM_DDR_CONTROLLERS > 1)
  1065. memsize_ddr2_dimm1 = spd_init(SPD_EEPROM_ADDRESS3,
  1066. 2, 1,
  1067. (unsigned int)memsize_total * 1024*1024);
  1068. memsize_total += memsize_ddr2_dimm1;
  1069. memsize_ddr2_dimm2 = spd_init(SPD_EEPROM_ADDRESS4,
  1070. 2, 2,
  1071. (unsigned int)memsize_total * 1024*1024);
  1072. memsize_total += memsize_ddr2_dimm2;
  1073. ddr2_enabled = enable_ddr(2);
  1074. /* Keep track of memory to be addressed by DDR2 */
  1075. memsize_ddr2 = memsize_ddr2_dimm1 + memsize_ddr2_dimm2;
  1076. if (ddr2_enabled) {
  1077. law_size_ddr2 = 19 + __ilog2(memsize_ddr2);
  1078. /*
  1079. * Set up LAWBAR for DDR 2 space.
  1080. */
  1081. if (ddr1_enabled)
  1082. mcm->lawbar8 = (((memsize_ddr1 * 1024 * 1024) >> 12)
  1083. & 0xfffff);
  1084. else
  1085. mcm->lawbar8 = ((CFG_DDR_SDRAM_BASE >> 12) & 0xfffff);
  1086. mcm->lawar8 = (LAWAR_EN
  1087. | LAWAR_TRGT_IF_DDR2
  1088. | (LAWAR_SIZE & law_size_ddr2));
  1089. debug("\nDDR: LAWBAR8=0x%08x\n", mcm->lawbar8);
  1090. debug("DDR: LAWAR8=0x%08x\n", mcm->lawar8);
  1091. }
  1092. #endif /* CONFIG_NUM_DDR_CONTROLLERS > 1 */
  1093. debug("\nMemory sizes are DDR1 = 0x%08lx, DDR2 = 0x%08lx\n",
  1094. memsize_ddr1, memsize_ddr2);
  1095. /*
  1096. * If neither DDR controller is enabled return 0.
  1097. */
  1098. if (!ddr1_enabled && !ddr2_enabled)
  1099. return 0;
  1100. else {
  1101. printf("Non-interleaved");
  1102. return memsize_total * 1024 * 1024;
  1103. }
  1104. #endif /* CONFIG_DDR_INTERLEAVE */
  1105. }
  1106. #endif /* CONFIG_SPD_EEPROM */
  1107. #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
  1108. /*
  1109. * Initialize all of memory for ECC, then enable errors.
  1110. */
  1111. void
  1112. ddr_enable_ecc(unsigned int dram_size)
  1113. {
  1114. uint *p = 0;
  1115. uint i = 0;
  1116. volatile immap_t *immap = (immap_t *)CFG_IMMR;
  1117. volatile ccsr_ddr_t *ddr1= &immap->im_ddr1;
  1118. dma_init();
  1119. for (*p = 0; p < (uint *)(8 * 1024); p++) {
  1120. if (((unsigned int)p & 0x1f) == 0) {
  1121. ppcDcbz((unsigned long) p);
  1122. }
  1123. *p = (unsigned int)CONFIG_MEM_INIT_VALUE;
  1124. if (((unsigned int)p & 0x1c) == 0x1c) {
  1125. ppcDcbf((unsigned long) p);
  1126. }
  1127. }
  1128. /* 8K */
  1129. dma_xfer((uint *)0x2000, 0x2000, (uint *)0);
  1130. /* 16K */
  1131. dma_xfer((uint *)0x4000, 0x4000, (uint *)0);
  1132. /* 32K */
  1133. dma_xfer((uint *)0x8000, 0x8000, (uint *)0);
  1134. /* 64K */
  1135. dma_xfer((uint *)0x10000, 0x10000, (uint *)0);
  1136. /* 128k */
  1137. dma_xfer((uint *)0x20000, 0x20000, (uint *)0);
  1138. /* 256k */
  1139. dma_xfer((uint *)0x40000, 0x40000, (uint *)0);
  1140. /* 512k */
  1141. dma_xfer((uint *)0x80000, 0x80000, (uint *)0);
  1142. /* 1M */
  1143. dma_xfer((uint *)0x100000, 0x100000, (uint *)0);
  1144. /* 2M */
  1145. dma_xfer((uint *)0x200000, 0x200000, (uint *)0);
  1146. /* 4M */
  1147. dma_xfer((uint *)0x400000, 0x400000, (uint *)0);
  1148. for (i = 1; i < dram_size / 0x800000; i++) {
  1149. dma_xfer((uint *)(0x800000*i), 0x800000, (uint *)0);
  1150. }
  1151. /*
  1152. * Enable errors for ECC.
  1153. */
  1154. debug("DMA DDR: err_disable = 0x%08x\n", ddr1->err_disable);
  1155. ddr1->err_disable = 0x00000000;
  1156. asm volatile("sync;isync");
  1157. debug("DMA DDR: err_disable = 0x%08x\n", ddr1->err_disable);
  1158. }
  1159. #endif /* CONFIG_DDR_ECC && ! CONFIG_ECC_INIT_VIA_DDRCONTROLLER */