pirq_routing.h 4.6 KB

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  1. /*
  2. * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
  3. *
  4. * Ported from coreboot src/arch/x86/include/arch/pirq_routing.h
  5. *
  6. * SPDX-License-Identifier: GPL-2.0+
  7. */
  8. #ifndef _PIRQ_ROUTING_H_
  9. #define _PIRQ_ROUTING_H_
  10. /*
  11. * This is the maximum number on interrupt entries that a PCI device may have.
  12. * This is NOT the number of slots or devices in the system
  13. * This is NOT the number of entries in the PIRQ table
  14. *
  15. * This tells us that in the PIRQ table, we are going to have 4 link-bitmap
  16. * entries per PCI device which is fixed at 4: INTA, INTB, INTC, and INTD.
  17. *
  18. * CAUTION: If you change this, PIRQ routing will not work correctly.
  19. */
  20. #define MAX_INTX_ENTRIES 4
  21. #define PIRQ_SIGNATURE \
  22. (('$' << 0) + ('P' << 8) + ('I' << 16) + ('R' << 24))
  23. #define PIRQ_VERSION 0x0100
  24. struct __packed irq_info {
  25. u8 bus; /* Bus number */
  26. u8 devfn; /* Device and function number */
  27. struct __packed {
  28. u8 link; /* IRQ line ID, 0=not routed */
  29. u16 bitmap; /* Available IRQs */
  30. } irq[MAX_INTX_ENTRIES];
  31. u8 slot; /* Slot number, 0=onboard */
  32. u8 rfu;
  33. };
  34. struct __packed irq_routing_table {
  35. u32 signature; /* PIRQ_SIGNATURE */
  36. u16 version; /* PIRQ_VERSION */
  37. u16 size; /* Table size in bytes */
  38. u8 rtr_bus; /* busno of the interrupt router */
  39. u8 rtr_devfn; /* devfn of the interrupt router */
  40. u16 exclusive_irqs; /* IRQs devoted exclusively to PCI usage */
  41. u16 rtr_vendor; /* Vendor ID of the interrupt router */
  42. u16 rtr_device; /* Device ID of the interrupt router */
  43. u32 miniport_data;
  44. u8 rfu[11];
  45. u8 checksum; /* Modulo 256 checksum must give zero */
  46. struct irq_info slots[CONFIG_IRQ_SLOT_COUNT];
  47. };
  48. /**
  49. * get_irq_slot_count() - Get the number of entries in the irq_info table
  50. *
  51. * This calculates the number of entries for the irq_info table.
  52. *
  53. * @rt: pointer to the base address of the struct irq_info
  54. * @return: number of entries
  55. */
  56. static inline int get_irq_slot_count(struct irq_routing_table *rt)
  57. {
  58. return (rt->size - 32) / sizeof(struct irq_info);
  59. }
  60. /**
  61. * pirq_check_irq_routed() - Check whether an IRQ is routed to 8259 PIC
  62. *
  63. * This function checks whether an IRQ is routed to 8259 PIC for a given link.
  64. *
  65. * Note: this function should be provided by the platform codes, as the
  66. * implementation of interrupt router may be different.
  67. *
  68. * @link: link number which represents a PIRQ
  69. * @irq: the 8259 IRQ number
  70. * @return: true if the irq is already routed to 8259 for a given link,
  71. * false elsewise
  72. */
  73. bool pirq_check_irq_routed(int link, u8 irq);
  74. /**
  75. * pirq_translate_link() - Translate a link value
  76. *
  77. * This function translates a platform-specific link value to a link number.
  78. * On Intel platforms, the link value is normally a offset into the PCI
  79. * configuration space into the legacy bridge.
  80. *
  81. * Note: this function should be provided by the platform codes, as the
  82. * implementation of interrupt router may be different.
  83. *
  84. * @link: platform-specific link value
  85. * @return: link number which represents a PIRQ
  86. */
  87. int pirq_translate_link(int link);
  88. /**
  89. * pirq_assign_irq() - Assign an IRQ to a PIRQ link
  90. *
  91. * This function assigns the IRQ to a PIRQ link so that the PIRQ is routed to
  92. * the 8259 PIC.
  93. *
  94. * Note: this function should be provided by the platform codes, as the
  95. * implementation of interrupt router may be different.
  96. *
  97. * @link: link number which represents a PIRQ
  98. * @irq: IRQ to which the PIRQ is routed
  99. */
  100. void pirq_assign_irq(int link, u8 irq);
  101. /**
  102. * pirq_route_irqs() - Route PIRQs to 8259 PIC
  103. *
  104. * This function configures all PCI devices' interrupt pins and maps them to
  105. * PIRQs and finally 8259 PIC. The routed irq number is written to interrupt
  106. * line register in the configuration space of the PCI device for OS to use.
  107. * The configuration source is taken from a struct irq_info table, the format
  108. * of which is defined in PIRQ routing table spec and PCI BIOS spec.
  109. *
  110. * @irq: pointer to the base address of the struct irq_info
  111. * @num: number of entries in the struct irq_info
  112. */
  113. void pirq_route_irqs(struct irq_info *irq, int num);
  114. /**
  115. * copy_pirq_routing_table() - Copy a PIRQ routing table
  116. *
  117. * This helper function copies the given PIRQ routing table to a given address.
  118. * Before copying, it does several sanity tests against the PIRQ routing table.
  119. * It also fixes up the table checksum and align the given address to a 16 byte
  120. * boundary to meet the PIRQ routing table spec requirements.
  121. *
  122. * @addr: address to store the copied PIRQ routing table
  123. * @rt: pointer to the PIRQ routing table to copy from
  124. * @return: end address of the copied PIRQ routing table
  125. */
  126. u32 copy_pirq_routing_table(u32 addr, struct irq_routing_table *rt);
  127. #endif /* _PIRQ_ROUTING_H_ */