bmips_ram.c 3.9 KB

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  1. /*
  2. * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
  3. *
  4. * Derived from linux/arch/mips/bcm63xx/cpu.c:
  5. * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
  6. * Copyright (C) 2009 Florian Fainelli <florian@openwrt.org>
  7. *
  8. * SPDX-License-Identifier: GPL-2.0+
  9. */
  10. #include <common.h>
  11. #include <dm.h>
  12. #include <errno.h>
  13. #include <ram.h>
  14. #include <asm/io.h>
  15. #define SDRAM_CFG_REG 0x0
  16. #define SDRAM_CFG_COL_SHIFT 4
  17. #define SDRAM_CFG_COL_MASK (0x3 << SDRAM_CFG_COL_SHIFT)
  18. #define SDRAM_CFG_ROW_SHIFT 6
  19. #define SDRAM_CFG_ROW_MASK (0x3 << SDRAM_CFG_ROW_SHIFT)
  20. #define SDRAM_CFG_32B_SHIFT 10
  21. #define SDRAM_CFG_32B_MASK (1 << SDRAM_CFG_32B_SHIFT)
  22. #define SDRAM_CFG_BANK_SHIFT 13
  23. #define SDRAM_CFG_BANK_MASK (1 << SDRAM_CFG_BANK_SHIFT)
  24. #define MEMC_CFG_REG 0x4
  25. #define MEMC_CFG_32B_SHIFT 1
  26. #define MEMC_CFG_32B_MASK (1 << MEMC_CFG_32B_SHIFT)
  27. #define MEMC_CFG_COL_SHIFT 3
  28. #define MEMC_CFG_COL_MASK (0x3 << MEMC_CFG_COL_SHIFT)
  29. #define MEMC_CFG_ROW_SHIFT 6
  30. #define MEMC_CFG_ROW_MASK (0x3 << MEMC_CFG_ROW_SHIFT)
  31. #define DDR_CSEND_REG 0x8
  32. struct bmips_ram_priv;
  33. struct bmips_ram_hw {
  34. ulong (*get_ram_size)(struct bmips_ram_priv *);
  35. };
  36. struct bmips_ram_priv {
  37. void __iomem *regs;
  38. const struct bmips_ram_hw *hw;
  39. };
  40. static ulong bcm6328_get_ram_size(struct bmips_ram_priv *priv)
  41. {
  42. return readl_be(priv->regs + DDR_CSEND_REG) << 24;
  43. }
  44. static ulong bmips_dram_size(unsigned int cols, unsigned int rows,
  45. unsigned int is_32b, unsigned int banks)
  46. {
  47. rows += 11; /* 0 => 11 address bits ... 2 => 13 address bits */
  48. cols += 8; /* 0 => 8 address bits ... 2 => 10 address bits */
  49. is_32b += 1;
  50. return 1 << (cols + rows + is_32b + banks);
  51. }
  52. static ulong bcm6338_get_ram_size(struct bmips_ram_priv *priv)
  53. {
  54. unsigned int cols = 0, rows = 0, is_32b = 0, banks = 0;
  55. u32 val;
  56. val = readl_be(priv->regs + SDRAM_CFG_REG);
  57. rows = (val & SDRAM_CFG_ROW_MASK) >> SDRAM_CFG_ROW_SHIFT;
  58. cols = (val & SDRAM_CFG_COL_MASK) >> SDRAM_CFG_COL_SHIFT;
  59. is_32b = (val & SDRAM_CFG_32B_MASK) ? 1 : 0;
  60. banks = (val & SDRAM_CFG_BANK_MASK) ? 2 : 1;
  61. return bmips_dram_size(cols, rows, is_32b, banks);
  62. }
  63. static ulong bcm6358_get_ram_size(struct bmips_ram_priv *priv)
  64. {
  65. unsigned int cols = 0, rows = 0, is_32b = 0;
  66. u32 val;
  67. val = readl_be(priv->regs + MEMC_CFG_REG);
  68. rows = (val & MEMC_CFG_ROW_MASK) >> MEMC_CFG_ROW_SHIFT;
  69. cols = (val & MEMC_CFG_COL_MASK) >> MEMC_CFG_COL_SHIFT;
  70. is_32b = (val & MEMC_CFG_32B_MASK) ? 0 : 1;
  71. return bmips_dram_size(cols, rows, is_32b, 2);
  72. }
  73. static int bmips_ram_get_info(struct udevice *dev, struct ram_info *info)
  74. {
  75. struct bmips_ram_priv *priv = dev_get_priv(dev);
  76. const struct bmips_ram_hw *hw = priv->hw;
  77. info->base = 0x80000000;
  78. info->size = hw->get_ram_size(priv);
  79. return 0;
  80. }
  81. static const struct ram_ops bmips_ram_ops = {
  82. .get_info = bmips_ram_get_info,
  83. };
  84. static const struct bmips_ram_hw bmips_ram_bcm6328 = {
  85. .get_ram_size = bcm6328_get_ram_size,
  86. };
  87. static const struct bmips_ram_hw bmips_ram_bcm6338 = {
  88. .get_ram_size = bcm6338_get_ram_size,
  89. };
  90. static const struct bmips_ram_hw bmips_ram_bcm6358 = {
  91. .get_ram_size = bcm6358_get_ram_size,
  92. };
  93. static const struct udevice_id bmips_ram_ids[] = {
  94. {
  95. .compatible = "brcm,bcm6328-mc",
  96. .data = (ulong)&bmips_ram_bcm6328,
  97. }, {
  98. .compatible = "brcm,bcm6338-mc",
  99. .data = (ulong)&bmips_ram_bcm6338,
  100. }, {
  101. .compatible = "brcm,bcm6358-mc",
  102. .data = (ulong)&bmips_ram_bcm6358,
  103. }, { /* sentinel */ }
  104. };
  105. static int bmips_ram_probe(struct udevice *dev)
  106. {
  107. struct bmips_ram_priv *priv = dev_get_priv(dev);
  108. const struct bmips_ram_hw *hw =
  109. (const struct bmips_ram_hw *)dev_get_driver_data(dev);
  110. fdt_addr_t addr;
  111. fdt_size_t size;
  112. addr = devfdt_get_addr_size_index(dev, 0, &size);
  113. if (addr == FDT_ADDR_T_NONE)
  114. return -EINVAL;
  115. priv->regs = ioremap(addr, size);
  116. priv->hw = hw;
  117. return 0;
  118. }
  119. U_BOOT_DRIVER(bmips_ram) = {
  120. .name = "bmips-mc",
  121. .id = UCLASS_RAM,
  122. .of_match = bmips_ram_ids,
  123. .probe = bmips_ram_probe,
  124. .priv_auto_alloc_size = sizeof(struct bmips_ram_priv),
  125. .ops = &bmips_ram_ops,
  126. .flags = DM_FLAG_PRE_RELOC,
  127. };