pcie_layerscape_fixup.c 6.6 KB

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  1. /*
  2. * Copyright 2017 NXP
  3. * Copyright 2014-2015 Freescale Semiconductor, Inc.
  4. * Layerscape PCIe driver
  5. *
  6. * SPDX-License-Identifier: GPL-2.0+
  7. */
  8. #include <common.h>
  9. #include <pci.h>
  10. #include <asm/arch/fsl_serdes.h>
  11. #include <asm/io.h>
  12. #include <errno.h>
  13. #ifdef CONFIG_OF_BOARD_SETUP
  14. #include <libfdt.h>
  15. #include <fdt_support.h>
  16. #ifdef CONFIG_ARM
  17. #include <asm/arch/clock.h>
  18. #endif
  19. #include "pcie_layerscape.h"
  20. #if defined(CONFIG_FSL_LSCH3) || defined(CONFIG_FSL_LSCH2)
  21. /*
  22. * Return next available LUT index.
  23. */
  24. static int ls_pcie_next_lut_index(struct ls_pcie *pcie)
  25. {
  26. if (pcie->next_lut_index < PCIE_LUT_ENTRY_COUNT)
  27. return pcie->next_lut_index++;
  28. else
  29. return -ENOSPC; /* LUT is full */
  30. }
  31. /* returns the next available streamid for pcie, -errno if failed */
  32. static int ls_pcie_next_streamid(void)
  33. {
  34. static int next_stream_id = FSL_PEX_STREAM_ID_START;
  35. if (next_stream_id > FSL_PEX_STREAM_ID_END)
  36. return -EINVAL;
  37. return next_stream_id++;
  38. }
  39. static void lut_writel(struct ls_pcie *pcie, unsigned int value,
  40. unsigned int offset)
  41. {
  42. if (pcie->big_endian)
  43. out_be32(pcie->lut + offset, value);
  44. else
  45. out_le32(pcie->lut + offset, value);
  46. }
  47. /*
  48. * Program a single LUT entry
  49. */
  50. static void ls_pcie_lut_set_mapping(struct ls_pcie *pcie, int index, u32 devid,
  51. u32 streamid)
  52. {
  53. /* leave mask as all zeroes, want to match all bits */
  54. lut_writel(pcie, devid << 16, PCIE_LUT_UDR(index));
  55. lut_writel(pcie, streamid | PCIE_LUT_ENABLE, PCIE_LUT_LDR(index));
  56. }
  57. /*
  58. * An msi-map is a property to be added to the pci controller
  59. * node. It is a table, where each entry consists of 4 fields
  60. * e.g.:
  61. *
  62. * msi-map = <[devid] [phandle-to-msi-ctrl] [stream-id] [count]
  63. * [devid] [phandle-to-msi-ctrl] [stream-id] [count]>;
  64. */
  65. static void fdt_pcie_set_msi_map_entry(void *blob, struct ls_pcie *pcie,
  66. u32 devid, u32 streamid)
  67. {
  68. u32 *prop;
  69. u32 phandle;
  70. int nodeoffset;
  71. uint svr;
  72. char *compat = NULL;
  73. /* find pci controller node */
  74. nodeoffset = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie",
  75. pcie->dbi_res.start);
  76. if (nodeoffset < 0) {
  77. #ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
  78. svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
  79. if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
  80. svr == SVR_LS2048A || svr == SVR_LS2044A ||
  81. svr == SVR_LS2081A || svr == SVR_LS2041A)
  82. compat = "fsl,ls2088a-pcie";
  83. else
  84. compat = CONFIG_FSL_PCIE_COMPAT;
  85. if (compat)
  86. nodeoffset = fdt_node_offset_by_compat_reg(blob,
  87. compat, pcie->dbi_res.start);
  88. #endif
  89. if (nodeoffset < 0)
  90. return;
  91. }
  92. /* get phandle to MSI controller */
  93. prop = (u32 *)fdt_getprop(blob, nodeoffset, "msi-parent", 0);
  94. if (prop == NULL) {
  95. debug("\n%s: ERROR: missing msi-parent: PCIe%d\n",
  96. __func__, pcie->idx);
  97. return;
  98. }
  99. phandle = fdt32_to_cpu(*prop);
  100. /* set one msi-map row */
  101. fdt_appendprop_u32(blob, nodeoffset, "msi-map", devid);
  102. fdt_appendprop_u32(blob, nodeoffset, "msi-map", phandle);
  103. fdt_appendprop_u32(blob, nodeoffset, "msi-map", streamid);
  104. fdt_appendprop_u32(blob, nodeoffset, "msi-map", 1);
  105. }
  106. /*
  107. * An iommu-map is a property to be added to the pci controller
  108. * node. It is a table, where each entry consists of 4 fields
  109. * e.g.:
  110. *
  111. * iommu-map = <[devid] [phandle-to-iommu-ctrl] [stream-id] [count]
  112. * [devid] [phandle-to-iommu-ctrl] [stream-id] [count]>;
  113. */
  114. static void fdt_pcie_set_iommu_map_entry(void *blob, struct ls_pcie *pcie,
  115. u32 devid, u32 streamid)
  116. {
  117. u32 *prop;
  118. u32 iommu_map[4];
  119. int nodeoffset;
  120. int lenp;
  121. /* find pci controller node */
  122. nodeoffset = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie",
  123. pcie->dbi_res.start);
  124. if (nodeoffset < 0) {
  125. #ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
  126. nodeoffset = fdt_node_offset_by_compat_reg(blob,
  127. CONFIG_FSL_PCIE_COMPAT, pcie->dbi_res.start);
  128. if (nodeoffset < 0)
  129. return;
  130. #else
  131. return;
  132. #endif
  133. }
  134. /* get phandle to iommu controller */
  135. prop = fdt_getprop_w(blob, nodeoffset, "iommu-map", &lenp);
  136. if (prop == NULL) {
  137. debug("\n%s: ERROR: missing iommu-map: PCIe%d\n",
  138. __func__, pcie->idx);
  139. return;
  140. }
  141. /* set iommu-map row */
  142. iommu_map[0] = cpu_to_fdt32(devid);
  143. iommu_map[1] = *++prop;
  144. iommu_map[2] = cpu_to_fdt32(streamid);
  145. iommu_map[3] = cpu_to_fdt32(1);
  146. if (devid == 0) {
  147. fdt_setprop_inplace(blob, nodeoffset, "iommu-map",
  148. iommu_map, 16);
  149. } else {
  150. fdt_appendprop(blob, nodeoffset, "iommu-map", iommu_map, 16);
  151. }
  152. }
  153. static void fdt_fixup_pcie(void *blob)
  154. {
  155. struct udevice *dev, *bus;
  156. struct ls_pcie *pcie;
  157. int streamid;
  158. int index;
  159. pci_dev_t bdf;
  160. /* Scan all known buses */
  161. for (pci_find_first_device(&dev);
  162. dev;
  163. pci_find_next_device(&dev)) {
  164. for (bus = dev; device_is_on_pci_bus(bus);)
  165. bus = bus->parent;
  166. pcie = dev_get_priv(bus);
  167. streamid = ls_pcie_next_streamid();
  168. if (streamid < 0) {
  169. debug("ERROR: no stream ids free\n");
  170. continue;
  171. }
  172. index = ls_pcie_next_lut_index(pcie);
  173. if (index < 0) {
  174. debug("ERROR: no LUT indexes free\n");
  175. continue;
  176. }
  177. /* the DT fixup must be relative to the hose first_busno */
  178. bdf = dm_pci_get_bdf(dev) - PCI_BDF(bus->seq, 0, 0);
  179. /* map PCI b.d.f to streamID in LUT */
  180. ls_pcie_lut_set_mapping(pcie, index, bdf >> 8,
  181. streamid);
  182. /* update msi-map in device tree */
  183. fdt_pcie_set_msi_map_entry(blob, pcie, bdf >> 8,
  184. streamid);
  185. /* update iommu-map in device tree */
  186. fdt_pcie_set_iommu_map_entry(blob, pcie, bdf >> 8,
  187. streamid);
  188. }
  189. }
  190. #endif
  191. static void ft_pcie_ls_setup(void *blob, struct ls_pcie *pcie)
  192. {
  193. int off;
  194. uint svr;
  195. char *compat = NULL;
  196. off = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie",
  197. pcie->dbi_res.start);
  198. if (off < 0) {
  199. #ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
  200. svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
  201. if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
  202. svr == SVR_LS2048A || svr == SVR_LS2044A ||
  203. svr == SVR_LS2081A || svr == SVR_LS2041A)
  204. compat = "fsl,ls2088a-pcie";
  205. else
  206. compat = CONFIG_FSL_PCIE_COMPAT;
  207. if (compat)
  208. off = fdt_node_offset_by_compat_reg(blob,
  209. compat, pcie->dbi_res.start);
  210. #endif
  211. if (off < 0)
  212. return;
  213. }
  214. if (pcie->enabled)
  215. fdt_set_node_status(blob, off, FDT_STATUS_OKAY, 0);
  216. else
  217. fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
  218. }
  219. /* Fixup Kernel DT for PCIe */
  220. void ft_pci_setup(void *blob, bd_t *bd)
  221. {
  222. struct ls_pcie *pcie;
  223. list_for_each_entry(pcie, &ls_pcie_list, list)
  224. ft_pcie_ls_setup(blob, pcie);
  225. #if defined(CONFIG_FSL_LSCH3) || defined(CONFIG_FSL_LSCH2)
  226. fdt_fixup_pcie(blob);
  227. #endif
  228. }
  229. #else /* !CONFIG_OF_BOARD_SETUP */
  230. void ft_pci_setup(void *blob, bd_t *bd)
  231. {
  232. }
  233. #endif