clk-peripheral.c 2.4 KB

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  1. /*
  2. * Copyright (C) 2016 Atmel Corporation
  3. * Wenyou.Yang <wenyou.yang@atmel.com>
  4. *
  5. * SPDX-License-Identifier: GPL-2.0+
  6. */
  7. #include <common.h>
  8. #include <clk-uclass.h>
  9. #include <dm.h>
  10. #include <linux/io.h>
  11. #include <mach/at91_pmc.h>
  12. #include "pmc.h"
  13. #define PERIPHERAL_ID_MIN 2
  14. #define PERIPHERAL_ID_MAX 31
  15. #define PERIPHERAL_MASK(id) (1 << ((id) & PERIPHERAL_ID_MAX))
  16. enum periph_clk_type {
  17. CLK_PERIPH_AT91RM9200 = 0,
  18. CLK_PERIPH_AT91SAM9X5,
  19. };
  20. /**
  21. * sam9x5_periph_clk_bind() - for the periph clock driver
  22. * Recursively bind its children as clk devices.
  23. *
  24. * @return: 0 on success, or negative error code on failure
  25. */
  26. static int sam9x5_periph_clk_bind(struct udevice *dev)
  27. {
  28. return at91_clk_sub_device_bind(dev, "periph-clk");
  29. }
  30. static const struct udevice_id sam9x5_periph_clk_match[] = {
  31. {
  32. .compatible = "atmel,at91rm9200-clk-peripheral",
  33. .data = CLK_PERIPH_AT91RM9200,
  34. },
  35. {
  36. .compatible = "atmel,at91sam9x5-clk-peripheral",
  37. .data = CLK_PERIPH_AT91SAM9X5,
  38. },
  39. {}
  40. };
  41. U_BOOT_DRIVER(sam9x5_periph_clk) = {
  42. .name = "sam9x5-periph-clk",
  43. .id = UCLASS_MISC,
  44. .of_match = sam9x5_periph_clk_match,
  45. .bind = sam9x5_periph_clk_bind,
  46. };
  47. /*---------------------------------------------------------*/
  48. static int periph_clk_enable(struct clk *clk)
  49. {
  50. struct pmc_platdata *plat = dev_get_platdata(clk->dev);
  51. struct at91_pmc *pmc = plat->reg_base;
  52. enum periph_clk_type clk_type;
  53. void *addr;
  54. if (clk->id < PERIPHERAL_ID_MIN)
  55. return -1;
  56. clk_type = dev_get_driver_data(dev_get_parent(clk->dev));
  57. if (clk_type == CLK_PERIPH_AT91RM9200) {
  58. addr = &pmc->pcer;
  59. if (clk->id > PERIPHERAL_ID_MAX)
  60. addr = &pmc->pcer1;
  61. setbits_le32(addr, PERIPHERAL_MASK(clk->id));
  62. } else {
  63. writel(clk->id & AT91_PMC_PCR_PID_MASK, &pmc->pcr);
  64. setbits_le32(&pmc->pcr,
  65. AT91_PMC_PCR_CMD_WRITE | AT91_PMC_PCR_EN);
  66. }
  67. return 0;
  68. }
  69. static ulong periph_get_rate(struct clk *clk)
  70. {
  71. struct udevice *dev;
  72. struct clk clk_dev;
  73. ulong clk_rate;
  74. int ret;
  75. dev = dev_get_parent(clk->dev);
  76. ret = clk_get_by_index(dev, 0, &clk_dev);
  77. if (ret)
  78. return ret;
  79. clk_rate = clk_get_rate(&clk_dev);
  80. clk_free(&clk_dev);
  81. return clk_rate;
  82. }
  83. static struct clk_ops periph_clk_ops = {
  84. .of_xlate = at91_clk_of_xlate,
  85. .enable = periph_clk_enable,
  86. .get_rate = periph_get_rate,
  87. };
  88. U_BOOT_DRIVER(clk_periph) = {
  89. .name = "periph-clk",
  90. .id = UCLASS_CLK,
  91. .platdata_auto_alloc_size = sizeof(struct pmc_platdata),
  92. .probe = at91_clk_probe,
  93. .ops = &periph_clk_ops,
  94. };