cpu_sh4.h 2.2 KB

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  1. /*
  2. * (C) Copyright 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. */
  6. #ifndef _ASM_CPU_SH4_H_
  7. #define _ASM_CPU_SH4_H_
  8. /* cache control */
  9. #define CCR_CACHE_STOP 0x00000808
  10. #define CCR_CACHE_ENABLE 0x00000101
  11. #define CCR_CACHE_ICI 0x00000800
  12. #define CACHE_OC_ADDRESS_ARRAY 0xf4000000
  13. #if defined (CONFIG_CPU_SH7750) || \
  14. defined(CONFIG_CPU_SH7751)
  15. #define CACHE_OC_WAY_SHIFT 14
  16. #define CACHE_OC_NUM_ENTRIES 512
  17. #else
  18. #define CACHE_OC_WAY_SHIFT 13
  19. #define CACHE_OC_NUM_ENTRIES 256
  20. #endif
  21. #define CACHE_OC_ENTRY_SHIFT 5
  22. #if defined (CONFIG_CPU_SH7750) || \
  23. defined(CONFIG_CPU_SH7751)
  24. # include <asm/cpu_sh7750.h>
  25. #elif defined (CONFIG_CPU_SH7722)
  26. # include <asm/cpu_sh7722.h>
  27. #elif defined (CONFIG_CPU_SH7723)
  28. # include <asm/cpu_sh7723.h>
  29. #elif defined (CONFIG_CPU_SH7724)
  30. # include <asm/cpu_sh7724.h>
  31. #elif defined (CONFIG_CPU_SH7734)
  32. # include <asm/cpu_sh7734.h>
  33. #elif defined (CONFIG_CPU_SH7752)
  34. # include <asm/cpu_sh7752.h>
  35. #elif defined (CONFIG_CPU_SH7753)
  36. # include <asm/cpu_sh7753.h>
  37. #elif defined (CONFIG_CPU_SH7757)
  38. # include <asm/cpu_sh7757.h>
  39. #elif defined (CONFIG_CPU_SH7763)
  40. # include <asm/cpu_sh7763.h>
  41. #elif defined (CONFIG_CPU_SH7780)
  42. # include <asm/cpu_sh7780.h>
  43. #elif defined (CONFIG_CPU_SH7785)
  44. # include <asm/cpu_sh7785.h>
  45. #else
  46. # error "Unknown SH4 variant"
  47. #endif
  48. #if defined(CONFIG_SH_32BIT)
  49. #define PMB_ADDR_ARRAY 0xf6100000
  50. #define PMB_ADDR_ENTRY 8
  51. #define PMB_VPN 24
  52. #define PMB_DATA_ARRAY 0xf7100000
  53. #define PMB_DATA_ENTRY 8
  54. #define PMB_PPN 24
  55. #define PMB_UB 9 /* Buffered write */
  56. #define PMB_V 8 /* Valid */
  57. #define PMB_SZ1 7 /* Page size (upper bit) */
  58. #define PMB_SZ0 4 /* Page size (lower bit) */
  59. #define PMB_C 3 /* Cacheability */
  60. #define PMB_WT 0 /* Write-through */
  61. #define PMB_ADDR_BASE(entry) (PMB_ADDR_ARRAY + (entry << PMB_ADDR_ENTRY))
  62. #define PMB_DATA_BASE(entry) (PMB_DATA_ARRAY + (entry << PMB_DATA_ENTRY))
  63. #define mk_pmb_addr_val(vpn) ((vpn << PMB_VPN))
  64. #define mk_pmb_data_val(ppn, ub, v, sz1, sz0, c, wt) \
  65. ((ppn << PMB_PPN) | (ub << PMB_UB) | \
  66. (v << PMB_V) | (sz1 << PMB_SZ1) | \
  67. (sz0 << PMB_SZ0) | (c << PMB_C) | \
  68. (wt << PMB_WT))
  69. #endif
  70. #endif /* _ASM_CPU_SH4_H_ */