brcm,bcm3380.dtsi 2.9 KB

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  1. /*
  2. * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. */
  6. #include <dt-bindings/clock/bcm3380-clock.h>
  7. #include <dt-bindings/gpio/gpio.h>
  8. #include <dt-bindings/reset/bcm3380-reset.h>
  9. #include "skeleton.dtsi"
  10. / {
  11. compatible = "brcm,bcm3380";
  12. cpus {
  13. reg = <0x14e00000 0x4>;
  14. #address-cells = <1>;
  15. #size-cells = <0>;
  16. u-boot,dm-pre-reloc;
  17. cpu@0 {
  18. compatible = "brcm,bcm3380-cpu", "mips,mips4Kc";
  19. device_type = "cpu";
  20. reg = <0>;
  21. u-boot,dm-pre-reloc;
  22. };
  23. cpu@1 {
  24. compatible = "brcm,bcm3380-cpu", "mips,mips4Kc";
  25. device_type = "cpu";
  26. reg = <1>;
  27. u-boot,dm-pre-reloc;
  28. };
  29. };
  30. clocks {
  31. compatible = "simple-bus";
  32. #address-cells = <1>;
  33. #size-cells = <1>;
  34. u-boot,dm-pre-reloc;
  35. periph_osc: periph-osc {
  36. compatible = "fixed-clock";
  37. #clock-cells = <0>;
  38. clock-frequency = <48000000>;
  39. u-boot,dm-pre-reloc;
  40. };
  41. periph_clk0: periph-clk@14e00004 {
  42. compatible = "brcm,bcm6345-clk";
  43. reg = <0x14e00004 0x4>;
  44. #clock-cells = <1>;
  45. };
  46. periph_clk1: periph-clk@14e00008 {
  47. compatible = "brcm,bcm6345-clk";
  48. reg = <0x14e00008 0x4>;
  49. #clock-cells = <1>;
  50. };
  51. };
  52. ubus {
  53. compatible = "simple-bus";
  54. #address-cells = <1>;
  55. #size-cells = <1>;
  56. u-boot,dm-pre-reloc;
  57. memory-controller@12000000 {
  58. compatible = "brcm,bcm6328-mc";
  59. reg = <0x12000000 0x1000>;
  60. u-boot,dm-pre-reloc;
  61. };
  62. periph_rst0: reset-controller@14e0008c {
  63. compatible = "brcm,bcm6345-reset";
  64. reg = <0x14e0008c 0x4>;
  65. #reset-cells = <1>;
  66. };
  67. periph_rst1: reset-controller@14e00090 {
  68. compatible = "brcm,bcm6345-reset";
  69. reg = <0x14e00090 0x4>;
  70. #reset-cells = <1>;
  71. };
  72. pll_cntl: syscon@14e00094 {
  73. compatible = "syscon";
  74. reg = <0x14e00094 0x4>;
  75. };
  76. syscon-reboot {
  77. compatible = "syscon-reboot";
  78. regmap = <&pll_cntl>;
  79. offset = <0x0>;
  80. mask = <0x1>;
  81. };
  82. wdt: watchdog@14e000dc {
  83. compatible = "brcm,bcm6345-wdt";
  84. reg = <0x14e000dc 0xc>;
  85. clocks = <&periph_osc>;
  86. };
  87. wdt-reboot {
  88. compatible = "wdt-reboot";
  89. wdt = <&wdt>;
  90. };
  91. gpio0: gpio-controller@14e00100 {
  92. compatible = "brcm,bcm6345-gpio";
  93. reg = <0x14e00100 0x4>, <0x14e00108 0x4>;
  94. gpio-controller;
  95. #gpio-cells = <2>;
  96. status = "disabled";
  97. };
  98. gpio1: gpio-controller@14e00104 {
  99. compatible = "brcm,bcm6345-gpio";
  100. reg = <0x14e00104 0x4>, <0x14e0010c 0x4>;
  101. gpio-controller;
  102. #gpio-cells = <2>;
  103. ngpios = <3>;
  104. status = "disabled";
  105. };
  106. uart0: serial@14e00200 {
  107. compatible = "brcm,bcm6345-uart";
  108. reg = <0x14e00200 0x18>;
  109. clocks = <&periph_osc>;
  110. status = "disabled";
  111. };
  112. uart1: serial@14e00220 {
  113. compatible = "brcm,bcm6345-uart";
  114. reg = <0x14e00220 0x18>;
  115. clocks = <&periph_osc>;
  116. status = "disabled";
  117. };
  118. leds: led-controller@14e00f00 {
  119. compatible = "brcm,bcm6328-leds";
  120. reg = <0x14e00f00 0x1c>;
  121. #address-cells = <1>;
  122. #size-cells = <0>;
  123. status = "disabled";
  124. };
  125. };
  126. };