cpu.c 2.6 KB

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  1. /*
  2. *
  3. * (C) Copyright 2000-2003
  4. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  5. *
  6. * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
  7. * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  8. *
  9. * SPDX-License-Identifier: GPL-2.0+
  10. */
  11. #include <common.h>
  12. #include <watchdog.h>
  13. #include <command.h>
  14. #include <netdev.h>
  15. #include <asm/immap.h>
  16. #include <asm/io.h>
  17. DECLARE_GLOBAL_DATA_PTR;
  18. int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
  19. {
  20. gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR);
  21. out_be16(&gptmr->pre, 10);
  22. out_be16(&gptmr->cnt, 1);
  23. /* enable watchdog, set timeout to 0 and wait */
  24. out_8(&gptmr->mode, GPT_TMS_SGPIO);
  25. out_8(&gptmr->ctrl, GPT_CTRL_WDEN | GPT_CTRL_CE);
  26. /* we don't return! */
  27. return 1;
  28. };
  29. int checkcpu(void)
  30. {
  31. siu_t *siu = (siu_t *) MMAP_SIU;
  32. u16 id = 0;
  33. puts("CPU: ");
  34. switch ((in_be32(&siu->jtagid) & 0x000FF000) >> 12) {
  35. case 0x0C:
  36. id = 5485;
  37. break;
  38. case 0x0D:
  39. id = 5484;
  40. break;
  41. case 0x0E:
  42. id = 5483;
  43. break;
  44. case 0x0F:
  45. id = 5482;
  46. break;
  47. case 0x10:
  48. id = 5481;
  49. break;
  50. case 0x11:
  51. id = 5480;
  52. break;
  53. case 0x12:
  54. id = 5475;
  55. break;
  56. case 0x13:
  57. id = 5474;
  58. break;
  59. case 0x14:
  60. id = 5473;
  61. break;
  62. case 0x15:
  63. id = 5472;
  64. break;
  65. case 0x16:
  66. id = 5471;
  67. break;
  68. case 0x17:
  69. id = 5470;
  70. break;
  71. }
  72. if (id) {
  73. char buf1[32], buf2[32];
  74. printf("Freescale MCF%d\n", id);
  75. printf(" CPU CLK %s MHz BUS CLK %s MHz\n",
  76. strmhz(buf1, gd->cpu_clk),
  77. strmhz(buf2, gd->bus_clk));
  78. }
  79. return 0;
  80. };
  81. #if defined(CONFIG_HW_WATCHDOG)
  82. /* Called by macro WATCHDOG_RESET */
  83. void hw_watchdog_reset(void)
  84. {
  85. gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR);
  86. out_8(&gptmr->ocpw, 0xa5);
  87. }
  88. int watchdog_disable(void)
  89. {
  90. gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR);
  91. /* UserManual, once the wdog is disabled, wdog cannot be re-enabled */
  92. out_8(&gptmr->mode, 0);
  93. out_8(&gptmr->ctrl, 0);
  94. puts("WATCHDOG:disabled\n");
  95. return (0);
  96. }
  97. int watchdog_init(void)
  98. {
  99. gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR);
  100. out_be16(&gptmr->pre, CONFIG_WATCHDOG_TIMEOUT);
  101. out_be16(&gptmr->cnt, CONFIG_SYS_TIMER_PRESCALER * 1000);
  102. out_8(&gptmr->mode, GPT_TMS_SGPIO);
  103. out_8(&gptmr->ctrl, GPT_CTRL_CE | GPT_CTRL_WDEN);
  104. puts("WATCHDOG:enabled\n");
  105. return (0);
  106. }
  107. #endif /* CONFIG_HW_WATCHDOG */
  108. #if defined(CONFIG_FSLDMAFEC) || defined(CONFIG_MCFFEC)
  109. /* Default initializations for MCFFEC controllers. To override,
  110. * create a board-specific function called:
  111. * int board_eth_init(bd_t *bis)
  112. */
  113. int cpu_eth_init(bd_t *bis)
  114. {
  115. #if defined(CONFIG_FSLDMAFEC)
  116. mcdmafec_initialize(bis);
  117. #endif
  118. #if defined(CONFIG_MCFFEC)
  119. mcffec_initialize(bis);
  120. #endif
  121. return 0;
  122. }
  123. #endif