sf_params.c 9.3 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179
  1. /*
  2. * SPI flash Params table
  3. *
  4. * Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc.
  5. *
  6. * SPDX-License-Identifier: GPL-2.0+
  7. */
  8. #include <common.h>
  9. #include <spi.h>
  10. #include <spi_flash.h>
  11. #include "sf_internal.h"
  12. /* Used when the "_ext_id" is two bytes at most */
  13. #define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
  14. .id = { \
  15. ((_jedec_id) >> 16) & 0xff, \
  16. ((_jedec_id) >> 8) & 0xff, \
  17. (_jedec_id) & 0xff, \
  18. ((_ext_id) >> 8) & 0xff, \
  19. (_ext_id) & 0xff, \
  20. }, \
  21. .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))), \
  22. .sector_size = (_sector_size), \
  23. .n_sectors = (_n_sectors), \
  24. .page_size = 256, \
  25. .flags = (_flags),
  26. #define INFO6(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
  27. .id = { \
  28. ((_jedec_id) >> 16) & 0xff, \
  29. ((_jedec_id) >> 8) & 0xff, \
  30. (_jedec_id) & 0xff, \
  31. ((_ext_id) >> 16) & 0xff, \
  32. ((_ext_id) >> 8) & 0xff, \
  33. (_ext_id) & 0xff, \
  34. }, \
  35. .id_len = 6, \
  36. .sector_size = (_sector_size), \
  37. .n_sectors = (_n_sectors), \
  38. .page_size = 256, \
  39. .flags = (_flags),
  40. const struct spi_flash_info spi_flash_ids[] = {
  41. #ifdef CONFIG_SPI_FLASH_ATMEL /* ATMEL */
  42. {"AT45DB011D", INFO(0x1f2200, 0x0, 64 * 1024, 4, SECT_4K) },
  43. {"AT45DB021D", INFO(0x1f2300, 0x0, 64 * 1024, 8, SECT_4K) },
  44. {"AT45DB041D", INFO(0x1f2400, 0x0, 64 * 1024, 8, SECT_4K) },
  45. {"AT45DB081D", INFO(0x1f2500, 0x0, 64 * 1024, 16, SECT_4K) },
  46. {"AT45DB161D", INFO(0x1f2600, 0x0, 64 * 1024, 32, SECT_4K) },
  47. {"AT45DB321D", INFO(0x1f2700, 0x0, 64 * 1024, 64, SECT_4K) },
  48. {"AT45DB641D", INFO(0x1f2800, 0x0, 64 * 1024, 128, SECT_4K) },
  49. {"AT25DF321A", INFO(0x1f4701, 0x0, 64 * 1024, 64, SECT_4K) },
  50. {"AT25DF321", INFO(0x1f4700, 0x0, 64 * 1024, 64, SECT_4K) },
  51. {"AT26DF081A", INFO(0x1f4501, 0x0, 64 * 1024, 16, SECT_4K) },
  52. #endif
  53. #ifdef CONFIG_SPI_FLASH_EON /* EON */
  54. {"EN25Q32B", INFO(0x1c3016, 0x0, 64 * 1024, 64, 0) },
  55. {"EN25Q64", INFO(0x1c3017, 0x0, 64 * 1024, 128, SECT_4K) },
  56. {"EN25Q128B", INFO(0x1c3018, 0x0, 64 * 1024, 256, 0) },
  57. {"EN25S64", INFO(0x1c3817, 0x0, 64 * 1024, 128, 0) },
  58. #endif
  59. #ifdef CONFIG_SPI_FLASH_GIGADEVICE /* GIGADEVICE */
  60. {"GD25Q64B", INFO(0xc84017, 0x0, 64 * 1024, 128, SECT_4K) },
  61. {"GD25LQ32", INFO(0xc86016, 0x0, 64 * 1024, 64, SECT_4K) },
  62. #endif
  63. #ifdef CONFIG_SPI_FLASH_ISSI /* ISSI */
  64. {"IS25LP032", INFO(0x9d6016, 0x0, 64 * 1024, 64, 0) },
  65. {"IS25LP064", INFO(0x9d6017, 0x0, 64 * 1024, 128, 0) },
  66. {"IS25LP128", INFO(0x9d6018, 0x0, 64 * 1024, 256, 0) },
  67. #endif
  68. #ifdef CONFIG_SPI_FLASH_MACRONIX /* MACRONIX */
  69. {"MX25L2006E", INFO(0xc22012, 0x0, 64 * 1024, 4, 0) },
  70. {"MX25L4005", INFO(0xc22013, 0x0, 64 * 1024, 8, 0) },
  71. {"MX25L8005", INFO(0xc22014, 0x0, 64 * 1024, 16, 0) },
  72. {"MX25L1605D", INFO(0xc22015, 0x0, 64 * 1024, 32, 0) },
  73. {"MX25L3205D", INFO(0xc22016, 0x0, 64 * 1024, 64, 0) },
  74. {"MX25L6405D", INFO(0xc22017, 0x0, 64 * 1024, 128, 0) },
  75. {"MX25L12805", INFO(0xc22018, 0x0, 64 * 1024, 256, RD_FULL | WR_QPP) },
  76. {"MX25L25635F", INFO(0xc22019, 0x0, 64 * 1024, 512, RD_FULL | WR_QPP) },
  77. {"MX25L51235F", INFO(0xc2201a, 0x0, 64 * 1024, 1024, RD_FULL | WR_QPP) },
  78. {"MX25L12855E", INFO(0xc22618, 0x0, 64 * 1024, 256, RD_FULL | WR_QPP) },
  79. #endif
  80. #ifdef CONFIG_SPI_FLASH_SPANSION /* SPANSION */
  81. {"S25FL008A", INFO(0x010213, 0x0, 64 * 1024, 16, 0) },
  82. {"S25FL016A", INFO(0x010214, 0x0, 64 * 1024, 32, 0) },
  83. {"S25FL032A", INFO(0x010215, 0x0, 64 * 1024, 64, 0) },
  84. {"S25FL064A", INFO(0x010216, 0x0, 64 * 1024, 128, 0) },
  85. {"S25FL116K", INFO(0x014015, 0x0, 64 * 1024, 128, 0) },
  86. {"S25FL164K", INFO(0x014017, 0x0140, 64 * 1024, 128, 0) },
  87. {"S25FL128P_256K", INFO(0x012018, 0x0300, 256 * 1024, 64, RD_FULL | WR_QPP) },
  88. {"S25FL128P_64K", INFO(0x012018, 0x0301, 64 * 1024, 256, RD_FULL | WR_QPP) },
  89. {"S25FL032P", INFO(0x010215, 0x4d00, 64 * 1024, 64, RD_FULL | WR_QPP) },
  90. {"S25FL064P", INFO(0x010216, 0x4d00, 64 * 1024, 128, RD_FULL | WR_QPP) },
  91. {"S25FL128S_256K", INFO(0x012018, 0x4d00, 256 * 1024, 64, RD_FULL | WR_QPP) },
  92. {"S25FL128S_64K", INFO(0x012018, 0x4d01, 64 * 1024, 256, RD_FULL | WR_QPP) },
  93. {"S25FL256S_256K", INFO(0x010219, 0x4d00, 256 * 1024, 128, RD_FULL | WR_QPP) },
  94. {"S25FL256S_64K", INFO(0x010219, 0x4d01, 64 * 1024, 512, RD_FULL | WR_QPP) },
  95. {"S25FS256S_64K", INFO6(0x010219, 0x4d0181, 64 * 1024, 512, RD_FULL | WR_QPP | SECT_4K) },
  96. {"S25FS512S", INFO(0x010220, 0x4D00, 128 * 1024, 512, RD_FULL | WR_QPP | SECT_4K) },
  97. {"S25FL512S_256K", INFO(0x010220, 0x4d00, 256 * 1024, 256, RD_FULL | WR_QPP) },
  98. {"S25FL512S_64K", INFO(0x010220, 0x4d01, 64 * 1024, 1024, RD_FULL | WR_QPP) },
  99. {"S25FL512S_512K", INFO(0x010220, 0x4f00, 256 * 1024, 256, RD_FULL | WR_QPP) },
  100. #endif
  101. #ifdef CONFIG_SPI_FLASH_STMICRO /* STMICRO */
  102. {"M25P10", INFO(0x202011, 0x0, 32 * 1024, 4, 0) },
  103. {"M25P20", INFO(0x202012, 0x0, 64 * 1024, 4, 0) },
  104. {"M25P40", INFO(0x202013, 0x0, 64 * 1024, 8, 0) },
  105. {"M25P80", INFO(0x202014, 0x0, 64 * 1024, 16, 0) },
  106. {"M25P16", INFO(0x202015, 0x0, 64 * 1024, 32, 0) },
  107. {"M25PE16", INFO(0x208015, 0x1000, 64 * 1024, 32, 0) },
  108. {"M25PX16", INFO(0x207115, 0x1000, 64 * 1024, 32, RD_QUAD | RD_DUAL) },
  109. {"M25P32", INFO(0x202016, 0x0, 64 * 1024, 64, 0) },
  110. {"M25P64", INFO(0x202017, 0x0, 64 * 1024, 128, 0) },
  111. {"M25P128", INFO(0x202018, 0x0, 256 * 1024, 64, 0) },
  112. {"M25PX64", INFO(0x207117, 0x0, 64 * 1024, 128, SECT_4K) },
  113. {"N25Q016A", INFO(0x20bb15, 0x0, 64 * 1024, 32, SECT_4K) },
  114. {"N25Q32", INFO(0x20ba16, 0x0, 64 * 1024, 64, RD_FULL | WR_QPP | SECT_4K) },
  115. {"N25Q32A", INFO(0x20bb16, 0x0, 64 * 1024, 64, RD_FULL | WR_QPP | SECT_4K) },
  116. {"N25Q64", INFO(0x20ba17, 0x0, 64 * 1024, 128, RD_FULL | WR_QPP | SECT_4K) },
  117. {"N25Q64A", INFO(0x20bb17, 0x0, 64 * 1024, 128, RD_FULL | WR_QPP | SECT_4K) },
  118. {"N25Q128", INFO(0x20ba18, 0x0, 64 * 1024, 256, RD_FULL | WR_QPP) },
  119. {"N25Q128A", INFO(0x20bb18, 0x0, 64 * 1024, 256, RD_FULL | WR_QPP) },
  120. {"N25Q256", INFO(0x20ba19, 0x0, 64 * 1024, 512, RD_FULL | WR_QPP | SECT_4K) },
  121. {"N25Q256A", INFO(0x20bb19, 0x0, 64 * 1024, 512, RD_FULL | WR_QPP | SECT_4K) },
  122. {"N25Q512", INFO(0x20ba20, 0x0, 64 * 1024, 1024, RD_FULL | WR_QPP | E_FSR | SECT_4K) },
  123. {"N25Q512A", INFO(0x20bb20, 0x0, 64 * 1024, 1024, RD_FULL | WR_QPP | E_FSR | SECT_4K) },
  124. {"N25Q1024", INFO(0x20ba21, 0x0, 64 * 1024, 2048, RD_FULL | WR_QPP | E_FSR | SECT_4K) },
  125. {"N25Q1024A", INFO(0x20bb21, 0x0, 64 * 1024, 2048, RD_FULL | WR_QPP | E_FSR | SECT_4K) },
  126. #endif
  127. #ifdef CONFIG_SPI_FLASH_SST /* SST */
  128. {"SST25VF040B", INFO(0xbf258d, 0x0, 64 * 1024, 8, SECT_4K | SST_WR) },
  129. {"SST25VF080B", INFO(0xbf258e, 0x0, 64 * 1024, 16, SECT_4K | SST_WR) },
  130. {"SST25VF016B", INFO(0xbf2541, 0x0, 64 * 1024, 32, SECT_4K | SST_WR) },
  131. {"SST25VF032B", INFO(0xbf254a, 0x0, 64 * 1024, 64, SECT_4K | SST_WR) },
  132. {"SST25VF064C", INFO(0xbf254b, 0x0, 64 * 1024, 128, SECT_4K) },
  133. {"SST25WF512", INFO(0xbf2501, 0x0, 64 * 1024, 1, SECT_4K | SST_WR) },
  134. {"SST25WF010", INFO(0xbf2502, 0x0, 64 * 1024, 2, SECT_4K | SST_WR) },
  135. {"SST25WF020", INFO(0xbf2503, 0x0, 64 * 1024, 4, SECT_4K | SST_WR) },
  136. {"SST25WF040", INFO(0xbf2504, 0x0, 64 * 1024, 8, SECT_4K | SST_WR) },
  137. {"SST25WF040B", INFO(0x621613, 0x0, 64 * 1024, 8, SECT_4K) },
  138. {"SST25WF080", INFO(0xbf2505, 0x0, 64 * 1024, 16, SECT_4K | SST_WR) },
  139. #endif
  140. #ifdef CONFIG_SPI_FLASH_WINBOND /* WINBOND */
  141. {"W25P80", INFO(0xef2014, 0x0, 64 * 1024, 16, 0) },
  142. {"W25P16", INFO(0xef2015, 0x0, 64 * 1024, 32, 0) },
  143. {"W25P32", INFO(0xef2016, 0x0, 64 * 1024, 64, 0) },
  144. {"W25X40", INFO(0xef3013, 0x0, 64 * 1024, 8, SECT_4K) },
  145. {"W25X16", INFO(0xef3015, 0x0, 64 * 1024, 32, SECT_4K) },
  146. {"W25X32", INFO(0xef3016, 0x0, 64 * 1024, 64, SECT_4K) },
  147. {"W25X64", INFO(0xef3017, 0x0, 64 * 1024, 128, SECT_4K) },
  148. {"W25Q80BL", INFO(0xef4014, 0x0, 64 * 1024, 16, RD_FULL | WR_QPP | SECT_4K) },
  149. {"W25Q16CL", INFO(0xef4015, 0x0, 64 * 1024, 32, RD_FULL | WR_QPP | SECT_4K) },
  150. {"W25Q32BV", INFO(0xef4016, 0x0, 64 * 1024, 64, RD_FULL | WR_QPP | SECT_4K) },
  151. {"W25Q64CV", INFO(0xef4017, 0x0, 64 * 1024, 128, RD_FULL | WR_QPP | SECT_4K) },
  152. {"W25Q128BV", INFO(0xef4018, 0x0, 64 * 1024, 256, RD_FULL | WR_QPP | SECT_4K) },
  153. {"W25Q256", INFO(0xef4019, 0x0, 64 * 1024, 512, RD_FULL | WR_QPP | SECT_4K) },
  154. {"W25Q80BW", INFO(0xef5014, 0x0, 64 * 1024, 16, RD_FULL | WR_QPP | SECT_4K) },
  155. {"W25Q16DW", INFO(0xef6015, 0x0, 64 * 1024, 32, RD_FULL | WR_QPP | SECT_4K) },
  156. {"W25Q32DW", INFO(0xef6016, 0x0, 64 * 1024, 64, RD_FULL | WR_QPP | SECT_4K) },
  157. {"W25Q64DW", INFO(0xef6017, 0x0, 64 * 1024, 128, RD_FULL | WR_QPP | SECT_4K) },
  158. {"W25Q128FW", INFO(0xef6018, 0x0, 64 * 1024, 256, RD_FULL | WR_QPP | SECT_4K) },
  159. #endif
  160. {}, /* Empty entry to terminate the list */
  161. /*
  162. * Note:
  163. * Below paired flash devices has similar spi_flash params.
  164. * (S25FL129P_64K, S25FL128S_64K)
  165. * (W25Q80BL, W25Q80BV)
  166. * (W25Q16CL, W25Q16DV)
  167. * (W25Q32BV, W25Q32FV_SPI)
  168. * (W25Q64CV, W25Q64FV_SPI)
  169. * (W25Q128BV, W25Q128FV_SPI)
  170. * (W25Q32DW, W25Q32FV_QPI)
  171. * (W25Q64DW, W25Q64FV_QPI)
  172. * (W25Q128FW, W25Q128FV_QPI)
  173. */
  174. };