clock.h 2.4 KB

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  1. /*
  2. * keystone2: common clock header file
  3. *
  4. * (C) Copyright 2012-2014
  5. * Texas Instruments Incorporated, <www.ti.com>
  6. *
  7. * SPDX-License-Identifier: GPL-2.0+
  8. */
  9. #ifndef __ASM_ARCH_CLOCK_H
  10. #define __ASM_ARCH_CLOCK_H
  11. #ifndef __ASSEMBLY__
  12. #ifdef CONFIG_SOC_K2HK
  13. #include <asm/arch/clock-k2hk.h>
  14. #endif
  15. #ifdef CONFIG_SOC_K2E
  16. #include <asm/arch/clock-k2e.h>
  17. #endif
  18. #ifdef CONFIG_SOC_K2L
  19. #include <asm/arch/clock-k2l.h>
  20. #endif
  21. #ifdef CONFIG_SOC_K2G
  22. #include <asm/arch/clock-k2g.h>
  23. #endif
  24. #define CORE_PLL MAIN_PLL
  25. #define DDR3_PLL DDR3A_PLL
  26. #define NSS_PLL PASS_PLL
  27. #define CLK_LIST(CLK)\
  28. CLK(0, core_pll_clk)\
  29. CLK(1, pass_pll_clk)\
  30. CLK(2, tetris_pll_clk)\
  31. CLK(3, ddr3a_pll_clk)\
  32. CLK(4, ddr3b_pll_clk)\
  33. CLK(5, sys_clk0_clk)\
  34. CLK(6, sys_clk0_1_clk)\
  35. CLK(7, sys_clk0_2_clk)\
  36. CLK(8, sys_clk0_3_clk)\
  37. CLK(9, sys_clk0_4_clk)\
  38. CLK(10, sys_clk0_6_clk)\
  39. CLK(11, sys_clk0_8_clk)\
  40. CLK(12, sys_clk0_12_clk)\
  41. CLK(13, sys_clk0_24_clk)\
  42. CLK(14, sys_clk1_clk)\
  43. CLK(15, sys_clk1_3_clk)\
  44. CLK(16, sys_clk1_4_clk)\
  45. CLK(17, sys_clk1_6_clk)\
  46. CLK(18, sys_clk1_12_clk)\
  47. CLK(19, sys_clk2_clk)\
  48. CLK(20, sys_clk3_clk)\
  49. CLK(21, uart_pll_clk)
  50. #include <asm/types.h>
  51. #define GENERATE_ENUM(NUM, ENUM) ENUM = NUM,
  52. #define GENERATE_INDX_STR(NUM, STRING) #NUM"\t- "#STRING"\n"
  53. #define CLOCK_INDEXES_LIST CLK_LIST(GENERATE_INDX_STR)
  54. enum {
  55. SPD200,
  56. SPD400,
  57. SPD600,
  58. SPD800,
  59. SPD850,
  60. SPD900,
  61. SPD1000,
  62. SPD1200,
  63. SPD1250,
  64. SPD1350,
  65. SPD1400,
  66. SPD1500,
  67. NUM_SPDS,
  68. };
  69. /* PLL identifiers */
  70. enum {
  71. MAIN_PLL,
  72. TETRIS_PLL,
  73. PASS_PLL,
  74. DDR3A_PLL,
  75. DDR3B_PLL,
  76. UART_PLL,
  77. MAX_PLL_COUNT,
  78. };
  79. enum ext_clk_e {
  80. sys_clk,
  81. alt_core_clk,
  82. pa_clk,
  83. tetris_clk,
  84. ddr3a_clk,
  85. ddr3b_clk,
  86. uart_clk,
  87. ext_clk_count /* number of external clocks */
  88. };
  89. enum clk_e {
  90. CLK_LIST(GENERATE_ENUM)
  91. };
  92. struct keystone_pll_regs {
  93. u32 reg0;
  94. u32 reg1;
  95. };
  96. /* PLL configuration data */
  97. struct pll_init_data {
  98. int pll;
  99. int pll_m; /* PLL Multiplier */
  100. int pll_d; /* PLL divider */
  101. int pll_od; /* PLL output divider */
  102. };
  103. extern unsigned int external_clk[ext_clk_count];
  104. extern const struct keystone_pll_regs keystone_pll_regs[];
  105. extern s16 divn_val[];
  106. extern int speeds[];
  107. void init_plls(void);
  108. void init_pll(const struct pll_init_data *data);
  109. struct pll_init_data *get_pll_init_data(int pll);
  110. unsigned long ks_clk_get_rate(unsigned int clk);
  111. int get_max_dev_speed(int *spds);
  112. int get_max_arm_speed(int *spds);
  113. void pll_pa_clk_sel(void);
  114. #endif
  115. #endif