timer.c 2.7 KB

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  1. /*
  2. * (C) Copyright 2007
  3. * Sascha Hauer, Pengutronix
  4. *
  5. * (C) Copyright 2009 Freescale Semiconductor, Inc.
  6. *
  7. * SPDX-License-Identifier: GPL-2.0+
  8. */
  9. #include <common.h>
  10. #include <asm/io.h>
  11. #include <div64.h>
  12. #include <asm/arch/imx-regs.h>
  13. #include <asm/arch/clock.h>
  14. #include <asm/arch/sys_proto.h>
  15. /* General purpose timers registers */
  16. struct mxc_gpt {
  17. unsigned int control;
  18. unsigned int prescaler;
  19. unsigned int status;
  20. unsigned int nouse[6];
  21. unsigned int counter;
  22. };
  23. static struct mxc_gpt *cur_gpt = (struct mxc_gpt *)GPT1_BASE_ADDR;
  24. /* General purpose timers bitfields */
  25. #define GPTCR_SWR (1 << 15) /* Software reset */
  26. #define GPTCR_24MEN (1 << 10) /* Enable 24MHz clock input */
  27. #define GPTCR_FRR (1 << 9) /* Freerun / restart */
  28. #define GPTCR_CLKSOURCE_32 (4 << 6) /* Clock source 32khz */
  29. #define GPTCR_CLKSOURCE_OSC (5 << 6) /* Clock source OSC */
  30. #define GPTCR_CLKSOURCE_PRE (1 << 6) /* Clock source PRECLK */
  31. #define GPTCR_CLKSOURCE_MASK (0x7 << 6)
  32. #define GPTCR_TEN 1 /* Timer enable */
  33. #define GPTPR_PRESCALER24M_SHIFT 12
  34. #define GPTPR_PRESCALER24M_MASK (0xF << GPTPR_PRESCALER24M_SHIFT)
  35. DECLARE_GLOBAL_DATA_PTR;
  36. static inline int gpt_has_clk_source_osc(void)
  37. {
  38. #if defined(CONFIG_MX6)
  39. if (((is_mx6dq()) && (soc_rev() > CHIP_REV_1_0)) ||
  40. is_mx6dqp() || is_mx6sdl() || is_mx6sx() || is_mx6ul())
  41. return 1;
  42. return 0;
  43. #else
  44. return 0;
  45. #endif
  46. }
  47. static inline ulong gpt_get_clk(void)
  48. {
  49. #ifdef CONFIG_MXC_GPT_HCLK
  50. if (gpt_has_clk_source_osc())
  51. return MXC_HCLK >> 3;
  52. else
  53. return mxc_get_clock(MXC_IPG_PERCLK);
  54. #else
  55. return MXC_CLK32;
  56. #endif
  57. }
  58. int timer_init(void)
  59. {
  60. int i;
  61. /* setup GP Timer 1 */
  62. __raw_writel(GPTCR_SWR, &cur_gpt->control);
  63. /* We have no udelay by now */
  64. for (i = 0; i < 100; i++)
  65. __raw_writel(0, &cur_gpt->control);
  66. i = __raw_readl(&cur_gpt->control);
  67. i &= ~GPTCR_CLKSOURCE_MASK;
  68. #ifdef CONFIG_MXC_GPT_HCLK
  69. if (gpt_has_clk_source_osc()) {
  70. i |= GPTCR_CLKSOURCE_OSC | GPTCR_TEN;
  71. /* For DL/S, SX, UL, set 24Mhz OSC Enable bit and prescaler */
  72. if (is_mx6sdl() || is_mx6sx() || is_mx6ul()) {
  73. i |= GPTCR_24MEN;
  74. /* Produce 3Mhz clock */
  75. __raw_writel((7 << GPTPR_PRESCALER24M_SHIFT),
  76. &cur_gpt->prescaler);
  77. }
  78. } else {
  79. i |= GPTCR_CLKSOURCE_PRE | GPTCR_TEN;
  80. }
  81. #else
  82. __raw_writel(0, &cur_gpt->prescaler); /* 32Khz */
  83. i |= GPTCR_CLKSOURCE_32 | GPTCR_TEN;
  84. #endif
  85. __raw_writel(i, &cur_gpt->control);
  86. gd->arch.tbl = __raw_readl(&cur_gpt->counter);
  87. gd->arch.tbu = 0;
  88. return 0;
  89. }
  90. unsigned long timer_read_counter(void)
  91. {
  92. return __raw_readl(&cur_gpt->counter); /* current tick value */
  93. }
  94. /*
  95. * This function is derived from PowerPC code (timebase clock frequency).
  96. * On ARM it returns the number of timer ticks per second.
  97. */
  98. ulong get_tbclk(void)
  99. {
  100. return gpt_get_clk();
  101. }