timer.c 4.4 KB

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  1. /*
  2. * (C) Copyright 2007
  3. * Sascha Hauer, Pengutronix
  4. *
  5. * (C) Copyright 2009 Freescale Semiconductor, Inc.
  6. *
  7. * SPDX-License-Identifier: GPL-2.0+
  8. */
  9. #include <common.h>
  10. #include <asm/io.h>
  11. #include <div64.h>
  12. #include <asm/arch/imx-regs.h>
  13. #include <asm/arch/clock.h>
  14. #include <asm/arch/sys_proto.h>
  15. /* General purpose timers registers */
  16. struct mxc_gpt {
  17. unsigned int control;
  18. unsigned int prescaler;
  19. unsigned int status;
  20. unsigned int nouse[6];
  21. unsigned int counter;
  22. };
  23. static struct mxc_gpt *cur_gpt = (struct mxc_gpt *)GPT1_BASE_ADDR;
  24. /* General purpose timers bitfields */
  25. #define GPTCR_SWR (1 << 15) /* Software reset */
  26. #define GPTCR_24MEN (1 << 10) /* Enable 24MHz clock input */
  27. #define GPTCR_FRR (1 << 9) /* Freerun / restart */
  28. #define GPTCR_CLKSOURCE_32 (4 << 6) /* Clock source 32khz */
  29. #define GPTCR_CLKSOURCE_OSC (5 << 6) /* Clock source OSC */
  30. #define GPTCR_CLKSOURCE_PRE (1 << 6) /* Clock source PRECLK */
  31. #define GPTCR_CLKSOURCE_MASK (0x7 << 6)
  32. #define GPTCR_TEN 1 /* Timer enable */
  33. #define GPTPR_PRESCALER24M_SHIFT 12
  34. #define GPTPR_PRESCALER24M_MASK (0xF << GPTPR_PRESCALER24M_SHIFT)
  35. DECLARE_GLOBAL_DATA_PTR;
  36. static inline int gpt_has_clk_source_osc(void)
  37. {
  38. #if defined(CONFIG_MX6)
  39. if (((is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) &&
  40. (soc_rev() > CHIP_REV_1_0)) || is_cpu_type(MXC_CPU_MX6DL) ||
  41. is_cpu_type(MXC_CPU_MX6SOLO) || is_cpu_type(MXC_CPU_MX6SX) ||
  42. is_cpu_type(MXC_CPU_MX6UL))
  43. return 1;
  44. return 0;
  45. #else
  46. return 0;
  47. #endif
  48. }
  49. static inline ulong gpt_get_clk(void)
  50. {
  51. #ifdef CONFIG_MXC_GPT_HCLK
  52. if (gpt_has_clk_source_osc())
  53. return MXC_HCLK >> 3;
  54. else
  55. return mxc_get_clock(MXC_IPG_PERCLK);
  56. #else
  57. return MXC_CLK32;
  58. #endif
  59. }
  60. static inline unsigned long long tick_to_time(unsigned long long tick)
  61. {
  62. ulong gpt_clk = gpt_get_clk();
  63. tick *= CONFIG_SYS_HZ;
  64. do_div(tick, gpt_clk);
  65. return tick;
  66. }
  67. static inline unsigned long long us_to_tick(unsigned long long usec)
  68. {
  69. ulong gpt_clk = gpt_get_clk();
  70. usec = usec * gpt_clk + 999999;
  71. do_div(usec, 1000000);
  72. return usec;
  73. }
  74. int timer_init(void)
  75. {
  76. int i;
  77. /* setup GP Timer 1 */
  78. __raw_writel(GPTCR_SWR, &cur_gpt->control);
  79. /* We have no udelay by now */
  80. for (i = 0; i < 100; i++)
  81. __raw_writel(0, &cur_gpt->control);
  82. i = __raw_readl(&cur_gpt->control);
  83. i &= ~GPTCR_CLKSOURCE_MASK;
  84. #ifdef CONFIG_MXC_GPT_HCLK
  85. if (gpt_has_clk_source_osc()) {
  86. i |= GPTCR_CLKSOURCE_OSC | GPTCR_TEN;
  87. /* For DL/S, SX, UL, set 24Mhz OSC Enable bit and prescaler */
  88. if (is_cpu_type(MXC_CPU_MX6DL) ||
  89. is_cpu_type(MXC_CPU_MX6SOLO) ||
  90. is_cpu_type(MXC_CPU_MX6SX) ||
  91. is_cpu_type(MXC_CPU_MX6UL)) {
  92. i |= GPTCR_24MEN;
  93. /* Produce 3Mhz clock */
  94. __raw_writel((7 << GPTPR_PRESCALER24M_SHIFT),
  95. &cur_gpt->prescaler);
  96. }
  97. } else {
  98. i |= GPTCR_CLKSOURCE_PRE | GPTCR_TEN;
  99. }
  100. #else
  101. __raw_writel(0, &cur_gpt->prescaler); /* 32Khz */
  102. i |= GPTCR_CLKSOURCE_32 | GPTCR_TEN;
  103. #endif
  104. __raw_writel(i, &cur_gpt->control);
  105. gd->arch.tbl = __raw_readl(&cur_gpt->counter);
  106. gd->arch.tbu = 0;
  107. return 0;
  108. }
  109. unsigned long long get_ticks(void)
  110. {
  111. ulong now = __raw_readl(&cur_gpt->counter); /* current tick value */
  112. /* increment tbu if tbl has rolled over */
  113. if (now < gd->arch.tbl)
  114. gd->arch.tbu++;
  115. gd->arch.tbl = now;
  116. return (((unsigned long long)gd->arch.tbu) << 32) | gd->arch.tbl;
  117. }
  118. ulong get_timer_masked(void)
  119. {
  120. /*
  121. * get_ticks() returns a long long (64 bit), it wraps in
  122. * 2^64 / GPT_CLK = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
  123. * 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in
  124. * 5 * 10^6 days - long enough.
  125. */
  126. return tick_to_time(get_ticks());
  127. }
  128. ulong get_timer(ulong base)
  129. {
  130. return get_timer_masked() - base;
  131. }
  132. /* delay x useconds AND preserve advance timstamp value */
  133. void __udelay(unsigned long usec)
  134. {
  135. unsigned long long tmp;
  136. ulong tmo;
  137. tmo = us_to_tick(usec);
  138. tmp = get_ticks() + tmo; /* get current timestamp */
  139. while (get_ticks() < tmp) /* loop till event */
  140. /*NOP*/;
  141. }
  142. /*
  143. * This function is derived from PowerPC code (timebase clock frequency).
  144. * On ARM it returns the number of timer ticks per second.
  145. */
  146. ulong get_tbclk(void)
  147. {
  148. return gpt_get_clk();
  149. }
  150. /*
  151. * This function is intended for SHORT delays only.
  152. * It will overflow at around 10 seconds @ 400MHz,
  153. * or 20 seconds @ 200MHz.
  154. */
  155. unsigned long usec2ticks(unsigned long usec)
  156. {
  157. ulong ticks;
  158. if (usec < 1000)
  159. ticks = ((usec * (get_tbclk()/1000)) + 500) / 1000;
  160. else
  161. ticks = ((usec / 10) * (get_tbclk() / 100000));
  162. return ticks;
  163. }