natsemi.c 2.4 KB

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  1. /*
  2. * National Semiconductor PHY drivers
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. *
  6. * Copyright 2010-2011 Freescale Semiconductor, Inc.
  7. * author Andy Fleming
  8. */
  9. #include <phy.h>
  10. /* NatSemi DP83630 */
  11. #define DP83630_PHY_PAGESEL_REG 0x13
  12. #define DP83630_PHY_PTP_COC_REG 0x14
  13. #define DP83630_PHY_PTP_CLKOUT_EN (1<<15)
  14. #define DP83630_PHY_RBR_REG 0x17
  15. static int dp83630_config(struct phy_device *phydev)
  16. {
  17. int ptp_coc_reg;
  18. phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET);
  19. phy_write(phydev, MDIO_DEVAD_NONE, DP83630_PHY_PAGESEL_REG, 0x6);
  20. ptp_coc_reg = phy_read(phydev, MDIO_DEVAD_NONE,
  21. DP83630_PHY_PTP_COC_REG);
  22. ptp_coc_reg &= ~DP83630_PHY_PTP_CLKOUT_EN;
  23. phy_write(phydev, MDIO_DEVAD_NONE, DP83630_PHY_PTP_COC_REG,
  24. ptp_coc_reg);
  25. phy_write(phydev, MDIO_DEVAD_NONE, DP83630_PHY_PAGESEL_REG, 0);
  26. genphy_config_aneg(phydev);
  27. return 0;
  28. }
  29. static struct phy_driver DP83630_driver = {
  30. .name = "NatSemi DP83630",
  31. .uid = 0x20005ce1,
  32. .mask = 0xfffffff0,
  33. .features = PHY_BASIC_FEATURES,
  34. .config = &dp83630_config,
  35. .startup = &genphy_startup,
  36. .shutdown = &genphy_shutdown,
  37. };
  38. /* DP83865 Link and Auto-Neg Status Register */
  39. #define MIIM_DP83865_LANR 0x11
  40. #define MIIM_DP83865_SPD_MASK 0x0018
  41. #define MIIM_DP83865_SPD_1000 0x0010
  42. #define MIIM_DP83865_SPD_100 0x0008
  43. #define MIIM_DP83865_DPX_FULL 0x0002
  44. /* NatSemi DP83865 */
  45. static int dp83865_config(struct phy_device *phydev)
  46. {
  47. phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET);
  48. genphy_config_aneg(phydev);
  49. return 0;
  50. }
  51. static int dp83865_parse_status(struct phy_device *phydev)
  52. {
  53. int mii_reg;
  54. mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_DP83865_LANR);
  55. switch (mii_reg & MIIM_DP83865_SPD_MASK) {
  56. case MIIM_DP83865_SPD_1000:
  57. phydev->speed = SPEED_1000;
  58. break;
  59. case MIIM_DP83865_SPD_100:
  60. phydev->speed = SPEED_100;
  61. break;
  62. default:
  63. phydev->speed = SPEED_10;
  64. break;
  65. }
  66. if (mii_reg & MIIM_DP83865_DPX_FULL)
  67. phydev->duplex = DUPLEX_FULL;
  68. else
  69. phydev->duplex = DUPLEX_HALF;
  70. return 0;
  71. }
  72. static int dp83865_startup(struct phy_device *phydev)
  73. {
  74. genphy_update_link(phydev);
  75. dp83865_parse_status(phydev);
  76. return 0;
  77. }
  78. static struct phy_driver DP83865_driver = {
  79. .name = "NatSemi DP83865",
  80. .uid = 0x20005c70,
  81. .mask = 0xfffffff0,
  82. .features = PHY_GBIT_FEATURES,
  83. .config = &dp83865_config,
  84. .startup = &dp83865_startup,
  85. .shutdown = &genphy_shutdown,
  86. };
  87. int phy_natsemi_init(void)
  88. {
  89. phy_register(&DP83630_driver);
  90. phy_register(&DP83865_driver);
  91. return 0;
  92. }