broadcom.c 6.7 KB

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  1. /*
  2. * Broadcom PHY drivers
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. *
  6. * Copyright 2010-2011 Freescale Semiconductor, Inc.
  7. * author Andy Fleming
  8. */
  9. #include <config.h>
  10. #include <common.h>
  11. #include <phy.h>
  12. /* Broadcom BCM54xx -- taken from linux sungem_phy */
  13. #define MIIM_BCM54xx_AUXCNTL 0x18
  14. #define MIIM_BCM54xx_AUXCNTL_ENCODE(val) (((val & 0x7) << 12)|(val & 0x7))
  15. #define MIIM_BCM54xx_AUXSTATUS 0x19
  16. #define MIIM_BCM54xx_AUXSTATUS_LINKMODE_MASK 0x0700
  17. #define MIIM_BCM54xx_AUXSTATUS_LINKMODE_SHIFT 8
  18. #define MIIM_BCM54XX_SHD 0x1c
  19. #define MIIM_BCM54XX_SHD_WRITE 0x8000
  20. #define MIIM_BCM54XX_SHD_VAL(x) ((x & 0x1f) << 10)
  21. #define MIIM_BCM54XX_SHD_DATA(x) ((x & 0x3ff) << 0)
  22. #define MIIM_BCM54XX_SHD_WR_ENCODE(val, data) \
  23. (MIIM_BCM54XX_SHD_WRITE | MIIM_BCM54XX_SHD_VAL(val) | \
  24. MIIM_BCM54XX_SHD_DATA(data))
  25. #define MIIM_BCM54XX_EXP_DATA 0x15 /* Expansion register data */
  26. #define MIIM_BCM54XX_EXP_SEL 0x17 /* Expansion register select */
  27. #define MIIM_BCM54XX_EXP_SEL_SSD 0x0e00 /* Secondary SerDes select */
  28. #define MIIM_BCM54XX_EXP_SEL_ER 0x0f00 /* Expansion register select */
  29. /* Broadcom BCM5461S */
  30. static int bcm5461_config(struct phy_device *phydev)
  31. {
  32. genphy_config_aneg(phydev);
  33. phy_reset(phydev);
  34. return 0;
  35. }
  36. static int bcm54xx_parse_status(struct phy_device *phydev)
  37. {
  38. unsigned int mii_reg;
  39. mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXSTATUS);
  40. switch ((mii_reg & MIIM_BCM54xx_AUXSTATUS_LINKMODE_MASK) >>
  41. MIIM_BCM54xx_AUXSTATUS_LINKMODE_SHIFT) {
  42. case 1:
  43. phydev->duplex = DUPLEX_HALF;
  44. phydev->speed = SPEED_10;
  45. break;
  46. case 2:
  47. phydev->duplex = DUPLEX_FULL;
  48. phydev->speed = SPEED_10;
  49. break;
  50. case 3:
  51. phydev->duplex = DUPLEX_HALF;
  52. phydev->speed = SPEED_100;
  53. break;
  54. case 5:
  55. phydev->duplex = DUPLEX_FULL;
  56. phydev->speed = SPEED_100;
  57. break;
  58. case 6:
  59. phydev->duplex = DUPLEX_HALF;
  60. phydev->speed = SPEED_1000;
  61. break;
  62. case 7:
  63. phydev->duplex = DUPLEX_FULL;
  64. phydev->speed = SPEED_1000;
  65. break;
  66. default:
  67. printf("Auto-neg error, defaulting to 10BT/HD\n");
  68. phydev->duplex = DUPLEX_HALF;
  69. phydev->speed = SPEED_10;
  70. break;
  71. }
  72. return 0;
  73. }
  74. static int bcm54xx_startup(struct phy_device *phydev)
  75. {
  76. /* Read the Status (2x to make sure link is right) */
  77. genphy_update_link(phydev);
  78. bcm54xx_parse_status(phydev);
  79. return 0;
  80. }
  81. /* Broadcom BCM5482S */
  82. /*
  83. * "Ethernet@Wirespeed" needs to be enabled to achieve link in certain
  84. * circumstances. eg a gigabit TSEC connected to a gigabit switch with
  85. * a 4-wire ethernet cable. Both ends advertise gigabit, but can't
  86. * link. "Ethernet@Wirespeed" reduces advertised speed until link
  87. * can be achieved.
  88. */
  89. static u32 bcm5482_read_wirespeed(struct phy_device *phydev, u32 reg)
  90. {
  91. return (phy_read(phydev, MDIO_DEVAD_NONE, reg) & 0x8FFF) | 0x8010;
  92. }
  93. static int bcm5482_config(struct phy_device *phydev)
  94. {
  95. unsigned int reg;
  96. /* reset the PHY */
  97. reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR);
  98. reg |= BMCR_RESET;
  99. phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, reg);
  100. /* Setup read from auxilary control shadow register 7 */
  101. phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXCNTL,
  102. MIIM_BCM54xx_AUXCNTL_ENCODE(7));
  103. /* Read Misc Control register and or in Ethernet@Wirespeed */
  104. reg = bcm5482_read_wirespeed(phydev, MIIM_BCM54xx_AUXCNTL);
  105. phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXCNTL, reg);
  106. /* Initial config/enable of secondary SerDes interface */
  107. phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_SHD,
  108. MIIM_BCM54XX_SHD_WR_ENCODE(0x14, 0xf));
  109. /* Write intial value to secondary SerDes Contol */
  110. phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_EXP_SEL,
  111. MIIM_BCM54XX_EXP_SEL_SSD | 0);
  112. phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_EXP_DATA,
  113. BMCR_ANRESTART);
  114. /* Enable copper/fiber auto-detect */
  115. phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_SHD,
  116. MIIM_BCM54XX_SHD_WR_ENCODE(0x1e, 0x201));
  117. genphy_config_aneg(phydev);
  118. return 0;
  119. }
  120. /*
  121. * Find out if PHY is in copper or serdes mode by looking at Expansion Reg
  122. * 0x42 - "Operating Mode Status Register"
  123. */
  124. static int bcm5482_is_serdes(struct phy_device *phydev)
  125. {
  126. u16 val;
  127. int serdes = 0;
  128. phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_EXP_SEL,
  129. MIIM_BCM54XX_EXP_SEL_ER | 0x42);
  130. val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_EXP_DATA);
  131. switch (val & 0x1f) {
  132. case 0x0d: /* RGMII-to-100Base-FX */
  133. case 0x0e: /* RGMII-to-SGMII */
  134. case 0x0f: /* RGMII-to-SerDes */
  135. case 0x12: /* SGMII-to-SerDes */
  136. case 0x13: /* SGMII-to-100Base-FX */
  137. case 0x16: /* SerDes-to-Serdes */
  138. serdes = 1;
  139. break;
  140. case 0x6: /* RGMII-to-Copper */
  141. case 0x14: /* SGMII-to-Copper */
  142. case 0x17: /* SerDes-to-Copper */
  143. break;
  144. default:
  145. printf("ERROR, invalid PHY mode (0x%x\n)", val);
  146. break;
  147. }
  148. return serdes;
  149. }
  150. /*
  151. * Determine SerDes link speed and duplex from Expansion reg 0x42 "Operating
  152. * Mode Status Register"
  153. */
  154. static u32 bcm5482_parse_serdes_sr(struct phy_device *phydev)
  155. {
  156. u16 val;
  157. int i = 0;
  158. /* Wait 1s for link - Clause 37 autonegotiation happens very fast */
  159. while (1) {
  160. phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_EXP_SEL,
  161. MIIM_BCM54XX_EXP_SEL_ER | 0x42);
  162. val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_EXP_DATA);
  163. if (val & 0x8000)
  164. break;
  165. if (i++ > 1000) {
  166. phydev->link = 0;
  167. return 1;
  168. }
  169. udelay(1000); /* 1 ms */
  170. }
  171. phydev->link = 1;
  172. switch ((val >> 13) & 0x3) {
  173. case (0x00):
  174. phydev->speed = 10;
  175. break;
  176. case (0x01):
  177. phydev->speed = 100;
  178. break;
  179. case (0x02):
  180. phydev->speed = 1000;
  181. break;
  182. }
  183. phydev->duplex = (val & 0x1000) == 0x1000;
  184. return 0;
  185. }
  186. /*
  187. * Figure out if BCM5482 is in serdes or copper mode and determine link
  188. * configuration accordingly
  189. */
  190. static int bcm5482_startup(struct phy_device *phydev)
  191. {
  192. if (bcm5482_is_serdes(phydev)) {
  193. bcm5482_parse_serdes_sr(phydev);
  194. phydev->port = PORT_FIBRE;
  195. } else {
  196. /* Wait for auto-negotiation to complete or fail */
  197. genphy_update_link(phydev);
  198. /* Parse BCM54xx copper aux status register */
  199. bcm54xx_parse_status(phydev);
  200. }
  201. return 0;
  202. }
  203. static struct phy_driver BCM5461S_driver = {
  204. .name = "Broadcom BCM5461S",
  205. .uid = 0x2060c0,
  206. .mask = 0xfffff0,
  207. .features = PHY_GBIT_FEATURES,
  208. .config = &bcm5461_config,
  209. .startup = &bcm54xx_startup,
  210. .shutdown = &genphy_shutdown,
  211. };
  212. static struct phy_driver BCM5464S_driver = {
  213. .name = "Broadcom BCM5464S",
  214. .uid = 0x2060b0,
  215. .mask = 0xfffff0,
  216. .features = PHY_GBIT_FEATURES,
  217. .config = &bcm5461_config,
  218. .startup = &bcm54xx_startup,
  219. .shutdown = &genphy_shutdown,
  220. };
  221. static struct phy_driver BCM5482S_driver = {
  222. .name = "Broadcom BCM5482S",
  223. .uid = 0x143bcb0,
  224. .mask = 0xffffff0,
  225. .features = PHY_GBIT_FEATURES,
  226. .config = &bcm5482_config,
  227. .startup = &bcm5482_startup,
  228. .shutdown = &genphy_shutdown,
  229. };
  230. int phy_broadcom_init(void)
  231. {
  232. phy_register(&BCM5482S_driver);
  233. phy_register(&BCM5464S_driver);
  234. phy_register(&BCM5461S_driver);
  235. return 0;
  236. }