ddr3_training_ip_db.h 621 B

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  1. /*
  2. * Copyright (C) Marvell International Ltd. and its affiliates
  3. *
  4. * SPDX-License-Identifier: GPL-2.0
  5. */
  6. #ifndef _DDR3_TRAINING_IP_DB_H_
  7. #define _DDR3_TRAINING_IP_DB_H_
  8. enum hws_pattern {
  9. PATTERN_PBS1,
  10. PATTERN_PBS2,
  11. PATTERN_RL,
  12. PATTERN_STATIC_PBS,
  13. PATTERN_KILLER_DQ0,
  14. PATTERN_KILLER_DQ1,
  15. PATTERN_KILLER_DQ2,
  16. PATTERN_KILLER_DQ3,
  17. PATTERN_KILLER_DQ4,
  18. PATTERN_KILLER_DQ5,
  19. PATTERN_KILLER_DQ6,
  20. PATTERN_KILLER_DQ7,
  21. PATTERN_PBS3,
  22. PATTERN_RL2,
  23. PATTERN_TEST,
  24. PATTERN_FULL_SSO0,
  25. PATTERN_FULL_SSO1,
  26. PATTERN_FULL_SSO2,
  27. PATTERN_FULL_SSO3,
  28. PATTERN_VREF,
  29. PATTERN_LIMIT
  30. };
  31. #endif /* _DDR3_TRAINING_IP_DB_H_ */